74ALVCH16373

74ALVCH16373 LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS s s s s s s s s s 3.6V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : tPD = 3.6 ns (MAX.) at VCC = 3.0 to 3.6V tPD = 4.5 ns (MAX.) at VCC = 2.3 to 2.7V tPD = 6.5 ns (MAX.) at VCC = 1.65V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3.0V |IOH| = IOL = 18mA (MIN) at VCC = 2.3V |IOH| = IOL = 4mA (MIN) at VCC = 1.65V OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V BUS HOLD PROVIDED ON DATA INPUTS PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R 74ALVCH16373TTR PIN CONNECTION DESCRIPTION The 74ALVCH16373 is a low voltage CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs. These 16 bit D-TYPE latches are bite controlled by two latch enable inputs (nLE) and two output enable inputs (OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.This device is designed to be used with 3 state memory address drivers, etc. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 1/11 74ALVCH16373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 SYMBOL 1OE NAME AND FUNCTION IEC LOGIC SYMBOLS 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2LE Latch Enable Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1LE Latch Enable Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE * L H X : Don‘t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level. 2/11 74ALVCH16373 LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (OFF State) DC Output Voltage (High or Low State) (note 1) DC Input Diode Current DC Output Diode Current (note 2) DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to VCC + 0.5 - 50 - 50 ± 50 ± 100 400 -65 to +150 300 Unit V V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current per Supply Pin Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND, VO > VCC RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO VO IOH, IOL IOH, IOL IOH, IOL Top dt/dv Supply Voltage Input Voltage Output Voltage (OFF State) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.3 to 2.7V) High or Low Level Output Current (VCC = 1.8V) Operating Temperature Input Rise and Fall Time (note 1) Parameter Value 1.65 to 3.6 -0.3 to 3.6 0 to 3.6 0 to VCC ± 24 ± 12 ±4 -55 to 125 0 to 10 Unit V V V V mA mA mA °C ns/V 1) VIN from 0.8V to 2V at VCC = 3.0V 3/11 74ALVCH16373 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 VOL Low Level Output Voltage 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 II IIHOLD Input Leakage Current Bus Hold Input Leakage Current 3.6 1.65 1.65 2.3 2.3 3.0 3.0 3.6 Ioff IOZ Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input 0 3.6 IO=-100 µA IO=-4 mA IO=-6 mA IO=-12 mA IO=-12 mA IO=-12 mA IO=-24 mA IO=100 µA IO=4 mA IO=6 mA IO=12 mA IO=12 mA IO=24 mA VI = 0 or 3.6V VI =0.58 V VI =1.07 V VI =0.7 V VI =1.7 V VI =0.8 V VI =2 V VI = 0 to 3.6V VI or VO = 3.6V VI = VIH or VIL VO = 0 to VCC VI = VCC or GND IO= 0 VIH = VCC - 0.6V + 25 - 25 + 45 - 45 + 75 - 75 ± 500 10 ±5 -40 to 85 °C Min. 0.65 Vcc 1.7 2.0 0.35 Vcc 0.7 0.8 VCC-0.2 1.2 2.0 1.7 2.2 2.4 2.0 0.2 0.45 0.4 0.7 0.4 0.55 ±5 + 25 - 25 + 45 - 45 + 75 - 75 ± 500 20 ± 10 µA µA µA µA µA VCC-0.2 1.2 2.0 1.7 2.2 2.4 2.0 0.2 0.45 0.4 0.7 0.4 0.55 ±5 µA V V Max. Value -55 to 125 °C Min. 0.65 Vcc 1.7 2.0 0.35 Vcc 0.7 0.8 Max. Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH ICC ∆ICC 3.6 3.0 to 3.6 20 500 40 750 4/11 74ALVCH16373 AC ELECTRICAL CHARACTERISTICS Test Condition Symbol Parameter VCC (V) CL (pF) 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 RL (Ω) 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 ts = tr (ns) 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 -40 to 85 °C Min. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.1 1.5 1.5 1.7 1.4 4 3.3 3.3 3.3 Max. 6.5 4.5 4.3 3.6 7.0 4.9 4.6 3.9 8.5 6 5.7 4.7 7 5.1 4.5 4.1 Value -55 to 125 °C Min. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.1 1.5 1.5 1.7 1.4 4 3.3 3.3 3.3 Max. 6.5 4.5 4.3 3.6 7.0 4.9 4.6 3.9 8.5 6 5.7 4.7 7 5.1 4.5 4.1 Unit tPLH tPHL Propagation Delay Time Dn to Qn 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPLH tPHL Propagation Delay 1.65 to 1.95 Time LE to Qn 2.3 to 2.7 2.7 3.0 to 3.6 tPZL tPZH Output Enable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 tPLZ tPHZ Output Disable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 ts Setup TIme, HIGH or 1.65 to 1.95 LOW level Dn to LE 2.3 to 2.7 2.7 3.0 to 3.6 th Hold Time High or 1.65 to 1.95 LOW level Dn to LE 2.3 to 2.7 2.7 3.0 to 3.6 tw LE Pulse Width, 1.65 to 1.95 HIGH 2.3 to 2.7 2.7 3.0 to 3.6 ns ns ns ns ns ns ns 5/11 74ALVCH16373 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 3.3 3.3 3.3 3.3 2.5 3.3 2.5 VIN =VCC or GND VIN =VCC or GND VIN = 0 to VCC fIN = 10MHz CL=50pF VIN = 0 or VCC Value TA = 25 °C Min. Typ. 3 6 7 19 16 5 4 Max. pF pF pF Unit CIN CIN COUT CPD CPD Input Capacitance Control Inputs Input Capacitance Data Inputs Output Capacitance Power Dissipation Capacitance Output enabled (note 1) Power Dissipation Capacitance Output disabled (note 1) pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per circuit) TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ (VCC = 3.0 to 3.6V) tPZL, tPLZ (VCC = 2.3 to 2.7V) tPZH, tPHZ RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open 6V 2VCC GND TEST CIRCUIT AND WAVEFORM SYMBOL VALUE Symbol 3.0 to 3.6V VIH VM VX VY CL RL=R1 tr = tr 6/11 2.7V 1.5V VOL +0.3V VOH -0.3V 50pF 500Ω