LMC6482
Datasheet
16 V CMOS dual rail-to-rail input and output, operational amplifiers
Features
MiniSO8
SO8
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Low input offset voltage: 2 mV max.
Rail-to-rail input and output
Excellent CMRR : 98 dB @ 16 V
Low current consumption: 900 µA max.
Gain bandwidth product: 2.7 MHz
Low supply voltage: 2.7 - 16 V
Unity gain stable
Low input bias current: 50 pA max.
High ESD tolerance: 4 kV HBM
Extended temp. range: -40 °C to +125 °C
Application
Maturity status link
LMC6482
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Data acquisition systems
Battery-powered instrumentation
Instrumentation amplifier
Active filtering
DAC buffer
High-impedance sensor interface
Current sensing (high and low side)
Description
The LMC6482 offer rail-to-rail input and output functionality allowing this product to
be used on full range input and output without limitation.
This rail to rail capability combined with excellent accuracy makes this device ideal
for systems such as data acquisition, that require wide input signal range.
This is particularly useful for a low-voltage supply such as 2.7 V that the LMC6482 is
able to operate with.
Thus, the LMC6482 has the great advantage of offering a large span of supply
voltages, ranging from 2.7 V to 16 V. It can be used in multiple applications with a
unique reference.
Low input bias current performance makes the LMC6482 perfect when used for
signal conditioning in sensor interface applications. In addition, low- side and highside current measurements can be easily made thanks to rail-to-rail functionality.
DS12573 - Rev 3 - October 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
LMC6482
Pin configuration
1
Pin configuration
Figure 1. Pin connection (top view)
DS12573 - Rev 3
OUT1
VCC+
IN1-
OUT2
IN1+
IN2-
VCC-
IN2+
page 2/24
LMC6482
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings
Symbol
Parameter
VCC
Supply voltage (1)
Vid
Differential input voltage (2)
Vin
Input voltage
Iin
Input current
Storage temperature
Rthja
Thermal resistance junction to ambient (4)(5)
18
V
±VCC
mV
(VCC-) - 0.2 to (VCC+) + 0.2
V
10
mA
-65 to 150
°C
MiniSO8
190
SO-8
125
Maximum junction temperature
HBM: Human body model
ESD
Unit
(3)
Tstg
Tj
Value
MM: machine model
150
(6)
°C/W
°C
4000
(7)
100
CDM: charged device model (8)
1500
Latch-up immunity
200
V
mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. See for the precautions
to follow when using LMC6482 with a high differential input voltage.
3. Input current must be limited by a resistor in series with the inputs.
4. Rth are typical values.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. According to JEDEC standard JESD22-A114F.
7. According to JEDEC standard JESD22-A115A.
8. According to ANSI/ESD STM5.3.1.
Table 2. Operating conditions
Symbol
DS12573 - Rev 3
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
2.7 to 16
(VCC-) - 0.1 to (VCC+) + 0.1
-40 to +125
Unit
V
°C
page 3/24
LMC6482
Electrical characteristics
3
Electrical characteristics
Table 3. Electrical characteristics VCC+ = +4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ
connected to VCC/2 (unless otherwise specified).
Symbol
Vio
Parameter
Input offset voltage
Conditions
Min.
Typ.
Vicm = VCC/2
2
Tmin < Top < Tmax
2.5
ΔVio/ΔT Input offset voltage drift (1)
ΔVio
Iib
Iio
Long term input offset voltage drift (2)
Input bias current (1)
Input offset current (1)
RIN
Input resistance
CIN
Input capacitance
CMRR
Avd
Common mode rejection ratio 20 log (ΔVic/ΔVio)
Large signal voltage gain
T = 25 °C
1
Vout = VCC/2
1
Tmin < Top < Tmax
Vout = VCC/2
1
Tmin < Top < Tmax
65
Tmin < Top < Tmax
60
RL = 2 kΩ, Vout= 0.3 to 3.7 V
85
Tmin < Top < Tmax
80
RL = 10 kΩ, Vout = 0.2 to 3.8 V
85
Tmin < Top < Tmax
80
Tmin < Top < Tmax
(voltage drop from VCC+)
RL = 10 kΩ tο VCC/2
Iout
Isource
ICC
85
136
140
6
23
5
15
Vout = 0 V
35
Tmin < Top < Tmax
20
No load, Vout = VCC/2
50
15
mV
37
mA
45
570
Tmin < Top < Tmax
SRn
mV
20
Tmin < Top < Tmax
Gm
15
60
25
Phase margin
50
20
Vout = VCC
ɸm
dB
60
RL = 10 kΩ tο VCC/2
RL = 10 kΩ, CL = 100 pF
pA
pF
Tmin < Top < Tmax
Gain bandwidth product
GBP
DS12573 - Rev 3
Supply current per amplifier
50
12.5
Tmin < Top < Tmax
Isink
50
nV
montℎ
TΩ
28
RL = 2 kΩ tο VCC/2
Low level output voltage
µV/°C
1
Tmin < Top < Tmax
VOL
mV
200
Vicm = -0.1 to 4.1 V, Vout = VCC/2
High level output voltage
Unit
5
200
RL=2 kΩ to VCC/2
VOH
Max.
800
900
1.9
µA
2.7
MHz
RL = 10 kΩ, CL = 100 pF
50
Degrees
Gain margin
RL = 10 kΩ, CL = 100 pF
15
dB
Negative slew rate
Av = 1, Vout = 3 VPP, 10 % to 90%
0.85
V/µs
0.6
page 4/24
LMC6482
Electrical characteristics
Symbol
Parameter
SRn
Negative slew rate
SRp
Positive slew rate
en
Equivalent input noise voltage
THD+N Total harmonic distortion + noise
Conditions
Min.
Tmin < Top < Tmax
0.5
Av = 1, Vout = 3 VPP, 10 % to 90%
1.0
Tmin < Top < Tmax
0.9
Typ.
Max.
Unit
1.4
V/µs
f = 1 kHz
22
f = 10 kHz
19
nV
Hz
0.001
%
f = 1 kHz, Av = 1, RL = 10 kΩ,
BW = 22 kHz, Vin = 0.8 VPP
1. Maximum values are guaranteed by design.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law
and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see
Section 5.6 Long term input offset voltage drift).
DS12573 - Rev 3
page 5/24
LMC6482
Electrical characteristics
Table 4. Electrical characteristics VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ
connected to VCC/2 (unless otherwise specified).
Symbol
Vio
Parameter
Input offset voltage
Conditions
Min.
Typ.
Vicm = VCC/2
2
Tmin < Top < Tmax
2.5
ΔVio/ΔT Input offset voltage drift (1)
ΔVio
Iib
Iio
Longterm input offset voltage drift (2)
Input bias current (1)
Input offset current (1)
RIN
Input resistance
CIN
Input capacitance
CMRR
Avd
Common mode rejectionratio 20 log (ΔVic/ΔVio)
Large signal voltage gain
T = 25 °C
25
Vout = VCC/2
1
Tmin < Top < Tmax
Vout = VCC/2
1
Tmin < Top < Tmax
72
Tmin < Top < Tmax
67
RL = 2 kΩ, Vout= 0.3 to 9.7 V
90
Tmin < Top < Tmax
85
RL = 10 kΩ, Vout = 0.2 to 9.8 V
90
Tmin < Top < Tmax
85
Tmin < Top < Tmax
(voltage drop from VCC+)
RL = 10 kΩ tο VCC/2
Iout
Isource
ICC
92
140
10
42
9
15
Vout = 0 V
50
Tmin < Top < Tmax
40
No load, Vout = VCC/2
SRn
Negative slew rate
SRp
Positive slew rate
70
30
mV
39
mA
69
630
Tmin < Top < Tmax
Gain margin
mV
40
Tmin < Top < Tmax
Gm
30
80
30
Phase margin
70
40
Vout = VCC
ɸm
dB
80
RL = 10 kΩ tο VCC/2
RL = 10 kΩ, CL = 100 pF
pA
pF
Tmin < Top < Tmax
Gain bandwidth product
GBP
DS12573 - Rev 3
Supply current per amplifier
50
12.5
Tmin < Top < Tmax
Isink
50
nV
montℎ
TΩ
45
RL = 2 kΩ tο VCC/2
Low level output voltage
µV/°C
1
Tmin < Top < Tmax
VOL
mV
200
Vicm = -0.1 to 10.1 V, Vout = VCC/2
High level output voltage
Unit
5
200
RL=2 kΩ to VCC/2
VOH
Max.
850
1000
1.9
µA
2.7
MHz
RL = 10 kΩ, CL = 100 pF
53
Degrees
RL = 10 kΩ, CL = 100 pF
15
dB
Av = 1, Vout = 8 VPP, 10 % to 90%
0.8
Tmin < Top < Tmax
0.7
Av = 1, Vout = 8 VPP, 10 % to 90%
1.0
1
V/µs
1.3
page 6/24
LMC6482
Electrical characteristics
Symbol
SRp
en
Parameter
Positive slew rate
Equivalent input noise voltage
THD+N Total harmonic distortion + noise
Conditions
Tmin < Top < Tmax
Min.
Typ.
Max.
Unit
V/µs
0.9
f = 1 kHz
22
f = 10 kHz
19
nV
Hz
0.0003
%
f = 1 kHz, Av = 1, RL = 10 kΩ,
BW = 22 kHz, Vin = 5 VPP
1. Maximum values are guaranteed by design.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law
and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see
Section 5.6 Long term input offset voltage drift).
DS12573 - Rev 3
page 7/24
LMC6482
Electrical characteristics
Table 5. Electrical characteristics VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ
connected to VCC/2 (unless otherwise specified).
Symbol
Vio
ΔVio/ΔT
ΔVio
Iib
Iio
Parameter
Input offset voltage
Longterm input offset voltage drift (2)
Input bias current (1)
Input offset current (1)
Input resistance
CIN
Input capacitance
SVRR
Avd
Min.
Vicm = VCC/2
Tmin < Top < Tmax
2.5
T = 25 °C
Vout = VCC/2
1
Tmin < Top < Tmax
1
Tmin < Top < Tmax
75
20 log (ΔVic/ΔVio)
Tmin < Top < Tmax
70
Supply voltage rejection ratio
Vcc = 4 to 16 V
100
20 log (ΔVcc/ΔVio)
Tmin < Top < Tmax
90
RL = 2 kΩ, Vout= 0.3 to 15.7 V
90
Tmin < Top < Tmax
85
RL = 10 kΩ, Vout = 0.2 to 15.8 V
90
Tmin < Top < Tmax
85
Tmin < Top < Tmax
(voltage drop from VCC+)
RL = 10 kΩ
12.5
pF
98
131
Iout
Isource
ICC
149
16
70
15
Tmin < Top < Tmax
15
Vout = 0 V
50
Tmin < Top < Tmax
45
No load, Vout = VCC/2
SRn
mV
40
mA
68
660
Tmin < Top < Tmax
Gm
40
50
30
Phase margin
mV
130
150
Vout = VCC
ɸm
40
50
RL = 10 kΩ
RL = 10 kΩ, CL = 100 pF
130
150
Tmin < Top < Tmax
Gain bandwidth product
GBP
DS12573 - Rev 3
Supply current per amplifier
dB
146
Tmin < Top < Tmax
Isink
pA
TΩ
70
RL = 2 kΩ
Low level output voltage
50
1
Tmin < Top < Tmax
VOL
50
nV
montℎ
200
Vicm = -0.1 to 16.1 V, Vout = VCC/2
High level output voltage
mV
µV/°C
200
Vout = VCC/2
Unit
5
500
Common mode rejection ratio
Large signal voltage gain
Max.
2
RL = 2 kΩ to V/2
VOH
Typ.
Input offset voltage drift (1)
RIN
CMRR
Conditions
900
1000
1.9
µA
2.7
MHz
RL = 10 kΩ, CL = 100 pF
55
Degrees
Gain margin
RL = 10 kΩ, CL = 100 pF
15
dB
Negative slew rate
Av = 1, Vout = 10 VPP, 10 % to 90%
0.95
V/µs
0.7
page 8/24
LMC6482
Electrical characteristics
Symbol
Parameter
SRn
Negative slew rate
SRp
Positive slew rate
en
THD+N
Equivalent input noise voltage
Total harmonic distortion + noise
Conditions
Tmin < Top < Tmax
Min.
Typ.
Max.
Unit
0.6
1.4
V/µs
f = 1 kHz
22
f = 10 kHz
19
nV
Hz
0.0002
%
Av = 1, Vout = 10 VPP, 10 % to 90%
Tmin < Top < Tmax
f = 1 kHz, Av = 1, RL = 10 kΩ,
BW = 22 kHz, Vin = 10 VPP
1
0.9
1. Maximum values are guaranteed by design.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law
and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see
Section 5.6 Long term input offset voltage drift).
DS12573 - Rev 3
page 9/24
LMC6482
Electrical characteristic curves
4
Electrical characteristic curves
Figure 3. Input offset voltage distribution at VCC = 16 V
Figure 2. Supply current vs. supply voltage
800
30
Vicm=Vcc/2
Vcc=16V
Vicm=8V
T=25°C
25
Population (%)
Supply Current (µA)
600
T=-40°C
400
T=25°C
T=125°C
20
15
10
200
5
0
0
2
4
6
8
10
Supply Voltage (V)
12
14
0
-2.0
16
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
Input offset voltage (mV)
Figure 4. Input offset voltage distribution at VCC = 4 V
Figure 5. Channel separation
140
30
Vcc=4V
Vicm=2V
T=25°C
0
Channel separation (dB)
25
Population (%)
-1.6
20
15
10
5
0
80
60
40
20
0
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
0
10
2.0
Input offset voltage (mV)
100
1k
10k
100k
1M
Frequency (Hz)
Figure 6. Output current vs. output voltage at VCC = 2.7 V
Figure 7. Output current vs. output voltage at VCC = 16 V
100
30
20
Vcc=16V
Vicm=8V
Gain=1
Vin=2Vpp
T=25ºC
Sink
75 Vid=-1V
Sink
Vid=-1V
0
T=125°C
T=25°C
T=-40°C
-10
-20
-30
0.0
DS12573 - Rev 3
Source
Vid=1V
Vcc=2.7V
0.5
1.0
1.5
Output Voltage (V)
2.0
2.5
Output Current (mA)
Output Current (mA)
50
10
25
0
T=125°C
T=25°C
T=-40°C
-25
-50
-75
-100
0
Source
Vid=1V
Vcc=16V
2
4
6
8
10
Output Voltage (V)
12
14
16
page 10/24
LMC6482
Electrical characteristic curves
Figure 8. Output low voltage vs. supply voltage
Figure 9. Output high voltage (drop from VCC+) vs. supply
voltage
30
T=-40°C
Output voltage (from Vcc+) (mV)
Output voltage (mV)
30
Vid=-0.1V
Rl=10kΩ to Vcc/2
25
T=25°C
20
T=125°C
15
10
5
0
4
6
8
10
12
Supply Voltage (V)
14
T=25°C
T=125°C
15
10
5
4
1.5
15.90
1.0
15.85
0.5
Slew rate (V/µs)
15.95
15.80
0.15
16.00
15.95
15.90
15.85
15.80
0.15
0.10
0.05
0.00
14
16
T=25°C
T=125°C
T=-40°C
-0.5
Vicm=Vcc/2
Vload=Vcc/2
Rl=10kΩ
Cl=100pF
4
6
8
10
12
Supply Voltage (V)
14
16
Figure 13. Positive slew rate at VCC = 16 V
6
6
Vcc=16V
Vicm=Vcc/2
Rl=10kΩ
Cl=100pF
2
T=-40°C
0
T=25°C
-2
4
Signal Amplitude (V)
4
Signal Amplitude (V)
0.0
-2.0
Figure 12. Negative slew rate at VCC = 16 V
T=125°C
2
T=125°C
0
T=25°C
-2
T=-40°C
Vcc=16V
Vicm=Vcc/2
Rl=10kΩ
Cl=100pF
-4
-4
DS12573 - Rev 3
12
-1.5
0.00
-6
-2
10
-1.0
Vcc=16V
Follower configuration
Input voltage (V)
8
Figure 11. Slew rate vs. supply voltage
2.0
0.05
6
Supply Voltage (V)
16.00
0.10
T=-40°C
20
0
16
Figure 10. Output voltage vs. input voltage close to the
rail at VCC = 16 V
Output voltage (V)
Vid=0.1V
Rl=10kΩ to Vcc/2
25
0
2
4
6
8 10
Time (µs)
12
14
16
18
-6
-2
0
2
4
6
8 10
Time (µs)
12
14
16
18
page 11/24
LMC6482
Electrical characteristic curves
Figure 15. Recovery behavior after a negative step on the
input
0.10
Vin
0.00
-0.05
-0.10
0
5
Time (µs)
10
6
0
0.00
0.04
0
0.00
-2
-10
0
10
20
Time (µs)
-0.04
40
30
Figure 17. Bode diagram at VCC = 2.7 V
60
0
Phase
50
-30
40
-60
Gain
30
-4
-0.08
Vcc=±8V
-6
-0.12
Gain=101
Rl=10kΩ
Cl=100pF
T=25°C
Vin
-8
-10
-10
0
10
20
Time (µs)
30
-0.16
-0.20
40
20
10
50
-120
-150
Vcc=2.7V
Vicm=1.35V
Rl=10kΩ
Cl=100pF
Gain=101
0
-10
T=25°C
-180
-210
T=125°C
-20
1k
10k
100k
-240
10M
1M
Frequency (Hz)
0
Phase
-90
T=-40°C
Figure 19. Power supply rejection ratio (PSRR) vs.
frequency
Figure 18. Bode diagram at VCC = 16 V
60
Gain (dB)
-0.04
Vcc=±1.35V
Phase(°)
-2
Input voltage (V)
Output Voltage (V)
0.08
Vcc=±1.35V
2
Figure 16. Recovery behavior after a positive step on the
input
0.04
Vcc=±8V
4
15
2
0.20
Gain=101
Rl=10kΩ
0.16
Cl=100pF
T=25°C
0.12
8
Output Voltage (V)
0.05
Signal Amplitude (V)
10
Vcc=16V
Vicm=8V
Rl=10kΩ
Cl=100pF
T=25°C
Input voltage (V)
Figure 14. Response to a small input voltage step
120
-30
100
40
-60
PSRR+
Gain
80
20
10
-150
Vcc=16V
Vicm=8V
Rl=10kΩ
Cl=100pF
Gain=101
0
-10
-120
T=25°C
-180
-210
T=125°C
-20
1k
10k
100k
Frequency (Hz)
DS12573 - Rev 3
1M
-240
10M
PSRR (dB)
-90
T=-40°C
Phase(°)
Gain (dB)
30
60
40
20
0
10
Vcc=16V
Vicm=8V
Gain=1
Rl=10kΩ
Cl=100pF
Vosc=200mVPP
T=25°C
100
PSRR1k
10k
Frequency (Hz)
100k
1M
page 12/24
LMC6482
Electrical characteristic curves
Figure 20. Output overshoot vs. capacitive load
Figure 21. Output impedance vs. frequency in closed loop
configuration
200
10000
Vicm=Vcc/2
Rl=10kΩ
Vin=100mVpp
Gain=1
T=25°C
Overshoot (%)
150
125
1000
Vcc=16V
Output impedance ( W )
175
100
Vcc=2.7V
75
50
100
10
1
25
0
10
100
Cload (pF)
0.1
1k
1000
1
0.1
Rl=100kΩ
100
Rl=10kΩ
Rl=2kΩ
1E-3
1000
Frequency (Hz)
10000
Rl=100kΩ
Vcc=16V
Vicm=8V
Gain=1
f=1kHz
BW=22kHz
T=25°C
0.1
1
Output Voltage (Vpp)
10
Figure 25. 0.1 to 10 Hz noise
6
120
Vcc=16V
Vicm=Vcc/2
T=25°C
100
80
60
40
Vcc=16V
4 Vicm=8V
T=25°C
Input voltage noise (µV)
Equivalent Input Noise Voltage (nV/VHz)
Rl=2kΩ
1E-4
0.01
140
2
0
-2
-4
20
DS12573 - Rev 3
10M
0.01
Figure 24. Noise vs. frequency
0
10
1M
Rl=10kΩ
THD + N (%)
THD + N (%)
1E-4
100k
Frequency (Hz)
1
Vcc=16V
Vicm=8V
Gain=1
Vin=10Vpp
BW=80kHz
T=25°C
0.01
1E-3
10k
Figure 23. THD + N vs. output voltage
Figure 22. THD + N vs. frequency
0.1
Vcc=16V
Vicm=8V
Gain=1
Vosc=30mVRMS
T=25°C
100
1k
Frequency (Hz)
10k
-6
0
2
4
Time (s)
6
8
10
page 13/24
LMC6482
Application information
5
Application information
5.1
Operating voltages
The LMC6482 device can operate from 2.7 to 16 V. The parameters are fully specified for 4 V, 10 V, and
16 V power supplies. However, the parameters are very stable in the full VCC range. Additionally, the main
specifications are guaranteed in extended temperature ranges from -40 to 125 °C.
5.2
Input pin voltage ranges
The LMC6482 device have internal ESD diode protection on the inputs. These diodes are connected between the
input and each supply rail to protect the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this over current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in
figure below.
Figure 26. Input current limitation
16 V
R
Vin
5.3
-
+
+
-
Vout
Rail-to-rail input
The LMC6482 device have a rail-to-rail input, and the input common mode range is extended from (VCC-) - 0.1 V
to (VCC+) + 0.1 V.
5.4
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 40 mV above and below the rail
when connected to a 10 kΩ resistive load to VCC/2.
5.5
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
ΔVio
Vio T − Vio 25°C
ΔT = max
T − 25°C
(1)
where T = -40 °C and 125 °C.
The LMC6482 datasheet maximum values are guaranteed by measurements on a representative sample size
ensuring a Cpk (process capability index) greater than 1.3.
DS12573 - Rev 3
page 14/24
LMC6482
Long term input offset voltage drift
5.6
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by
the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
AFV = ϵβ.VS − VU
where:
AFV is the voltage acceleration factor
(2)
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3
Where:
AFT is the temperature acceleration factor
Ea 1
1
AFT = e k . TU − TS
(3)
Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5
eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4)
AF = AFT × AFV
(4)
Montℎs = AF × 1000 ℎ × 12 montℎs/ 24 ℎ × 365.25 days
(5)
VCC = max VPP witℎ Vicm = VCC /2
(6)
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in to calculate the number of months of use equivalent to 1000 hours of reliable stress duration.
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
conditions (see equation 6)
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the
ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation
7)
ΔVio =
Vio drift
montℎs
(7)
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
5.7
High values of input differential voltage
In a closed loop configuration, which represents the typical use of an op amp, the input differential voltage is low
(close to Vio). However, some specific conditions can lead to higher input differential values, such as:
operation in an output saturation state
operation at speeds higher than the device bandwidth, with output voltage dynamics limited by slew rate.
use of the amplifier in a comparator configuration, hence in open loop
DS12573 - Rev 3
page 15/24
LMC6482
Capacitive load
Use of the LMC6482 in comparator configuration, especially combined with high temperature and long duration
can create a permanent drift of Vio.
5.8
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.
Figure below "Stability criteria with a serial resistor at different supply voltage" shows the serial resistor that must
be added to the output, to make a system stable. The Figure 28. Test configuration for Riso shows the test
configuration using an isolation resistor, Riso.
Figure 27. Stability criteria with a serial resistor at different supply voltage
1000
Vcc=16V
Riso ( W )
Stable
Vcc=2.7V
100
Unstable
Vicm=Vcc/2
Rl=10kΩ
Gain=1
T=25°C
10
100p
1n
Cload (F)
10n
100n
Figure 28. Test configuration for Riso
V CC+
Riso
VIN
+
V CC-
5.9
Cload
VOUT
10 kΩ
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for
all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.
5.10
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help
to reduce electromagnetic interference impact.
DS12573 - Rev 3
page 16/24
LMC6482
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
6.1
MiniSO8 package information
Figure 29. MiniSO8 package outline
Table 6. MiniSO8 mechanical data
Dim.
Millimeters
Min.
Inches
Typ.
A
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.03
0.22
0.4
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.8
3
3.2
0.11
0.118
0.126
E
4.65
4.9
5.15
0.183
0.193
0.203
E1
2.8
3
3.1
0.11
0.118
0.122
e
L
0.85
0.65
0.4
0.6
0.006
0.033
0.8
0.016
0.024
0.95
0.037
L2
0.25
0.01
k
0°
0.037
0.026
L1
ccc
DS12573 - Rev 3
Max.
8°
0.1
0°
0.031
8°
0.004
page 17/24
LMC6482
SO8 package information
6.2
SO8 package information
Figure 30. SO8 package outline
Table 7. SO-8 mechanical data
Dim.
Millimeters
Min.
Inches
Typ.
A
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.01
D
4.8
4.9
5
0.189
0.193
0.197
E
5.8
6
6.2
0.228
0.236
0.244
E1
3.8
3.9
4
0.15
0.154
0.157
e
0.004
0.01
0.049
1.27
0.05
h
0.25
0.5
0.01
0.02
L
0.4
1.27
0.016
0.05
L1
k
ccc
DS12573 - Rev 3
Max.
1.04
0
0.04
8°
0.1
1°
8°
0.004
page 18/24
LMC6482
Ordering information
7
Ordering information
Table 8. Order code
Order code
LMC6482IDT
LMC6482IST
DS12573 - Rev 3
Temperature range
-40 ° to +125 °C
Package
SO8
MiniSO8
Packing
Tape and reel
Marking
LMC6482
6482
page 19/24
LMC6482
Revision history
Table 9. Document revision history
DS12573 - Rev 3
Date
Revision
Changes
24-Jul-2018
1
Initial release.
12-Sep-2018
2
Updated the temperature range value in Table 8. Order code.
26-Oct-2021
3
Added Marking column in Table 8. Order code.
page 20/24
LMC6482
Contents
Contents
1
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6
7
5.1
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4
Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.7
High values of input differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.8
Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.9
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.10
Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.1
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DS12573 - Rev 3
page 21/24
LMC6482
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics VCC+ = +4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to
VCC/2 (unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to
VCC/2 (unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to
VCC/2 (unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MiniSO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DS12573 - Rev 3
page 22/24
LMC6482
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
DS12573 - Rev 3
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 16 V . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 4 V . . . . . . . . . . . . . .
Channel separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current vs. output voltage at VCC = 2.7 V . . . . . . . . . . .
Output current vs. output voltage at VCC = 16 V . . . . . . . . . . .
Output low voltage vs. supply voltage . . . . . . . . . . . . . . . . . .
Output high voltage (drop from VCC+) vs. supply voltage . . . . .
Output voltage vs. input voltage close to the rail at VCC = 16 V .
Slew rate vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Negative slew rate at VCC = 16 V . . . . . . . . . . . . . . . . . . . . .
Positive slew rate at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . .
Response to a small input voltage step . . . . . . . . . . . . . . . . .
Recovery behavior after a negative step on the input . . . . . . . .
Recovery behavior after a positive step on the input . . . . . . . .
Bode diagram at VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . .
Power supply rejection ratio (PSRR) vs. frequency . . . . . . . . .
Output overshoot vs. capacitive load . . . . . . . . . . . . . . . . . . .
Output impedance vs. frequency in closed loop configuration . .
THD + N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THD + N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.1 to 10 Hz noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stability criteria with a serial resistor at different supply voltage .
Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . . . .
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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page 23/24
LMC6482
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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