M28010-20WBA6T

M28010 1 Mbit (128K x 8) Parallel EEPROM With Software Data Protection PRELIMINARY DATA s s Fast Access Time: 100 ns Single Supply Voltage: – 4.5 V to 5.5 V for M28010 – 2.7 V to 3.6 V for M28010-W – 1.8 V to 2.4 V for M28010-R 32 s s s Low Power Consumption Fast BYTE and PAGE WRITE (up to 128 Bytes) Enhanced Write Detection and Monitoring: – Data Polling – Toggle Bit – Page Load Timer Status PDIP32 (BA) 1 s s s s s s JEDEC Approved Bytewide Pin-Out Software Data Protection Hardware Data Protection Software Chip Erase 100000 Erase/Write Cycles (minimum) Data Retention (minimum): 10 Years PLCC32 (KA) TSOP32 (NA) 8 x 20 mm DESCRIPTION The M28010 devices consist of 128Kx8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics’ proprietary double polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply (5V, 3V or 2V, depending on the option chosen). Table 1. Signal Names A0-A16 DQ0-DQ7 W E G VCC VSS Address Input Data Input / Output Write Enable Figure 1. Logic Diagram VCC 17 A0-A16 8 DQ0-DQ7 W E G M28010 Chip Enable Output Enable Supply Voltage Ground VSS AI02221 February 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/23 M 28010 Figure 2A. DIP Connections DU A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 M28010 25 24 23 22 21 20 19 18 17 AI02222 Figure 2C. TSOP Connections VCC W DU A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A11 A9 A8 A13 A14 DU W VCC DU A16 A15 A12 A7 A6 A5 A4 1 32 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 8 9 M28010 25 24 16 17 AI02224 Note: 1. DU = Do Not Use Note: 1. DU = Do Not Use Figure 2B. PLCC Connections A12 A15 A16 DU VCC W DU 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 G A10 E DQ7 9 M28010 25 data retention. The organization of the data in a 4 byte (32-bit) “word” format leads to significant savings in power consumption. Once a byte has been read, subsequent byte read cycles from the same “word” (with addresses differing only in the two least significant bits) are fetched from the previously loaded Read Buffer, not from the memory array. As a result, the power consumption for these subsequent read cycles is much lower than the power consumption for the first cycle. By careful design of the memory access patterns, a 50% reduction in the power consumption is possible. SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A16). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers, and is used to initiate read operations. 17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 AI02223 Note: 1. DU = Do Not Use The device has been designed to offer a flexible microcontroller interface, featuring both hardware and software hand-shaking, with Data Polling and Toggle Bit. The device supports a 128 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm. The M28010 is designed for applications requiring as much as 100,000 write cycles and ten years of 2/23 M28010 Table 2. Absolute Maximum Ratings 1 Symbol TA T STG VCC VIO VI VESD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage (except A9) Input Voltage Electrostatic Discharge Voltage (Human Body model) 2 Value –40 to 85 –65 to 150 –0.3 to VCCMAX+1 –0.3 to V CC+0.6 –0.3 to 4.5 2000 Unit °C °C V V V V Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω) Figure 3. Block Diagram A7-A16 (Page Address) ADDRESS LATCH X DECODE 1Mbit ARRAY A0-A6 ADDRESS LATCH LATCH PAGE Y DECODE REFERENCES VPP GEN VREAD GEN SENSE PAGE & DATA LATCH E G W CONTROL LOGIC PROGRAMMING STATE MACHINE ECC (1) & MULTIPLEXER I/O BUFFERS DQ0-DQ7 AI02225 3/23 M 28010 Table 3. Operating Modes 1 Mode Read Write Stand-by / Write Inhibit Write Inhibit Write Inhibit Output Disable Note: 1. X = VIH or VIL. E VIL VIL V IH X X X G V IL VIH X X V IL VIH W VIH VIL X VIH X X DQ0-DQ7 Data Out Data In Hi-Z Data Out or Hi-Z Data Out or Hi-Z Hi-Z Write Enable (W). The Write Enable input controls whether the addressed location is to be read, from or written to. DEVICE OPERATION In order to prevent data corruption and inadvertent write operations, an internal VCC comparator inhibits the Write operations if the V CC voltage is lower than VWI (see Table 4A to Table 4C). Once the voltage applied on the VCC pin goes over the Table 4A. Power-Up Timing1 for M28010 (5V range) (TA = –40 to 85 °C; VCC = 4.5 to 5.5 V) Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation VWI threshold (VCC>VWI), write access to the memory is allowed after a time-out tPUW, as specified in Table 4A to Table 4C. Further protection against data corruption is offered by the E and W low pass filters: any glitch, on the E and W inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory. Min. 5 5 3.0 Max. Unit ms ms Time Delay to Write Operation (once VCC ≥ VWI) Write Inhibit Threshold 4.2 V Note: 1. Sampled only, not 100% tested. Table 4B. Power-Up Timing1 for M28010-W (3V range) (TA = –40 to 85 °C; VCC = 2.7 to 3.6 V) Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC ≥ VWI) Write Inhibit Threshold Min. 5 5 2.0 2.6 Max. Unit ms ms V Note: 1. Sampled only, not 100% tested. Table 4C. Power-Up Timing1 for M28010-R (2V range) (TA = –40 to 85 °C; VCC = 1.8 to 2.4 V) Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC ≥ VWI) Write Inhibit Threshold Min. 5 5 1.2 1.7 Max. Unit ms ms V Note: 1. Sampled only, not 100% tested. 4/23 M28010 Read The device is accessed like a static RAM. When E and G are low, and W is high, the contents of the addressed location are presented on the I/O pins. Otherwise, when either G or E is high, the I/O pins revert to their high impedance state. Write Write operations are initiated when both W and E are low and G is high. The device supports both W-controlled and E-controlled write cycles (as shown in Figure 12 and Figure 13). The address is latched during the falling edge of W or E (which ever occurs later) and the data is latched on the rising edge of W or E (which ever occurs first). After a delay, tWLQ5H, that cannot be shorter than the value specified in Table 9A to Table 9C, the internal write cycle starts. It continues, under internal timing control, until the write operation is complete. The commencement of this period can be detected by reading the Page Load Timer Status on DQ5. The end of the internal write cycle Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write) SDP is Disabled and Application needs to Enable it, and Write Data SDP is Disabled and Application needs to Enable it Write AAh in Address 5555h Page Write Timing Write AAh in Address 5555h Write 55h in Address 2AAAh Page Write Timing Write 55h in Address 2AAAh Write A0h in Address 5555h Write A0h in Address 5555h Write is enabled Time Out (tWLQ5H) Write data in any addresses within one page Wait for write completion (tQ5HQ5X) SDP is set Write AAh in Address 5555h Time Out (tWLQ5H) Wait for write completion (tQ5HQ5X) DATA has been written and SDP is Enabled Write 55h in Address 2AAAh Page Write Timing Write A0h in Address 5555h Write is enabled Write data in any addresses within one page Time Out (tWLQ5H) Wait for write completion (tQ5HQ5X) DATA has been written and SDP is Enabled AI02227B 5/23 M 28010 Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write) SDP is Enabled and Application needs to Disable it SDP is Enabled and Application needs to Write Data Write AAh in Address 5555h Write AAh in Address 5555h Write 55h in Address 2AAAh Write 55h in Address 2AAAh Page Write Timing Write 80h in Address 5555h Page Write Timing Write 80h in Address 5555h Write AAh in Address 5555h Write AAh in Address 5555h Write 55h in Address 2AAAh Write 55h in Address 2AAAh Write 20h in Address 5555h Write 20h in Address 5555h Time Out (tWLQ5H) Physical Write Instructions Write data in any addresses within one page Wait for write completion (tQ5HQ5X) SDP is Disabled Time Out (tWLQ5H) Wait for write completion (tQ5HQ5X) DATA has been written and SDP is Disabled AI02226B can be detected by reading the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6. Page Write The Page Write mode allows up to 128 bytes to be written on a single page in a single go. This is achieved through a series of successive Write operations, no two of which are separated by more than the tWLQ5H value (as specified in Table 9A to Table 9C). The page write can be initiated during any byte write operation. Following the first Byte Write instruction, the host may send another address and data with a minimum data transfer rate of: 1/t WLQ5H. The internal write cycle can start at any instant after tWLQ5H. Once initiated, the write operation is 6/23 internally timed, and continues, uninterrupted, until completion. All bytes must be located on the same page address (A16-A7 must be the same for all bytes). Otherwise, the Page Write operation is not executed. The Page Write Abort event is indicated to the application via DQ1 (as described on page 8). As with the single byte Write operation, described above, the DQ5, DQ6 and DQ7 lines can be used to detect the beginning and end of the internally controlled phase of the Page Write cycle. Software Data Protection (SDP) The device offers a software-controlled writeprotection mechanism that allows the user to inhibit all write operations to the device, including chip erase. This can be useful for protecting the M28010 Figure 6. Software Chip Erase Algorithm Write AAh in Address 5555h Figure 7. Status Bit Assignment DQ7 DP DQ6 TB DQ5 PLTS DQ4 X DQ3 X DQ2 X DQ1 PWA DQ0 SDP Write 55h in Address 2AAAh Page Write Timing Write 80h in Address 5555h DP TB PLTS X PWA SDP = Data Polling = Toggle Bit = Page Load Timer Status = undefined = Page Write Abort = Software Data Protection AI02486B Write AAh in Address 5555h Write 55h in Address 2AAAh Figure 8. Software Data Protection Status Read Algorithm Write 10h in Address 5555h Write AAh in Address 5555h Page Write Timing Time Out (tWLQ5H) Write 55h in Address 2AAAh Wait for write completion (tQ5HQ5X) Whole Array has been Set to FFh Write 20h in Address 5555h AI02236C Read SDP on DQ0 memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). By default, the device is shipped in the “unprotected” state: the memory contents can be freely changed by the user. Once the Software Data Protection Mode is enabled, all write commands are ignored, and have no effect on the memory contents. The device remains in this mode until a valid Software Data Protection disable sequence is received. The device reverts to its “unprotected” state. The status of the Software Data Protection (enabled or disabled) is represented by a nonvolatile latch, and is remembered across periods of the power being off. The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in Figure 4. Write xxh in Address xxxxh Normal User Mode AI02237B Similarly, to disable the Software Data Protection, the user has to write specific data bytes into six different locations, as shown in Figure 5. This complex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism. When SDP is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inadvertent use). The sequence is as shown in Figure 5. This consists of an unlock key, to enable the write action, at the end of which the SDP continues to be enabled. This allows the SDP to be enabled, and data to be written, within a single Write cycle (tWC). 7/23 M 28010 Software Chip Erase The device can be erased (with all bytes set to FFh) by using a six-byte software command code. This operation can be initiated only if the user loads, with a Page Write addressing mode, six specific data bytes to six specific locations (as shown in Figure 6). The complexity of the sequence has been designed to guard against inadvertent use of the command. Status Bits The devices provide five status bits (DQ7, DQ6, DQ5, DQ1 and DQ0) for use during write operations. These allow the application to use the write time latency of the device for getting on with other work. These signals are available on the I/O port bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only during the internal write cycle, tQ5HQ5X). Data Polling bit (DQ7). The internally timed write cycle starts as soon as tWLQ5H (defined in Table 9A to Table 9C) has elapsed since the previous byte was latched in to the memory. The value of the DQ7 bit of this last byte, is used as a signal throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its original value once the operation is complete. Toggle bit (DQ6). The device offers another way for determining when the internal write cycle is running. During the internal write cycle, DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read value being ’0’) on subsequent attempts to read any byte of the memory. When the internal write cycle is complete, the toggling is stopped, and the values read on DQ7-DQ0 are those of the addressed memory byte. This indicates that the device is again available for new Read and Write operations. Page Load Timer Status bit (DQ5). An internal timer is used to measure the period between successive Write operations, up to tWLQ5H (defined in Table 9A to Table 9C). The DQ5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). The DQ5 line is held high when the counter has overflowed (hence showing that the device is now starting the internal write to the memory array). Page Write Abort bit (DQ1). During a page write operation, the A16 to A7 signals should be kept constant. They should not change while successive data bytes are being transferred to the internal latches of the memory device. If a change occurs on any of the pins, A16 to A7, during the page write operation (that is, before the falling edge of W or E, which ever occurs later), the internal write cycle is not started, and the internal circuitry is completely reset. The abort signal can be observed on the DQ1 pin, using a normal read operation. This can be performed at any time during the byte load cycle, tWLQ5H, or while the W input is being held high between two load cycles. The default value of DQ1 is initially set to ’0’ and changes to ’1’ if the internal circuitry has detected a change on any of the address pins A16 to A7. This PWA bit can be checked regardless of whether Software Data Protection is enabled or disabled. Table 5A. Read Mode DC Characteristics for M28010 (5V range) (TA = –40 to 85 °C; VCC = 4.5 to 5.5 V) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0 V ≤ V IN ≤ VCC 0 V ≤ VOUT ≤ VCC E = VIL, G = VIL, f = 0.1 MHz ICC 1 Supply Current (CMOS inputs) E = VIL, G = VIL, f = 5 MHz E = VIL, G = VIL, f = 10 MHz ICC1 1 V IL V IH VOL VOH Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = –400 µA 2.4 E > VCC – 0.3 V –0.3 2 Min. Max. 5 5 2 22 40 50 0.8 VCC + 0.3 0.4 Unit µA µA mA mA mA µA V V V V Note: 1. All inputs and outputs open circuit. 8/23 M28010 Table 5B. Read Mode DC Characteristics for M28010-W (3V range) (TA = –40 to 85 °C; VCC = 2.7 to 3.6 V) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0 V ≤ V IN ≤ VCC 0 V ≤ VOUT ≤ VCC E = VIL, G = VIL, f = 0.1 MHz ICC 1 Supply Current (CMOS inputs) E = VIL, G = VIL, f = 5 MHz E = VIL, G = VIL , f = 10 MHz ICC1 1 V IL V IH VOL VOH Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = –100 µA 2.4 E > VCC – 0.3 V –0.3 2 Min. Max. 5 5 2 15 26 30 0.6 VCC + 0.3 0.45 Unit µA µA mA mA mA µA V V V V Note: 1. All inputs and outputs open circuit. Table 5C. Read Mode DC Characteristics for M28010-R (2V range) (TA = –40 to 85 °C; VCC = 1.8 to 2.4 V) Symbol ILI ILO ICC 1 ICC1 1 V IL V IH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) E = VIL, G = VIL, f = 5 MHz, VCC = 2.4 V Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 0.4 mA I OH = –100 µA VCC–0.15 E > VCC – 0.3 V –0.3 VCC–0.3 12 30 0.2 VCC+0.3 0.15 mA µA V V V V Test Conditio n 0 V ≤ VIN ≤ V CC 0 V ≤ VOUT ≤ VCC E = V IL, G = VIL, f = 0.1 MHz, VCC = 2.4 V Min. Max. 5 5 2 Unit µA µA mA Note: 1. All inputs and outputs open circuit. Software Data Protection bit (DQ0). Reading the SDP bit (DQ0) allows the user to determine whether the Software Data Protection mode has been enabled (SDP=1) or disabled (SDP=0). The SDP bit (DQ0) can be read by using a dedicated algorithm (as shown in Figure 8), or can be combined with the reading of the DP bit (DQ7), TB bit (DQ6) and PLTS bit (DQ5). 9/23 M 28010 Table 6. Input and Output Parameters1 (TA = 25 °C, f = 1 MHz) Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test Condition V IN = 0 V VOUT = 0 V Min. Max. 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. Table 7. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 5 ns 0 V to VCC VCC/2 Figure 10. AC Testing Equivalent Load Circuit IOL Figure 9. AC Testing Input Output Waveforms DEVICE UNDER TEST IOH OUT VCC VCC/2 0V AI02228 CL = 30pF CL includes JIG capacitance AI02578 Table 8A. Read Mode AC Characteristics for M28010 (5V range) (TA = –40 to 85 °C; VCC = 4.5 to 5.5 V) Symbol Alt. Parameter Test Condi t ion E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 M28010 –10 Min Max 100 100 40 40 40 0 0 0 Min –12 Max 120 120 45 45 45 ns ns ns ns ns ns Unit tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. 10/23 M28010 Table 8B. Read Mode AC Characteristics for M28010-W (3V range) (TA = –40 to 85 °C; VCC = 2.7 to 3.6 V) Symbol Alt. Parameter Test Condi t ion E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 M28010-W –10 Min Max 100 100 70 50 50 0 0 0 Min –12 Max 120 120 80 60 60 0 0 0 Min –15 Max 150 150 100 70 70 ns ns ns ns ns ns Unit tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Table 8C. Read Mode AC Characteristics for M28010-R (2V range) (TA = –40 to 85 °C; VCC = 1.8 to 2.4 V) Symbol Alt. Parameter Test Condi t ion E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 M28010-R –20 Min Max 200 200 80 50 50 0 0 0 Min –25 Max 250 250 90 60 60 ns ns ns ns ns ns Unit tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. 11/23 M 28010 Figure 11. Read Mode AC Waveforms (with Write Enable, W, high) A0-A16 tAVQV E tGLQV G tELQV DQ0-DQ7 VALID tAXQX tEHQZ tGHQZ DATA OUT Hi-Z AI02229 Note: 1. Write Enable (W) = VIH Table 9A. Write Mode AC Characteristics for M28010 (5V range) (TA = –40 to 85 °C; VCC = 4.5 to 5.5 V) M28010 Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tELEH tWHEH tWHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tAS tAS tCES tOES tOES tWES tAH tAH tWP tCEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after the last byte write Byte Write Cycle time Page Write Cycle time (up to 128 bytes) Data Valid before Write Enable High Data Valid before Chip Enable High 50 50 Test Condit ion Min E = VIL, G = VIH G = VIH, W= VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 70 70 100 0 0 0 0 0 50 100 150 5 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms ms ns ns Unit 12/23 M28010 Table 9B. Write Mode AC Characteristics for M28010-W (3V range) (TA = –40 to 85 °C; VCC = 2.7 to 3.6 V) M28010-W Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tELEH tWHEH tWHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tAS tAS tCES tOES tOES tWES tAH tAH tWP tCEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after the last byte write Byte Write Cycle time Page Write Cycle time (up to 128 bytes) Data Valid before Write Enable High Data Valid before Chip Enable High 80 80 Test Condit ion Min E = VIL, G = VIH G = VIH, W= VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 70 70 100 0 0 0 0 0 50 100 150 5 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms ms ns ns Unit 13/23 M 28010 Table 9C. Write Mode AC Characteristics for M28010-R (2V range) (TA = –40 to 85 °C; VCC = 1.8 to 2.4 V) M28010-R Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tELEH tWHEH tWHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tWHRH tDVWH tDVEH Alt. tAS tAS tCES tOES tOES tWES tAH tAH tWP tCEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after the last byte write Byte Write Cycle time Page Write Cycle time (up to 128 bytes) Data Valid before Write Enable High Data Valid before Chip Enable High 120 120 Test Condit ion Min E = VIL, G = VIH G = VIH, W= VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 120 120 120 0 0 0 0 0 100 120 150 5 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms ms ns ns Unit 14/23 M28010 Figure 12. Write Mode AC Waveforms (Write Enable, W, controlled) A0-A16 tAVWL E tELWL G tGHWL W VALID tWLAX tWHEH tWLWH tWHGL tWHWL DQ0-DQ7 DATA IN tDVWH tWHDX AI02230 Figure 13. Write Mode AC Waveforms (Chip Enable, E, controlled) A0-A16 tAVEL E tGHEL G tWLEL W tEHWH DQ0-DQ7 DATA IN tDVEH tEHDX AI02231 VALID tELAX tELEH tEHGL 15/23 M 28010 Figure 14. Page Write Mode AC Waveforms (Write Enable, W, controlled) A0-A16 Addr 0 Addr 1 Addr 2 Addr n E G tWHWL W tWLWH DQ0-DQ7 (in) Byte 0 Byte 1 Byte 2 Byte n DQ5 (out) tWLQ5H tQ5HQ5X AI02829B Figure 15. Software Protected Write Cycle Waveforms A0-A6 5555h A7-A16 2AAAh 5555h Page Add 1 Byte Add 0 Byte Add n E G tWHWL W tWLWH DQ0-DQ7 AAh tDVWH 55h A0h tWHDX Byte 0 Byte n AI02233B Note: 1. A16 to A7 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E are both low. 16/23 M28010 Figure 16. Data Polling Sequence Waveforms A0-A16 Address of the last byte of the Page Write instruction E G tWHGL W DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 LAST BYTE LOADED INTERNAL WRITE SEQUENCE OR TIME BETWEEN TWO CONSECUTIVE BYTES LOADING READY AFTER INTERNAL WRITE SEQUENCE AI02234 Figure 17. Toggle Bit Sequence Waveforms A0-A16 Address of the last byte of the Page Write instruction E G W DQ6 (1) LAST BYTE LOADED TOGGLE INTERNAL WRITE SEQUENCE OR TIME BETWEEN TWO CONSECUTIVE BYTES LOADING READY AFTER INTERNAL WRITE SEQUENCE AI02235 Note: 1. The Toggle Bit is first set to ‘0’. 17/23 M 28010 Table 10. Ordering Information Scheme Example: M28010 –10 W KA 6 T Option T Tape & Reel Packing Speed -10 -12 -15 -20 -25 100 ns 120 ns 150 ns 200 ns 250 ns 11 6 Temperature Range 0 to 70 ° C –40 to 85 °C Operating Voltage blank 4.5 V to 5.5 V W R 2.7 V to 3.6 V 1.8 V to 2.4 V BA KA NA Package PDIP32 PLCC32 TSOP32: 8 x 20mm Note: 1. This temperature range on request only. ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all ‘1’s (FFh). The notation used for the device number is as shown in Table 10. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 18/23 M28010 Table 11. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data mm Symbol A A1 A2 B B1 C D D2 E E1 e1 eA eB L S α N 2.54 15.24 38.10 15.24 1.52 Typ. Min. – 0.38 3.56 0.38 – 0.20 41.78 – – 13.59 – – 15.24 3.18 1.78 0° 32 Max. 5.08 – 4.06 0.51 – 0.30 42.04 – – 13.84 – – 17.78 3.43 2.03 10° 0.100 0.600 1.500 0.600 0.060 Typ. inches Min. – 0.015 0.140 0.015 – 0.008 1.645 – – 0.535 – – 0.600 0.125 0.070 0° 32 Max. 0.200 – 0.160 0.020 – 0.012 1.655 – – 0.545 – – 0.700 0.135 0.080 10° Figure 18. PDIP32 (BA) A2 A1 B1 B D2 D S N A L α eA eB C e1 E1 1 E PDIP Note: 1. Drawing is not to scale. 19/23 M 28010 Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular Symbol A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Typ. Min. 2.54 1.52 – 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 – 0.00 – 32 7 9 0.10 Max. 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 – 0.25 – 0.035 0.050 Typ. inches Min. 0.100 0.060 – 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 – 0.000 – 32 7 9 0.004 Max. 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 – 0.010 – Figure 19. PLCC32 (KA) D D1 1N A1 A2 B1 Ne E1 E F 0.51 (.020) D2/E2 B e 1.14 (.045) Nd A R CP PLCC Note: 1. Drawing is not to scale. 20/23 M28010 Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data mm Symbol Typ. A A1 A2 B C D D1 E e L α N CP 0.50 0.05 0.95 0.15 0.10 19.80 18.30 7.90 – 0.50 0° 32 0.10 Min. Max. 1.20 0.17 1.05 0.27 0.21 20.20 18.50 8.10 – 0.70 5° 0.020 0.002 0.037 0.006 0.004 0.780 0.720 0.311 – 0.020 0° 32 0.004 Typ. Min. Max. 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.319 – 0.028 5° inches Figure 20. TSOP32 (NS) A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a A1 α L Note: 1. Drawing is not to scale. 21/23 M 28010 Table 14. Revision History Date 15-Feb-2000 28-Feb-2000 Description of Revision ICC1(max), in Read Mode DC Char table for 5V, changed from 30 µA to 50 µA. tDVWH(min) and tDVEH(min), in Write Mode AC Char table for 3V, changed from 50 ns to 80 ns 22/23 M28010 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics. © 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http:// www.st.com 23/23