ST7LITEUS2
ST7LITEUS5
8-bit MCU with single voltage Flash memory, ADC, timers
Features
■
Memories
– 1 Kbytes single-voltage Flash Program
memory with readout protection, ICP and
IAP)
10 K write/erase cycles guaranteed
data retention: 20 years at 55 °C
– 128 bytes RAM
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■
Plastic DIP8
Clock, Reset and Supply management
– 3-level low-voltage supervisor (LVD) and
auxiliary voltage detector (AVD) for safe
power-on/off
– Clock sources: internal trimmable 8 MHz
RC oscillator, internal low power, low
frequency RC oscillator or external clock
– Five power saving modes: Halt, Autowakeup from Halt, Active-halt, Wait, Slow
■
Interrupt management
– 11 interrupt vectors plus TRAP and RESET
– 5 external interrupt lines (on 5 vectors)
■
I/O ports
– 5 multifunctional bidirectional I/O lines
– 1 additional Output line
– 6 alternate function lines
– 5 high sink outputs
Table 1.
SO8
150”
DFN8
Plastic DIP16
■
2 Timers
– One 8-bit Lite timer (LT) with prescaler
including: watchdog, one realtime base and
one 8-bit input capture.
– One 12-bit auto-reload timer (AT) with
output compare function and PWM
■
A/D Converter
– 10-bit resolution for 0 to VDD
– 5 input channels
■
Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8x8 unsigned multiply instruction
■
Development Tools
– Full hardware/software development
package
– Debug module
Device summary
Features
ST7LITEUS2
ST7LITEUS5
Program memory
1 Kbytes
RAM (stack)
128 (64) bytes
Peripherals
LT Timer w/ Wdg, AT Timer w/ 1 PWM
ADC
Operating Supply
-
10-bit
2.4 to 3.3 V @fCPU=4 MHz, 3.3 to 5.5 V @fCPU=8 MHz
CPU Frequency
Operating Temperature
Packages
up to 8 MHz RC
-40 to +85 °C / -40 to 125 °C
SO8 150”, Pastic DIP8, DFN8, Pastic DIP16(1)
1. For development or tool prototyping purposes only. Not orderable in production quantities.
February 2009
Rev 5
1/136
www.st.com
1
Contents
ST7LITEUS2, ST7LITEUS5
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.2
In application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2
4.4
I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.2
Flash Write/Erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7.1
5
6
2/136
Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.2
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.3
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.4
Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.5
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2
Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ST7LITEUS2, ST7LITEUS5
6.3
6.4
Contents
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.1
Main Clock Control/Status register (MCCSR) . . . . . . . . . . . . . . . . . . . . 30
6.3.2
RC Control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.3
System Integrity (SI) Control/status register (SICSR) . . . . . . . . . . . . . . 31
6.3.4
AVD Threshold Selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . 32
6.3.5
Clock Controller Control/Status register (CKCNTCSR) . . . . . . . . . . . . . 32
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.2
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.3
External Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.4
Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.5
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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6.5
7
6.5.1
Multiplexed I/O Reset Control register 1 (MUXCR1) . . . . . . . . . . . . . . . 37
6.5.2
Multiplexed I/O Reset Control register 0 (MUXCR0) . . . . . . . . . . . . . . . 37
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3
Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4
8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3.1
External Interrupt Control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 41
7.3.2
External Interrupt Control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 42
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4.1
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4.2
Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.3
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4.4
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.3
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.4
Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.5
8.4.1
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.4.2
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3/136
Contents
ST7LITEUS2, ST7LITEUS5
8.5.1
9
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.1
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.3
Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.6
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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10
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1
10.2
10.3
4/136
Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12-bit auto-reload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ST7LITEUS2, ST7LITEUS5
11
Contents
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1
ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1.1
Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.4
Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.5
Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.6
Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.7
Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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11.2
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.1
12
Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.4
12.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.2
Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . 95
12.3.3
Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . 96
12.3.4
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.4.1
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.4.2
Internal RC oscillator supply current characteristics . . . . . . . . . . . . . . 100
12.4.3
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.5
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.6
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.7
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.8
12.7.1
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 105
12.7.2
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.7.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 106
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5/136
Contents
ST7LITEUS2, ST7LITEUS5
12.9
12.8.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12.8.2
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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Device configuration and ordering information . . . . . . . . . . . . . . . . . 123
14.1
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.1.1
OPTION BYTE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.1.2
OPTION BYTE 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.2
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.4
14.3.1
Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.2
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.3
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.4
Order codes for development and programming tools . . . . . . . . . . . . . 128
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6/136
ST7LITEUS2, ST7LITEUS5
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 86
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 87
Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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7/136
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
ST7LITEUS2, ST7LITEUS5
Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . . 96
Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Internal RC oscillator supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
RAM and Hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Flash Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ADC accuracy with VDD = 2.4V to 2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8-lead very thin fine pitch dual flat no-lead package mechanical data . . . . . . . . . . . . . . . 118
8-pin plastic small outline package, 150-mil width, package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8-pin plastic dual in-line package, 300-mil width package mechanical data. . . . . . . . . . . 120
16-pin plastic dual in-line package, 300-mil width, package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Definition of sector 0 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Supported order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Development tool order codes for the ST7LITEUSx family . . . . . . . . . . . . . . . . . . . . . . . 129
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 79.
Table 80.
Table 81.
Table 82.
8/136
ST7LITEUS2, ST7LITEUS5
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8-pin SO and Plastic DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8-pin DFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . . . 95
Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature . . . . . . . . . . . 98
Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature. . . . . . . . . . . . 98
Typical IDD in run mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 101
Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 101
Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int
RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
IDD vs temp @VDD 5 V & int RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
IDD vs temp @VDD 5 V & int RC = 4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
IDD vs temp @VDD 5 V & int RC = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Figure 45.
Figure 46.
Figure 47.
9/136
List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
ST7LITEUS2, ST7LITEUS5
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Typical IPU vs. VDD with VIN=VSSl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Typical VOL at VDD = 2.4 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical VOL at VDD = 3 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical VOL at VDD = 5 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical VOL at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical VOL at VDD = 3 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical VOL at VDD = 5 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Typical VDD-VOH at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical VDD-VOH at VDD = 3 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical VDD-VOH at VDD = 5 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical VDD-VOH vs. VDD (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8-lead very thin fine pitch dual flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . . . 118
8-pin plastic small outline package, 150-mil width package outline . . . . . . . . . . . . . . . . . 119
8-pin plastic dual in-line package, 300-mil width package outline . . . . . . . . . . . . . . . . . . 120
16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 121
Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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10/136
ST7LITEUS2, ST7LITEUS5
1
Introduction
Introduction
The ST7LITEUS2 and ST7LITEUS5 are members of the ST7 microcontroller family. All ST7
devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set.
The ST7LITEUS2 and ST7LITEUS5 feature FLASH memory with byte-by-byte In-Circuit
Programming (ICP) and In-Application Programming (IAP) capability.
Under software control, the ST7LITEUS2 and ST7LITEUS5 can be placed in Wait, Slow, or
Halt mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
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For easy reference, all parametric data are located in Section 12 on page 92.
The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 I2C protocol reference manual.
Figure 1.
General block diagram
AWU RC OSC
Internal
Clock
8-MHz RC OSC
External
Clock
VDD
VSS
with WATCHDOG
POWER
SUPPLY
PORT A
CONTROL
8-BIT CORE
ALU
1 KByte
FLASH
MEMORY
ADDRESS AND DATA BUS
PA3 / RESET
LITE TIMER
LVD
12-BIT AUTORELOAD TIMER
PA5:0
(6 bits)
10-BIT ADC
RAM
(128 Bytes)
11/136
Pin description
2
ST7LITEUS2, ST7LITEUS5
Pin description
Figure 2.
8-pin SO and Plastic DIP package pinout
VDD
1
PA5 (HS) / AIN4 / CLKIN
2
ei4
ei0
7 PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA4 (HS) / AIN3/MCO
3
ei3
ei1
6
PA1 (HS) / AIN1 / ICCCLK
PA3 / RESET
4
ei2
5
PA2 (HS) / LTIC / AIN2
8
VSS
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1.
HS: High sink capability.
2. eix : associated external interrupt vector
Figure 3.
12/136
8-pin DFN package pinout
VDD
1
PA5 (HS) / AIN4 / CLKIN
2
ei4
PA4 (HS) / AIN3/MCO
3
ei3
PA3 / RESET
4
1.
HS: High sink capability.
2.
eix : associated external interrupt vector
8
VSS
ei0
7
PA0 (HS) / AIN0 / ATPWM / ICCDATA
ei1
6
PA1 (HS) / AIN1 / ICCCLK
ei2
5
PA2 (HS) / LTIC / AIN2
ST7LITEUS2, ST7LITEUS5
Figure 4.
Pin description
16-pin package pinout
Reserved 1)
1
1
NC
VDD
2
1
VSS
RESET
3
ei0
1
PA0 (HS) / AIN0 / ATPWM
ICCCLK
4
ei1
1
PA1 (HS) / AIN1
PA5 (HS) / AIN4 / CLKIN
5
ei4
12
NC
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PA4 (HS) / AIN3/MCO
6
PA3
7
ei210
NC
8
9
ei3
11
ICCDATA
PA2 (HS) / LTIC / AIN2
NC
1. Reserved pins must be tied to ground.
2. The differences versus the 8-pin packages are listed below:
The I2C signals (ICCCLK and ICCDATA) are mapped on dedicated pins.
The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3.
PA3 pin is always configured as output. Any change on multiplexed IO reset control registers (MUXCR1
and MUXCR2) will have no effect on PA3 functionality. Refer to Section 6.5: Register description on
page 37.
13/136
Pin description
ST7LITEUS2, ST7LITEUS5
Legend/abbreviations for Table 2
Type: I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3 VDD /0.7 VDD with input trigger
Output level: HS = High sink (on N-buffer only)
Port and control configuration
●
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
●
Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
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Device pin description
Port/control
PP
OD
Output
ana
int
Input
float
Output
Pin name
Input
Pin
no.
Type
Level
wpu
Table 2.
Main
function
(after
reset)
Alternate function
1
VDD
S
Main power supply
2
PA5/AIN4/CLKIN
I/
CT HS
O
X
ei4
X
X
X Port A5
Analog input 4 or External Clock
Input
3
PA4/AIN3/MCO
I/
CT HS
O
X
ei3
X
X
X Port A4
Analog input 3 or main clock output
4
PA3/RESET (1)
O
X
X Port A3
RESET(1)
5
PA2/AIN2/LTIC
I/
CT HS
O
X
X Port A2
Analog input 2 or Lite Timer Input
Capture
X
X
ei2
X
6
PA1/AIN1/
ICCCLK
I/
CT HS
O
X
ei1
X
X
X Port A1
Analog input 1 or In Circuit
Communication Clock
Caution: During normal operation
this pin must be pulled-up, internally
or externally (external pull-up of 10k
mandatory in noisy environment).
This is to avoid entering I2C mode
unexpectedly during a reset. In the
application, even if the pin is
configured as output, any reset will
put it back in pull-up
7
PA0/AIN0/ATPW
M/ICCDATA
I/
CT HS
O
X
ei0
X
X
X Port A0
Analog input 0 or Auto-Reload
Timer PWM or In Circuit
Communication Data
8
VSS
S
Ground
1. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to
MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 6.5 on page 37.
14/136
ST7LITEUS2, ST7LITEUS5
3
Register and memory map
Register and memory map
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM
and 1 Kbyte of user program memory. The RAM space includes up to 64 bytes for the stack
from 00C0h to 00FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh).
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The size of Flash Sector 0 and other device options are configurable by option byte.
Warning:
Figure 5.
Memory locations marked as “Reserved” must never be
accessed. Accessing a reserved area can have unpredictable
effects on the device.
Memory map
0000h
HW registers(1)
007Fh
0080h
0080h
Short addressing
RAM (zero page)
00C0h
RAM
(128 Bytes)
b
64-byte stack
00FFh
00FFh
0100h
DEE0h
DEE1h
DEE2h
Reserved
FBFFh
FC00h
1Kbytes FLASH
PROGRAM MEMORY
FC00h
FDFFh
FE00h
Flash Memory
(1 Kbytes)
FFFFh
DEE3h
RCCRH0
RCCRL0
RCCRH1
RCCRL1
0.5 Kbytes
SECTOR 1
0.5 Kbytes
SECTOR 0
FFDFh
FFE0h
Interrupt & Reset vectors(3)
FFFFh
1. See Table 3.
2. See Section 6.2 on page 28 for the description of RCCRHx registers.
3. See Table 9.
15/136
Register and memory map
Table 3.
Address
0000h
0001h
0002h
Hardware register map (1)
Block
Port A
Register
label
PADR
PADDR
PAOR
0003h000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
ST7LITEUS2, ST7LITEUS5
Register name
Port A Data register
Port A Data Direction register
Port A Option register
Reset status
00h(2)
08h
02h(3)
Remarks
R/W
R/W
R/W
Reserved area (8 bytes)
LITE
TIMER
LTCSR
LTICR
ATCSR
CNTRH
AUTO- CNTRL
RELOAD ATRH
TIMER ATRL
PWMCR
PWM0CSR
Lite Timer Control/Status register
Lite Timer Input Capture register
0xh
00h
R/W
Read only
Timer Control/Status register
Counter register High
Counter register Low
Auto-Reload register High
Auto-Reload register Low
PWM Output Control register
PWM 0 Control/Status register
00h
00h
00h
00h
00h
00h
00h
R/W
Read only
Read only
R/W
R/W
R/W
R/W
00h
00h
R/W
R/W
00h
R/W
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0014h to
0016h
0017h
0018h
Reserved area (3 bytes)
AUTODCR0H
RELOAD
DCR0L
TIMER
0019h to
002Eh
0002Fh
PWM 0 Duty Cycle register High
PWM 0 Duty Cycle register Low
Reserved area (22 bytes)
FLASH
FCSR
0030h to
0033h
Flash Control/Status register
Reserved area (4 bytes)
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status register
A/D Data register High
A/D Data register Low
00h
xxh
00h
R/W
Read only
R/W
0037h
ITC
EICR1
External Interrupt Control register 1
00h
R/W
0038h
MCC
MCCSR
Main Clock Control/Status register
00h
R/W
FFh
0000 0x00b
R/W
R/W
0039h
003Ah
Clock and RCCR
Reset
SICSR
003Bh to
003Ch
RC oscillator Control register
System Integrity Control/Status register
Reserved area (2 bytes)
003Dh
ITC
EICR2
External Interrupt Control register 2
00h
R/W
003Eh
AVD
AVDTHCR
AVD Threshold Selection register
03h
R/W
Clock Controller Control/Status register
09h
R/W
00h
00h
R/W
R/W
003Fh
Clock
CKCNTCSR
controller
0040h to
0046h
0047h
0048h
16/136
Reserved area (7 bytes)
MuxIOreset
MUXCR0
MUXCR1
Mux IO-Reset Control register 0
Mux IO-Reset Control register 1
ST7LITEUS2, ST7LITEUS5
Table 3.
Register and memory map
Hardware register map (continued)(1)
Register
label
Address
Block
0049h
004Ah
AWU
AWUPR
AWUCSR
AWU Prescaler register
AWU Control/Status register
FFh
00h
R/W
R/W
DM(4)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control register
DM Status register
DM Breakpoint register 1 High
DM Breakpoint register 1 Low
DM Breakpoint register 2 High
DM Breakpoint register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
Register name
Reset status
Remarks
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0051h to
007Fh
Reserved area (47 bytes)
1. Legend: x=undefined, R/W=read/write
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
3. The bits associated with unavailable pins must always keep their reset value.
4. For a description of the DM registers, see the ST7 I2C Protocol Reference Manual.
17/136
Flash program memory
4
Flash program memory
4.1
Introduction
ST7LITEUS2, ST7LITEUS5
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
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4.2
Main features
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4.3
Programming modes e
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●
ICP (in-circuit programming)
●
IAP (in-application programming)
●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
Sector 0 size configurable by option byte
●
Readout and write protection
The ST7 can be programmed in three different ways:
●
Insertion in a programming tool
In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or
erased.
●
In-circuit programming
In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or
erased without removing the device from the application board.
●
In-application programming
In this mode, sector 1 can be programmed or erased without removing the device from
the application board and while the application is running.
4.3.1
In-circuit programming (ICP)
ICP uses a protocol called I2C (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
via cable. ICP is performed in three steps:
●
18/136
Switch the ST7 to I2C mode. This is done by driving a specific signal sequence on the
ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters I2C mode,
it fetches a specific RESET vector which points to the ST7 system memory containing
ST7LITEUS2, ST7LITEUS5
Flash program memory
the I2C protocol routine. This routine enables the ST7 to receive bytes from the I2C
interface.
●
Download ICP driver code in RAM from the ICCDATA pin
●
Execute ICP driver code in RAM to program the FLASH memory
Depending on the ICP driver code downloaded in RAM, FLASH memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In application programming (IAP)
This mode uses an IAP driver program previously programmed in Sector 0 by the user (in
ICP mode).
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4.4
I C interface
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This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc).
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
2
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
●
RESET: device reset
●
VSS: device power supply ground
●
ICCCLK: I2C output serial clock pin
●
ICCDATA: I2C input serial data pin
●
CLKIN: main clock input for external source
●
VDD: application board power supply
Refer to Figure 6 for a description of the I2C interface.
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the programming tool is plugged to the board, even if an
I2C session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the programming
tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5 mA at high level (push pull output or pull-up resistor1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the I2C session.
The use of Pin 7 of the I2C connector depends on the programming tool architecture. This
pin must be connected when using most ST programming tools (it is used to monitor the
application power supply). Please refer to the programming tool manual.
19/136
Flash program memory
ST7LITEUS2, ST7LITEUS5
Pin 9 has to be connected to the CLKIN pin of the ST7 when I2C mode is selected with
option bytes disabled (35-pulse I2C entry mode). When option bytes are enabled (38-pulse
I2C entry mode), the internal RC clock (internal RC or AWU RC) is forced. If internal RC is
selected in the option byte, the internal RC is provided. If AWU RC or external clock is
selected, the AWU RC oscillator is provided.
A serial resistor must be connected to I2C connector pin 6 in order to prevent contention on
PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin
forces the opposite state in output mode. The resistor value is defined to limit the current
below 2 mA at 5 V. If PA3 is used as output push-pull, then the application must be switched
off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to
drive the RESET pin below VIL, special care must also be taken when a pull-up is placed on
PA3 for application reasons.
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protection
O4.5 Memory
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Caution:
During normal operation, ICCCLK pin must be pulled- up, internally or externally (external
pull-up of 10 kΩ mandatory in noisy environment). This is to avoid entering I2C mode
unexpectedly during a reset. In the application, even if the pin is configured as output, any
reset will put it back in input pull-up.
Figure 6.
Typical I2C interface
PROGRAMMING TOOL
I2C CONNECTOR
I2C Cable
I2 C
CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION BOARD
APPLICATION
RESET SOURCE
3.3kΩ
(See Note 5)
See Note 2
APPLICATION
POWER SUPPLY
See Note 1 and Caution
APPLICATION
I/O
ICCDATA
RESET
ST7
ICCCLK
CLKIN
VDD
See Note 1
There are two different types of memory protection: readout protection and Write/Erase
Protection which can be applied individually.
4.5.1
Readout protection
Readout protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Program memory is protected.
20/136
ST7LITEUS2, ST7LITEUS5
Flash program memory
In flash devices, this protection is removed by reprogramming the option. In this case,
program memory is automatically erased, and the device can be reprogrammed.
Readout protection selection depends on the device type:
4.5.2
●
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●
In ROM devices it is enabled by mask option specified in the option list.
Flash Write/Erase protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program
memory. Its purpose is to provide advanced security to applications and prevent any change
being made to the memory content.
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4.6
Related documentation
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Warning:
Once set, Write/erase protection can never be removed. A
write-protected flash device is no longer reprogrammable.
Write/erase protection is enabled through the FMP_W bit in the option byte.
For details on Flash programming and I2C protocol, refer to the ST7 Flash programming
reference manual and to the ST7 I2C protocol reference manual.
21/136
Flash program memory
ST7LITEUS2, ST7LITEUS5
4.7
Register description
4.7.1
Flash Control/Status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other
programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
Reset value: 000 0000 (00h)
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7
0
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0
0
0
0
OPT
LAT
PGM
Read/write
Table 4.
Address
(Hex.)
002Fh
22/136
FLASH register map and reset values
Register
Label
FCSR
Reset
value
7
6
5
4
3
2
1
0
0
0
0
0
0
OPT
0
LAT
0
PGM
0
ST7LITEUS2, ST7LITEUS5
5
Central processing unit
5.1
Introduction
Central processing unit
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
5.2
Main features
●
63 basic instructions
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CPU registers
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Fast 8-bit by 8-bit multiply
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17 main addressing modes
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Two 8-bit index registers
●
16-bit stack pointer
●
Low power modes
●
Maskable hardware interrupts
●
Non-maskable software interrupt
The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
5.3.1
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
5.3.2
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The cross-assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
5.3.3
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
23/136
Central processing unit
Figure 7.
ST7LITEUS2, ST7LITEUS5
CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
PCH
15
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
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7
0
1 1 1 H I
N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
1. X = Undefined value
5.3.4
Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Reset value: 111x1xxx
7
1
0
1
1
H
I
Read/Write
24/136
N
Z
C
ST7LITEUS2, ST7LITEUS5
Central processing unit
Bit 7:5 Set to ‘1’
Bit 4 H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Bit 3 I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the
JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I
is cleared. By default an interrupt routine is not interruptible because the I bit
is set by hardware at the start of the routine and reset by the IRET
instruction at the end of the routine. If the I bit is cleared by software in the
interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
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Bit 2 N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and
JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
25/136
Central processing unit
5.3.5
ST7LITEUS2, ST7LITEUS5
Stack Pointer (SP)
Reset value: 00 FFh
15
0
8
0
0
0
0
0
0
0
Read/write
7
1
0
1
SP5
SP4
SP3
SP2
SP1
SP0
Read/write
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The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call is located at two locations and an interrupt five locations in the stack area.
26/136
ST7LITEUS2, ST7LITEUS5
Figure 8.
Central processing unit
Stack manipulation example
CALL
subroutine
PUSH Y
Interrupt
event
POP Y
RET
or RSP
IRET
@ 00C0h
SP
SP
CC
A
Y
CC
A
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
SP
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@ 00FFh
SP
1. Stack higher address = 00FFh.
2. Stack lower address = 00C0h.
27/136
Supply, reset and clock management
6
ST7LITEUS2, ST7LITEUS5
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components.
6.1
Main features
●
Clock management
–
8 MHz internal RC oscillator (enabled by option byte)
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Internal RC oscillator adjustmento
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–
External clock Input (enabled by option byte)
●
Reset sequence manager (RSM)
●
System integrity management (SI)
–
Main supply low voltage detection (LVD) with reset generation (enabled by option
byte)
–
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
The ST7 contains an internal RC oscillator with a specific accuracy for a given device,
temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0]
option bits (see Section 14.1 on page 123). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a 10-bit calibration value in the
RCCR (RC Control register) and in the bits [6:5] in the SICSR (SI Control Status register).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored in Flash memory for 3.3 and 5 V VDD supply voltages at 25°C,
as shown in the following table.
Table 5.
Predefined RC oscillator calibration values
RCCR
RCCRH0
RCCRL0
RCCRH1
RCCRL1
Conditions
ST7LITEUS2/ST7LITEUS5 address
VDD=5 V
TA=25 °C
fRC=8 MHz
DEE0h(1) (CR[9:2] bits)
VDD=3.3 V
TA=25 °C
fRC=8 MHz
DEE2h 1) (CR[9:2] bits)
DEE1h 1) (CR[1:0] bits)
DEE3h 1) (CR[1:0] bits)
1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area butare special bytes containing also
the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the
RC calibration value locations) has been erased (after the readout protection removal), then the RC
calibration values can still be obtained through these two addresses.
28/136
ST7LITEUS2, ST7LITEUS5
Supply, reset and clock management
1
In I2C mode, the internal RC oscillator is forced as a clock source, regardless of the
selection in the option byte. Refer to note 5 in Section 4.4 on page 19 for further details.
2
See Section 12: Electrical characteristics for more information on the frequency and
accuracy of the RC oscillator.
3
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Note:
Refer to application note AN2326 for information on how to calibrate the RC frequency using
an external reference signal.
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The ST7LITEUS2 and ST7LITEUS5 also contain an Auto-wakeup RC oscillator. This RC
oscillator should be enabled to enter Auto-wakeup from Halt mode.
The Auto-wakeup RC oscillator can also be configured as the startup clock through the
CKSEL[1:0] option bits (see Section 14.1 on page 123).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure 9):
Case 1
Switching from internal RC to AWU:
1.
Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
2.
The RC_FLAG is cleared and the clock output is at 1.
3.
Wait 3 AWU RC cycles till the AWU_FLAG is set
4.
The switch to the AWU clock is made at the positive edge of the AWU clock signal
5.
Once the switch is made, the internal RC is stopped
Case 2
Switching from AWU RC to internal RC:
Note:
1.
Reset the RC/AWU bit to enable the internal RC oscillator
2.
Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
running on internal RC clock.
3.
Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC
cycles)
4.
The switch to the internal RC clock is made at the positive edge of the internal RC clock
signal
5.
Once the switch is made, the AWU RC is stopped
1
When the internal RC is not selected, it is stopped so as to save power consumption.
2
When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto-wakeup from Halt mode.
3
When the external clock is selected, the AWU RC oscillator is always on.
29/136
Supply, reset and clock management
Figure 9.
ST7LITEUS2, ST7LITEUS5
Clock switching
Internal RC Set RC/AWU
Poll AWU_FLAG until set
AWU RC
6.3
Reset RC/AWU
Poll RC_FLAG until set
AWU RC
Internal RC
Register description
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6.3.1
Main Clock Control/Status register (MCCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
MCO
SMS
Read / Write
Bits 7:2 Reserved, must be kept cleared.
Bit 1 MCO Main Clock Out enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit
allows to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit
selects the input clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSC )
1: Slow mode (fCPU = fOSC/32)
30/136
ST7LITEUS2, ST7LITEUS5
6.3.2
Supply, reset and clock management
RC Control register (RCCR)
Reset value: 1111 1111 (FFh)
7
CR9
0
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Read / Write
Bits 7:0 CR[9:2] RC Oscillator Frequency Adjustment Bits
These bits, as well as CR[1:0] bits in the SICSR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. The application can store the correct value for each voltage
range in Flash memory and write it to this register at startup.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of different values in the register until the
correct frequency is reached. The fastest method is to use a dichotomy
starting with 80h.
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6.3.3
System Integrity (SI) Control/status register (SICSR)
Reset value: 0000 0x00 (0xh)
7
0
0
CR1
CR0
0
0
LVDRF
AVDF
AVDIE
Read / Write
Bit 7 Reserved, must be kept cleared.
Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. Refer to Section 6.2 on page 28.
Bits 4:3 Reserved, must be kept cleared.
Bits 2:0 System Integrity bits. Refer to Section 7.4 on page 43.
31/136
Supply, reset and clock management
6.3.4
ST7LITEUS2, ST7LITEUS5
AVD Threshold Selection register (AVDTHCR)
Reset value: 0000 0011 (03h)
7
0
CK2
CK1
CK0
0
0
0
AVD1
AVD0
Read / Write
Bits 7:5 CK[2:0] Internal RC Prescaler Selection
These bits are set by software and cleared by hardware after a reset. These bits
select the prescaler of the internal RC oscillator. See Figure 10 on page 34 and
Table 6.
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Bits 4:2 Reserved, must be kept cleared.
Bits 1:0 AVD Threshold Selection bits. Refer to Section 7.4: System integrity management
(SI).
Internal RC prescaler selection bits(1)
Table 6.
CK2
CK1
CK0
fOSC
0
0
0
fRC
0
0
1
fRC/2
0
1
0
fRC/4
0
1
1
fRC/8
1
0
0
fRC/16
1. If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be
enabled in the RC prescaler.
6.3.5
Clock Controller Control/Status register (CKCNTCSR)
Read/Write
Reset value: 0000 1001 (09h)
7
0
0
0
0
0
AWU_FLAG
RC_
FLAG
Read / Write
Bits 7:4 Reserved, must be kept cleared.
Bit 3 AWU_FLAG AWU Selection
This bit is set and cleared by hardware
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
32/136
0
RC/AWU
ST7LITEUS2, ST7LITEUS5
Supply, reset and clock management
Bit 2 RC_FLAG RC Selection
This bit is set and cleared by hardware
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
Bit 0 = RC/AWU RC/AWU Selection
0: RC enabled
1: AWU enabled (default value)
Table 7.
Address
(Hex.)
Clock register map and reset values
Register
label
7
6
5
4
3
2
0038h
MCCSR
Reset value
0
0
0
0
0
0
0039h
RCCR
reset value
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
003Ah
SICSR
reset value
0
CR1
CR0
0
003Eh
AVDTHCR
reset value
CK2
0
CK1
0
CK0
0
003Fh
CKCNTCSR
reset value
0
0
0
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LVDRF
x
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1
CR3
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AVDF
0
SMS
0
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CR2
1
AVDIE
0
0
0
AVD1
1
AVD2
1
AWU_FLAG
1
RC_FLAG
0
0
RC/AWU
1
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33/136
Supply, reset and clock management
ST7LITEUS2, ST7LITEUS5
Figure 10. Clock management block diagram
CR9
CR8
CR7
CR6
CR5
CR1
CR4
CR3
CR2
RCCR
SICSR
CR0
Tunable
internal RC Oscillator
RC/AWU CKCNTCSR
Clock
Controller
8MHz(fRC)
8 MHz RC OSC
4 MHz
2 MHz
fOSC
AWU CK
Ext Clock
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Prescaler
1 MHz
500 kHz
AWU
RC
CLKIN
fCLKIN
33kHz
CKSEL[1:0]
Option bits
/2
DIVIDER
13-BIT
LITE TIMER COUNTER
fOSC
fOSC
/32 DIVIDER
fOSC/32
0
1
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR
MCO
34/136
ST7LITEUS2, ST7LITEUS5
Supply, reset and clock management
6.4
Reset sequence manager (RSM)
6.4.1
Introduction
The reset sequence manager includes three reset sources as shown in Figure 12:
Note:
●
External RESET source pulse
●
Internal LVD reset (low voltage detection)
●
Internal WATCHDOG reset
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Figure 12.
These sources act on the RESET pin and it is always kept low during the delay phase.
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The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 11:
Caution:
●
Active phase depending on the reset source
●
64 CPU clock cycle delay
●
RESET vector fetch
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery
has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset sequence phases
RESET
Active phase
INTERNAL RESET
64 CLOCK CYCLES
FETCH
VECTOR
35/136
Supply, reset and clock management
ST7LITEUS2, ST7LITEUS5
Figure 12. Reset block diagram
VDD
RON
RESET
INTERNAL
RESET
FILTER
WATCHDOG RESET
PULSE
GENERATOR
ILLEGAL OPCODE RESET 1)
LVD RESET
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1. Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions
6.4.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and
therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
6.4.3
External Power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fCLKIN frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
6.4.4
Internal low voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-on reset
●
Voltage Drop reset
The device RESET pin acts as an output that is pulled low when VDD
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