STA2058EXA

STA2058 TESEO™ GPS platform high-sensitivity baseband Data Brief Features ■ Single chip baseband with embedded Flash ■ Complete embedded memory system: – Flash 256 KB +16 Kbytes – RAM 64 Kbytes ) s t( LQFP64 LFBGA144 c u d ■ 66 MHz ARM7TDMI 32 bit processor ■ High performance GPS engine (HPGPS) Evaluation kits ■ SBAS (WAAS and EGNOS) supported ■ STA2058 module reference design (25x25mm) ■ Sensitivity (-146 dBm acquisition, -159 dBm tracking) ■ Evaluation board hosting STA2058 module ■ SDK board (for application SW development) ■ o s b Time to first fix (1s reacquisition, 2.5 s hot start, 34 s warm start, 39 s cold start) Description -O ■ Accuracy (2 m autonomous) ■ External memory interface (EMI) supporting up to 64 Mbite of external SRAM, Flash and ROM ■ Extensive GPS receiver interfaces: 48 GPIOs, 4 UARTs, 2 SPIs, 2 I2Cs, 2 CANs 2.0, 1 USB 1.1,1 HDLC and 4 channels ADC ) s ( ct STA2058 is the high-sensitivity baseband of TESEO GPS platform which include the STA5620 RF Front-End. The embedded Flash memory enables the equipment manufacturer to load the entire GPS software (including tracking, acquisition, navigation and data output) after customizing its interfaces to his needs. A standard GPS library is available from ST. u d o r P e ■ ST proprietary Flash embedded technology ■ LFBGA144 and LQFP64 lead-free package ■ -40 °C to 85 °C operating temperature range t e l o TESEO is the ideal solution for consumer, handheld, PND (portable navigation), in vehicle navigation and telematics systems. s b O Table 1. e t le o r P SBAS (WAAS and EGNOS) feature is also supported. Device summary Order code Package EMI (External Memory Interface) Packing Automotive grade STA2058 LQFP64 (10x10x1.4mm) No Tray No STA2058TR LQFP64 (10x10x1.4mm) No Tape and reel No STA2058EX LFBGA144 (10x10x1.7mm) Yes Tray No STA2058EXTR LFBGA144 (10x10x1.7mm) Yes Tape and reel No STA2058EXA LFBGA144 (10x10x1.7mm) Yes Tray Yes STA2058EXATR LFBGA144 (10x10x1.7mm) Yes Tape and reel Yes September 2013 Rev 4 For further information contact your local STMicroelectronics sales office. 1/20 www.st.com 20 Contents STA2058 Contents 1 Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 3 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 5 2/20 ) s t( 3.1 Package LFBGA144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Package LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 c u d o r P Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 e t le 4.1 DC electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 nRSTIN input filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Flash electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 o s b O ) s ( t c u d o r P e 4.8 LVD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9 GPS performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 t e l o s b O 6 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STA2058 1 Features summary Features summary ● ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up to 66 MHz. ● Complete embedded memory system: Flash 256 Kbytes + 16 Kbytes (100 KB erasing/programming cycles) – RAM 64 Kbytes. ● External memory interface provides glueless support for up to four banks of external SRAM, Flash, ROM. ● High performance GPS engine (HPGPS). ● ST Proprietary CMOS (0.18 µm) Flash embedded technology. ● SBAS (WAAS and EGNOS) supported ● -40 °C to 85 °C operating temperature range. ● 144-pin LFBGA package and 64-pin LQFP package ● Power supply: e t le ) s t( c u d o r P – 3.0 V to 3.6 V operating supply range for Input/Output periphery – 3.0 V to 3.6 V operating supply range for A/D Converter reference – 1.8 V operating supply range for core supply provided either by internal voltage regulator (with external stabilization capacitor) or by external supply voltage. o s b O ) ● Reset and clock control unit able to provide low power modes (WAIT, SLOW, STOP, STANDBY) and to generate the internal clock from the external reference through integrated PLL. ● 48 programmable general purpose I/O, each pin programmable independently as digital input or digital output; 40 (30 in LQFP64) are multiplexed with peripheral functions; 16 can generate an interrupt on input level/transition. ● Real time clock module with 32 kHz low power oscillator and separate power supply to continue running during standby mode. ● s ( t c u d o r P e let ● o s b – 16-bit Watchdog timer with 8 bits prescaler for system reliability and integrity. 2 CAN modules compliant with the CAN specification V2.0 part B (active) and bit rate can be programmed up to 1 MBaud. One additional CAN at 1 Mbps (for STA2058 EM SIP version) ● Four 16-bit programmable timers with 7 bit prescaler, up to two input capture/output compare, one pulse counter function, one PWM channel with selectable frequency each. ● 4 channels 12-bit sigma-delta analog to digital converter, single channel or multi channel conversion modes, single-shot or continuous conversion modes, sample rate 1 kHz, conversion range 0-2.5 V . ● Three serial communication interfaces (UART) allow full duplex, asynchronous, communications with external devices, independently programmable TX and RX baud rates up to 625 Kbaud. ● One UART adapted to suit smart card interface needs, for asynchronous SC as defined by ISO 7816-3. It includes SC clock generation. ● Two serial peripheral interfaces (SPI) allow full duplex, synchronous communications with external devices, master or slave operation, max baud rate of 5.5 Mb/s. One SPI may be used as multimedia card interface. O 3/20 Features summary STA2058 ● Two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 KHz), 7/10 bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2 x SPI + 1 x I2C or 1 x SPI + 2 x I2C may be used at a time. ● Enhanced interrupt controller supports 32 interrupt vectors, independently maskable, with interrupt vector table for faster response and 16 priority levels, software programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ. ● Wakeup unit allows exiting from power down modes by detection of an event on two external pins (one is active high and other is active low) or on internal real time clock alarm. ● USB unit V1.1 compliant, software configurable endpoint setting, USB suspend/resume support ● High level data link controller (HDLC) unit supports full duplex operating mode, NRZ, NRZI, FM0 and MANCHESTER modes, and internal 8-bit baud rate generator. ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 4/20 o r P STA2058 Pin description 2 Pin description 2.1 Logic symbol Figure 1. STA2058 TESEO symbol Power Pads V18 (2) A[23:0] V33 (7) D[15:0] VSS (10) WEn.[1:0] AVSS CSn.[3:0] AVDD V18BKP STA2058 TESEO o s b JTRSTn JTDO O ) DBGRQS BOOTEN s ( t c u d o P1.[15:0] o r P GeneraI Purpose I/O P2.[15:0] (LFBGA144 Only) e t le JTDI JTCK JTMS Debug ) s t( c u d P0.[15:0] CK CKOUT RSTINn JTAG Port LFBGA144 ONLY RDn GPSCLK Clock & Reset EMI Interface nSTDBY_I nSTDBY_O RTCXTO RTCXTI RTC & WKUP Pads WAKEUP nWAKEUP USBDN USBDP USB Pads GPSDAT[1] LFBGA144 Only GPSDAT[0] r P e t e l o s b O 5/20 System block diagram 3 STA2058 System block diagram Figure 2. STA2058 TESEO block diagram ARM7TDMI CPU 1 DP EMI 256K Flash 5 DP STC(JTAG) HPGPS 16-ch. correlator + Emerald DSP APB BRIDGE3 ARM7 Native BUS 64K RAM 39 DP + 8 AF RCCU PLL 2 AF SPI0 4 AF SPI1 4 AF UART0 2 AF UART1 2 AF TIMER3 UART2 2 AF RTC UART3 2 AF [USB] 3 DP [CAN0] 2 AF [CAN1] 2 AF HDLC 3 AF uc 4 AF od bs O 6/20 t(s TIMER2 2 AF t e l o 2 DP OSCILL 16 AF Wakeup 2 AF WATCHDOG 48 IO )- TIMER1 Fully Prog. I/O APB BUS ol s b O APB BUS TIMER0 4 AF e t e 2 AF I2C1 12-bit A/D Converter 4 AF o r P I2C0 Interrupt Contr. r P e c u d APB BRIDGE2 5 DP ) s t( APB BRIDGE1 VREG 3 DP 3 DP STA2058 System block diagram ybus YRAM xbus pbus xbus Acquisition Output Data INT APB bus Register Interface ISR ARM DA INT so t c u P e e t le HPGPS ) (s d o r AA 3 IP Ob HPGPS_EME top c u d RWA CSA AB DB RWB CSB o r P 1023x32 RAM B1 APB 1023x32 RAM A1 4 ) s t( 1023x32 RAM A0 ybus 1023x32 RAM B0 XBAR EMERALD INT pbus XRAM New HPGPS 16-ch including Emerald DSP 16-bit PRAM Figure 3. 2046x32bit RAM (*) (*) Maximum memory size addressable by HPGPS. The real value depends on the device specs t e l o s b O 7/20 System block diagram STA2058 3.1 Package LFBGA144 Table 2. Ball out for LFBGA144 package A B C D E F G H J K L M 1 P0.10/ U1.RX/ U1.TX P2.0/ CSn.0 P2.1/ CSn.1 VSS P2.2/ CSn.2 P2.6/ A.22 BOOTEN P2.12 P2.13 P2.15 JTDI NC 2 VSS RDN P0.11/ U1.TX/ BOOT.1 V33 P2.3/ CSn.3 P2.8 P2.9/ CAN1_TX JTMS JTRSTn 3 V33 P0.9/ U0.TX/ BOOT.0 P0.12/ SCCLK P0.13/ U2.RX/ T2.OCMP A P2.4/ A.20 NC P2.10/ CAN1_RX JTCK GPSDAT0 V33 P0.8/ P0.14/ U0.RX/U0. U2.TX/ TX T2.ICAPA P2.5/ A.21 VSS P2.11 JTDO CK CKOUT 4 P0.6/ S1.SCLK P0.7/ S1.SSN 5 A.19 WEn.1 WEn.0 P0.5/ S1.MOSI P2.7/ A.23 VSS P2.14 NC 6 P0.3/ S0.SSN/ I1.SDA A.15 A.16 A.17 A.18 V33 V18 V18 7 P0.2/ P0.1/ S0.SCLK/ S0.MOSI/ I1.SCL U3.RX P0.4/ S1.MISO VSS V18 A.14 D.12 GPSCLK GPSDAT1 uc od r P e ) s t( VSSREG VSS V33REG_B KP WAKEUP_ PA DBGRQS VSS P0.15/ WAKEUP RTCXTO RTCXTI V18BKP V18BKP D.1 D.0 nSTDBY_ O VSS18 RSTINn D.11 P1.12/ CANTX AVSS AVSS D.3 D.2 NC AVDD s b O t e l o VSSBKP nSTDBY_IN 8 A.9 A.10 A.11 A.13 P0.0/ S0.MISO/ U3.TX A.0 9 VSS18 V33 A.5 A.6 V33 D.15 D.10 P1.8/ PPS D.9 P1.0/ T3.OCMP B/ AIN.0 P1.15/ HTXD P1.13/ HCLK/ I0.SCL VSS D.14 USBDN P1.7/ T1.OCMP B D.8 P1.1/ P1.5/ T3.ICAPA/ T1.ICAPB AIN.1 D.4 P1.14/ HRXD/ I0.SDA P1.10/ USBCLK A.2 D.13 USBDP VSSIOPLL D.5 P1.3/ P1.4/ T3.ICAPB/ T1.ICAPA AIN.3 AVDD A.3 P1.9/ PRN.11 A.1 P1.11/ CANRX NC V33IO-PLL P1.6/ T1.OCMPA 10 A.8 V33 11 A.7 NC s b O 8/20 A.12 od r P e t e l o 12 A.4 t c u ) (s D.7 D.6 P1.2/ T3.OCMPA/ AIN.2 STA2058 3.2 System block diagram Package LQFP64 LQFP64 package outline 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P0.9/U0.TX/BOOT.0 P0.8/U0.RX/U0.TX P0.7/S1.SSN P0.6/S1.SCLK P0.5/S1.MOSI VSS V18 VSS18 P0.4/S1.MISO P0.3/S0.SSN/I1.SDA P0.2/S0.SCLK/I1.SCL P0.1/S0.MOSI/U3.RX P0.0/S0.MISO/U3.TX V33 VSS P1.15/HTXD Figure 4. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TESEO LQFP64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 e t le o s b P1.14/HRXD/I0.SDA P1.13/HCLK/I0.SCL P1.10/USBCLK P1.9/PRN.11 VSS P1.12/CANTX/USBDN P1.11/CANRX/USBDP P1.8/PPS P1.7/T1.OCMPA VSSIO-PLL V33IO-PLL P1.6/T1.OCMPB P1.5/T1.ICAPB P1.4/T1.ICAPA P1.3/T3.ICAPB/AIN.3 P1.2/T3.OCMPA/AIN.2 ) s t( c u d o r P 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.10/U1.RX/U1.TX P0.11/U1.TX/BOOT.1 P0.12/SCCLK VSS P0.13/U2.RX/T2.OCMPA P0.14/U2.TX/T2.ICAPA BOOTEN VSS V33 JTDI JTMS JTCK JTDO nJTRST GPSDAT GPSCLK V33REG_BKP VSSREG CK P0.15/WAKEUP RTCXTI RTCXTO nSTDBY_IN nRSTIN VSSBKP V18BKP V18 VSS18 AVDD AVSS P1.0/T3.OCMPB/AIN.0 P1.1/T3.ICAPA/AIN.1 O ) Remapped for bkp supply Double bond bw CAN & USB Pads s ( t c u d o r P e t e l o s b O 9/20 System block diagram 3.3 STA2058 Power supply pins Table 3. Power supply pins Symbol I/O LQFP 64 LFBGA144 V33 - Digital supply voltage for I/O circuitry (3.3 Volt) 9, 51 D2,A3,K3,F6,B9 , E9,B10 VSS - Digital ground for I/O circuitry 4, 8, 44, 50, 59 D1,A2,F4,L4,M 4, F5, D7,E10 V33IO-PLL - Digital supply voltage for I/O circuitry and for PLL reference (3.3V) 38 H12 VSSIO-PLL - Digital ground for I/O circuitry and for PLL reference 39 V33REG_B - Digital supply voltage for backup block I/O circuitry and for ballast I/O (3.3V) 17 - Digital ground for ballast I/O - Digital supply voltage for core circuitry (1.8 Volt): when using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 10μF (tantalum, low series resistance) + 33nF (ceramic) shall be connected between these pins and VSS18 to guarantee on-chip voltage stability. 27, 58 G6, H6,E7 - Digital Ground for core circuitry 28, 57 A9,L7 - Digital supply voltage for backup block (RTC, oscillator, Wake-up controller - 1.8 Volt): when using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 1μF shall be connected between this pin and VSSBKP to guarantee on-chip voltage stability. 26 J6,K6 KP VSSREG V18 VSS18 V18BKP 10/20 ) (s s b O t c u d o r M2 L3 - Digital Ground for backup logic 25 L6 AVDD - Analog supply voltage for the A/D converter 29 M9, M11 AVSS - Analog supply Ground for the A/D converter 30 J8,K8 t e l o s b O r P e t e l o uc od 18 ) s t( H11 P e VSSBKP Note: Function V33 and V33IO-PLL are all internally connected. Same for VSS and VSSIO-PLL. All VSS, VSS18, VSSBKP, AVSS pins must be tied together to the common ground plane, taking care of noise filtering, especially on AVSS STA2058 Electrical characteristic 4 Electrical characteristic 4.1 DC electrical characteristic V33 = 3.3 V ± 10 %, TA = -40 / 85 °C unless otherwise specified. Table 4. DC electrical characteristic Value Symbol Parameter Test conditions Min. VIH VIL Input high level CMOS With or w/o hysteresis 0.7V33 Input high level P0.15 (WAKEUP) only 1.8 Input low level CMOS With or w/o hysteresis Input low level P0.15 (WAKEUP) only VOH e t le o r P P0.15 (WAKEUP) only Output high level high current pins Push Pull, IOH= 8mA V33-0.8 Output high level standard current pins Push Pull, IOH= 4mA V33-0.8 VOL Output low level standard current pins RWPU Weak pull-up resistor RWPD Weak pull-down resistor e t e ol o r P du s ( t c ) s ( ct Input hysteresis Schmitt trigger o s b Unit V 0.3V33 0.4 O ) Max. du Input hysteresis CMOS Schmitt trigger VHYS Typ. 0.3 0.8 V V 0.7 V 1.2 V 0.5 V Push Pull, IOH= 8mA 0.4 V Push Pull, IOH= 4mA 0.4 V Measured at 0.5V33 100 kΩ Measured at 0.5V33 100 kΩ s b O 11/20 Electrical characteristic STA2058 4.2 AC electrical characteristics Table 5. AC electrical characteristics V33 = 3.3 V ± 10 %, TA = 27 °C unless otherwise specified. Value Symbol Mode System clock Unit Min. Typ. Max. IDDRUN RUN mode 33 MHz system clock 60 mA IDDWFI WFI mode 1 MHz system clock 5 mA IDDLP LPWFI mode 32 kHz system clock 300 µA IDDSTP STOP mode Main VReg off, Flash in power-down 200 IDDSB1 STANDBY_1 mode LP VReg and 32kHz Osc on 15 IDDSB0 STANDBY_0 mode LP VReg, LVD, 32kHz Osc bypassed 3 Note: ) s t( µA uc d o r 30 µA 10 µA IDDRUN is the consumption in applications exploiting the full performances of the core. A typical GPS application would run at 33MHz, at the maximum frequency (66MHz) the power consumption is IDDRUN = 150 mA (typ). P e et l o s In WFI mode the VReg and Flash are ON to guarantees the minimum interrupt response time. Table 6. b O - AC electrical characteristics V33 = 3.3 V ± 10%, TA = -40 / 85 °C unless otherwise specified. Symbol Mode (s) t c u od Unit Min. FCPU CPU max frequency FMAX Flash max frequency Executing from Flash Pr Value System clock Executing from RAM or EMI Max. 66 MHz 60 MHz e input filter characteristics nRSTIN t e ol 4.3 s b O Table 7. Symbol V33 = 3.3 V ± 10 %, TA = -40 / 85 °C unless otherwise specified. nRSTIN input filter characteristics Value Mode System clock Unit Min. tFR nRSTIN input filtered pulse tNFR nRSTIN input not filtered pulse 12/20 Typ. Typ. Max. 100 1.2 ns µs STA2058 4.4 Electrical characteristic Flash electrical characteristics V33 = 3.3 ± 10%, TA = -40 / 85 °C unless otherwise specified. Table 8. Flash program/erase characteristics 1 Value Symbol Parameter Test conditions Unit Typ Max (C0) Max (Cmax) tPW Word program 40 µs tPDW Double word program 60 µs tPB0 Bank 0 program (256K) Double word program 1.6 2.1 4.3 tPB1 Bank 1 program (16K) Double word program 130 170 300 tES Sector erase (64K) Not preprogrammed Preprogrammed 2.3 1.9 4.0 3.3 tES Sector erase (8K) Not preprogrammed Preprogrammed 0.7 0.6 1.1 1.0 uc tES Bank 0 erase (256K) Not preprogrammed Preprogrammed tES Bank 1 erase (16K) Not preprogrammed Preprogrammed tRPD Recovery from power-down tPSL Program suspend latency tESL Erase suspend latency ) s ( t b O - C0: TA = 85 °C after 0 cycles Cmax: TA = 85 °C after max number of cycles Table 9. Flash program/erase characteristics 2 e t e l Symbol o s b tESR 0.9 0.8 ) s t( ms s 1.36 1.26 s 13.7 11.2 17.2 14.0 s 1.5 1.3 1.87 1.66 s 20 µs 10 µs 300 µs Pr c u d Note: O l o s e t e 8.0 6.6 od 4.9 4.1 s o r P Parameter Value Conditions Unit Min Typ Max Endurance 10 Kcycles Endurance (Bank1 sectors) 100 Kcycles Data retention 20 Years 20 ms Erase suspend rate Min time from erase resume to next erase suspend 13/20 Electrical characteristic 4.5 STA2058 Oscillator electrical characteristics V33 = 3.3 ± 10 %, TA = -40 / 85 °C unless otherwise specified. Crystal oscillator and resonator RTCXTO DEVICE RTCXTI RTCXTO DEVICE RTCXTI Figure 5. ) s t( c u d RS CL Table 10. tSTUP so Parameter Oscillator transconductance Oscillator startup time o r P Value Test conditions (s) b O - Min Unit Typ Max μA/V 8 Stable VDD t c ADC electrical ucharacteristics d o r P e t e ol 4.6 e t le Oscillator electrical characteristics Symbol gm CL 2.5 s V33 = 3.3 ± 10%, AVDD = 3.3V ± 10%, TA = -40 / 85 °C unless otherwise specified. Table 11. Symbol s b O ADC electrical characteristics Parameter RES Resolution ΔVIN Input voltage range FMod Modulator oversampling frequency IBW Input bandwidth Nch Number of input channels PBR Passband ripple SINAD THD 14/20 Value Test conditions Unit Min Sinewave with ΔVIN amplitude Typ Max 12 0 bits 2.5 V 2.1 MHz FMod/40 96 kHz 4 n 0.1 dB S/N and distortion 56 63 dB Total harmonic distortion 60 74 dB STA2058 Table 11. Electrical characteristic ADC electrical characteristics (continued) Value Symbol Parameter Test conditions Unit Min ZIN Input impedance CIN Input capacitance IADC Power consumption TA=27 °C ISTBY Standby power consumption TA=27 °C 4.7 FMod = 2 MHz Typ Max 1 MΩ 2.5 5 pF 3.0 mA 1 µA ) s t( PLL electrical characteristics V33 = 3.3 ± 10 %, V33IOPLL= 3.3 ± 10 %, TA = -40 / 85 °C unless otherwise specified. Table 12. PLL electrical characteristics o r P Value Symbol Parameter Test conditions e t le Min TPLL1 PLL reference clock FREF_RANGE=0 TPLL2 PLL reference clock FREF_RANGE=1 MX[1:0]=’00’ or ‘01’ TPLL3 PLL reference clock FREF_RANGE=1 MX[1:0]=’10’ or ‘11’ TLOCK PLL lock time TLOCK PLL lock time e t e ol Pr ΔTJITTER PLL jitter (peak to peak) s b O 4.8 Typ Unit Max 1.5 3.0 MHz 3.0 8.25 MHz 3.0 6 MHz FREF_RANGE=0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE=1 Stable Input Clock Stable V33IOPLL, V18 600 µs 2 ns o s b O ) s ( t c u d o c u d TPLL = 4 MHz, MX[1:0]=’11’ Global Output division=32 (Output Clock=2 MHz) 0.7 LVD electrical characteristics V33 = 3.3 ± 10 %, TA = -40 / 85 °C unless otherwise specified. Table 13. LVD electrical characteristics Value Symbol Parameter Test conditions Unit Min TLVD LVD Threshold Main and LP LVD’s ΔV VLPREG - TLVD Main regulator off Typ 1.3 50 Max V mV 15/20 Electrical characteristic 4.9 STA2058 GPS performances V33 = 3.3 ± 10 %, TA = 27 °C, unless otherwise specified Table 14. GPS performances Value Symbol Parameter Test conditions Unit Min Reacquisition HOt start 50%, -130dBm, Fu 2ppm, Tu ± 2, Pu 30km TTFF Warm start Cold start Accuracy CEP 50%, 24hr static at 130dBm s