STF10NM60N

STI10NM60N N-channel 600 V, 0.53 Ω typ.,10 A MDmesh™ II Power MOSFET in I²PAK package Datasheet - obsolete product Features TAB 3 12 I2PAK Order code VDS @TJmax RDS(on) max. STI10NM60N 650 V < 0.55 Ω • 100% avalanche tested ID PTOT 10 A 70 W ) s ( ct u d o • Low input capacitance and gate charge Figure 1. Internal schematic diagram • Switching applications '7$% ) s ( ct * u d o 6 r P e t e l o bs O r P Applications e t e l o s Description b -O • Low gate input resistance $0Y This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Table 1. Device summary Order code Marking Package Packing STI10NM60N 10NM60N I²PAK Tube December 2015 This is information on a discontinued product. DocID15764 Rev 8 1/12 www.st.com Contents STI10NM60N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ........................... 6 3 Test circuits 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 .............................................. 8 ) s ( ct 2 I PAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 u d o r P e 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 t e l o ) (s s b O t c u d o r P e t e l o s b O 2/12 DocID15764 Rev 8 STI10NM60N 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Value Symbol VGS Parameter Gate- source voltage I²PAK Unit ± 25 V ID Drain current (continuous) at TC = 25 °C 10 A ID Drain current (continuous) at TC = 100 °C 5 A Drain current (pulsed) 32 IDM (1) PTOT dv/dt(2) ) s ( t A c u d Total dissipation at TC = 25 °C 70 Peak diode recovery voltage slope 15 o r P VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) TJ Tstg Operating junction temperature Storage temperature e t e l - 55 to 150 W V/ns V °C o s b 1. Pulse width limited by safe operating area. 2. ISD ≤ 10 A, di/dt ≤ 400 A/µs, VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS. O ) Table 3. Thermal data t(s Symbol O I²PAK Unit Rthj-case Thermal resistance junction-case max. 1.79 °C/W Rthj-amb Thermal resistance junction-ambient max. 62.50 °C/W Rthj-pcb Thermal resistance junction-pcb max. e t e ol bs c u d Value Parameter o r P Symbol °C/W Table 4. Avalanche characteristics Parameter Value Unit IAS Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max.) 4 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAS, VDD = 50 V) 200 mJ DocID15764 Rev 8 3/12 12 Electrical characteristics 2 STI10NM60N Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5. On /off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 ID = 1 mA, VGS = 0, TC = 150 °C IDSS Zero-gate voltage drain current (VGS = 0) VDS = 600 V VDS = 600 V, TC = 125 °C IGSS Gate-body leakage current (VDS = 0) VGS = ± 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A Min. 600 Typ. Max. Unit V 650 (s) 1 100 µA µA ± 100 nA t c u od r P e 3 4 V 0.53 0.55 Ω Min. Typ. Max. Unit - 540 - pF - 44 - pF - 1.2 - pF 2 t e l o s b O Table 6. Dynamic Symbol ct Ciss Input capacitance Coss Output capacitance Crss Test conditions VDS = 50 V, f = 1 MHz, VGS = 0 Reverse transfer capacitance Equivalent capacitance time related VDS = 0 to 480 V, VGS = 0 - 110 - pF Rg Gate input resistance f =1 MHz open drain - 6 - Ω Qg Total gate charge - 19 - nC - 3 - nC - 10 - nC e t e l O du o r P Coss eq(1) o s b ) (s Parameter Qgs Gate-source charge Qgd Gate-drain charge VDD = 480 V, ID = 8 A, VGS = 10 V 1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 4/12 DocID15764 Rev 8 STI10NM60N Electrical characteristics Table 7. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Min. Typ. - 10 - ns - 12 - ns - 32 - ns - 15 - ns Turn-on delay time Rise time VDD = 300 V, ID = 4 A, RG = 4.7 Ω, VGS = 10 V Turn-off-delay time Fall time Table 8. Source-drain diode Symbol Parameter Test conditions ISD ISDM(1) Source-drain current Source-drain current (pulsed) VSD(2) Forward on voltage trr Qrr Reverse recovery charge IRRM Reverse recovery current trr ISD = 8 A, di/dt = 100 A/µs VDD= 60 V let o s b Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current u d o r P e Reverse recovery time ISD = 8 A, di/dt = 100 A/µs VDD= 60 V TJ = 150 °C O ) ) s ( ct Min. Typ. Max. Unit - ISD = 8 A, VGS = 0 Max. Unit - 8 32 A A 1.3 V - 250 ns - 2.12 µC 17 A 315 ns 2.6 µC 16.5 A - s ( t c 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% u d o r P e t e l o s b O DocID15764 Rev 8 5/12 12 Electrical characteristics STI10NM60N Electrical characteristics (curves) 2.1 Figure 2. Safe operating area for I²PAK Figure 3. Thermal impedance for I²PAK AM03944v1 ID (A) 1µs 10 D S( on ) O Li per m at ite io d ni by n m this ax a R rea is 10µs 1 100µs 1ms 10ms ) s ( ct Tj=150°C Tc=25°C 0.1 Single pulse 0.01 0.1 10 1 100 u d o VDS(V) Figure 4. Output characteristics ID (A) 14 r P e Figure 5. Transfer characteristics AM03947v1 VGS=10V ID (A) t e l o 14 6V 12 s b O AM03948v1 VDS=20V 12 10 10 )- 8 8 s ( t c 6 6 5V 4 2 0 0 u d o r P e 5 10 20 15 t e l o 25 2 4V 30 s b O AM09028v1 VDS ID=1mA 1.10 0 0 VDS(V) Figure 6. Normalized VDS vs. temperature (norm) 4 2 4 6 8 10 VGS(V) Figure 7. Static drain-source on-resistance AM00891v1 RDS(on) (Ω) 0.56 1.08 1.06 0.52 1.04 1.02 0.48 1.00 VGS=10V 0.98 0.44 0.96 0.94 0.92 -50 -25 6/12 0 25 50 75 100 TJ(°C) 0.40 0 DocID15764 Rev 8 2 4 6 8 ID(A) STI10NM60N Electrical characteristics Figure 8. Gate charge vs. gate-source voltage Figure 9. Capacitance variations AM03951v1 VGS (V) VDD=480V 12 ID=4A 1000 VDS 10 AM03952v1 C (pF) Ciss 8 100 6 Coss 4 10 ) s ( ct 2 Crss 0 0 10 5 20 15 1 0.1 Qg(nC) Figure 10. Normalized gate threshold voltage vs. temperature VGS(th) (norm) RDS(on) (norm) 2.1 100 u d o r P e t e l o ID=250µA 10 VDS(V) Figure 11. Normalized on-resistance vs. temperature AM03953v1 1.10 1.9 s b O AM03954v1 ID=4A VGS=10V 1.7 1.00 )- 0.90 s ( t c 0.80 0.70 -50 -25 1 0 e t e ol Pr u d o 25 50 75 100 TJ(°C) 1.5 1.3 1.1 0.9 0.7 0.5 -50 -25 0 25 50 75 100 TJ(°C) s b O DocID15764 Rev 8 7/12 12 Test circuits 3 STI10NM60N Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. VG c u d 47kΩ 1kΩ AM01468v1 e t e ol Figure 14. Test circuit for inductive load switching and diode recovery times A A G D.U.T. FAST DIODE B B S s ( t c 3.3 μF B 25 Ω D 1000 μF RG S r P e s b O 2200 μF 3.3 μF VDD ID Vi D.U.T. Pw let AM01470v1 AM01471v1 Figure 16. Unclamped inductive waveform b O AM01469v1 L VD VDD u d o G so )- L=100μH o r P Figure 15. Unclamped inductive load test circuit A D ) s ( t 2.7kΩ PW PW D.U.T. Figure 17. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/12 0 DocID15764 Rev 8 10% AM01473v1 STI10NM60N 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. I2PAK package information 4.1 Figure 18. I2PAK (TO-262) package outline ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 0004982_Rev_H DocID15764 Rev 8 9/12 12 Package information STI10NM60N Table 9. I²PAK (TO-262) package mechanical data mm Dim. Min. Typ. A 4.40 4.60 A1 2.40 2.72 b 0.61 0.88 b1 1.14 1.70 c 0.49 0.70 c2 1.23 1.32 D 8.95 9.35 e 2.40 e1 4.95 E 10 L 13 L1 3.50 L2 1.27 ) s ( ct du 2.70 ete ol ) (s s b O t c u d o r P e t e l o s b O 10/12 Max. DocID15764 Rev 8 o r P 5.15 10.40 14 3.93 1.40 STI10NM60N 5 Revision history Revision history Table 10. Document revision history Date Revision Changes 10-Jun-2009 1 First release 12-Jan-2010 2 Figure 4: Safe operating area for TO-220FP has been corrected 31-Mar-2010 3 Features have been corrected 17-Sep-2010 4 Content reworked to improve readability 24-Nov-2010 5 Corrected ID value 16-Nov-2012 6 Inserted new package and mechanical data: I²PAK 18-Jul-2013 7 Updated Section 4: Package mechanical data. Minor text changes. 02-Dec-2015 8 Part numbers STD10NM60N, STF10NM60N, STP10NM60N, STU10NM60N have been moved to a separate datasheet. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O DocID15764 Rev 8 11/12 12 STI10NM60N ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r IMPORTANT NOTICE – PLEASE READ CAREFULLY P e STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. t e l o s b O Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID15764 Rev 8