STF7N52K3

STD7N52K3, STP7N52K3 Datasheet N-channel 525 V, 0.72 Ω typ., 6 A, MDmesh™ K3 Power MOSFETs in DPAK and TO-220 packages Features Order codes TAB TAB STD7N52K3 2 3 1 STP7N52K3 TO-220 DPAK 1 2 3 D(2, TAB) • • • • • VDS RDS(on) max. ID PTOT 525 V 0.85 Ω 6A 90 W 100% avalanche tested Extremely high dv/dt capability Very low intrinsic capacitance Improved diode reverse recovery characteristics Zener-protected Applications G(1) • Switching applications Description S(3) AM01475V1 These MDmesh™ K3 Power MOSFETs are the result of improvements applied to STMicroelectronics’ MDmesh™ technology, combined with a new optimized vertical structure. These devices boast an extremely low on-resistance, superior dynamic performance and high avalanche capability, rendering them suitable for the most demanding applications. Product status links STD7N52K3 STP7N52K3 Product summary STD7N52K3 Order code STD7N52K3 Marking 7N52K3 Package DPAK Packing Tape and reel STP7N52K3 Order code STP7N52K3 Marking 7N52K3 Package TO-220 Packing Tube DS5889 - Rev 6 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD7N52K3, STP7N52K3 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit ±30 V Drain current (continuous) at TC = 25 °C 6 A Drain current (continuous) at TC = 100 °C 3.8 A IDM(1) Drain current (pulsed) 24 A PTOT Total dissipation at TC = 25 °C 90 W IAR(2) Avalanche current, repetitive or non-repetitive 3 A EAS(3) Single pulse avalanche energy 100 mJ ESD Gate-source human body model (C = 100 pF, R = 1.5 kΩ) 2.5 kV Peak diode recovery voltage slope 12 V/ns -55 to 150 °C VGS Parameter Gate-source voltage ID dv/dt(4) Tstg Storage temperature range TJ Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. Pulse width is limited by TJmax. 3. Starting TJ = 25 °C, ID = IAR, VDD = 50 V 4. ISD ≤ 6 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 80% V(BR)DSS Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Rthj-amb Parameter Value DPAK Thermal resistance junction-case Thermal resistance junction-pcb Thermal resistance junction-ambient TO-220 1.39 Unit °C/W 50 °C/W 62.5 °C/W 1. When mounted on an 1-inch² FR-4, 2oz Cu board. DS5889 - Rev 6 page 2/21 STD7N52K3, STP7N52K3 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On/off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. ID = 1 mA, VGS = 0 V Typ. 525 Zero gate voltage drain current IGSS Gate body leakage current VGS = ±20 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3 A VGS = 0 V, VDS = 525 V, TC = 125 1 µA 50 µA ±10 µA 3.75 4.5 V 0.72 0.85 Ω Typ. Max. Unit - pF °C(1) 3 Unit V VGS = 0 V, VDS = 525 V IDSS Max. 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Test conditions Min. 870 VDS = 50 V, f = 1 MHz, VGS = 0 V - Reverse transfer capacitance (1) 70 13 Equivalent output capacitance VDS = 0 to 420 V, VGS = 0 V, - 53 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 3.5 - Ω Qg Total gate charge VDD = 420 V, ID = 6 A, Qgs Gate-source charge VGS = 0 to 10 V - nC Gate-drain charge (see Figure 17. Test circuit for gate charge behavior) Coss(tr) Qgd 33 - 6 21 1. Coss(tr) is defined as the constant equivalent capacitance giving the same storage energy as Coss when VDS increases from 0 to 420 V. Table 5. Switching times Symbol td(on) tr td(off) tf DS5889 - Rev 6 Parameter Test conditions Turn-on delay time VDD = 260 V, ID = 3 A, Rise time RG = 4.7 Ω, VGS = 10 V Turn-off delay time (see Figure 16. Test circuit for resistive load switching times and Figure 21. Switching time waveform) Fall time Min. Typ. Max. Unit - ns 13 11 - 36 19 page 3/21 STD7N52K3, STP7N52K3 Electrical characteristics Table 6. Source-drain diode Symbol ISD Parameter Test conditions Source-drain current Typ. Source-drain current (pulsed) VSD(2) Forward on voltage ISD = 6 A, VGS = 0 V trr Reverse recovery time ISD = 6 A, di/dt = 100 A/µs, Qrr Reverse recovery charge IRRM Reverse recovery current VDD = 60 V (see Figure 18. Test circuit for inductive load switching and diode recovery times) trr Reverse recovery time ISD = 6 A, di/dt = 100 A/µs, Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C Reverse recovery current (see Figure 18. Test circuit for inductive load switching and diode recovery times) 24 - - - Max. 6 - ISDM(1) IRRM Min. 1.5 Unit A V 220 ns 1.8 μC 16 A 250 ns 2.2 μC 18 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Table 7. Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS = ±1 mA, ID = 0 A Min. Typ. Max. Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DS5889 - Rev 6 page 4/21 STD7N52K3, STP7N52K3 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area for DPAK AM08952v1 ID (A) Tj=150°C Tc=25°C S ingle puls e Figure 2. Thermal impedance for DPAK GC20460 K 10µs 101 n) (o 100µs DS Op Lim e ra ite tio n d by in th m is ax ar R e a is 100 100 1ms 10-1 10ms 10-1 10-1 100 VDS (V) 102 101 Figure 3. Safe operating area for TO-220 10-2 10-5 10-4 10-3 10-2 tp (s) 10-1 Figure 4. Thermal impedance for TO-220 AM08950v1 ID (A) Tj=150°C Tc=25°C S ingle puls e 101 n) (o 100µs DS Op Lim e ra ite tio n d by in th m is ax ar R ea is 10µs 100 1ms 10ms 10-1 10-1 100 102 101 VDS (V) Figure 5. Output characteristics Figure 6. Transfer characteristics AM08953v1 ID (A) AM08954v1 ID (A) VDS = 8 V 9 10 VGS =10V 8 7 8 6 6 5 4 4 3 6V 2 2 1 0 DS5889 - Rev 6 0 1 2 3 4 5 6 7 8 5V 9 VDS (V) 0 0 1 2 3 4 5 6 7 8 9 VGS (V) page 5/21 STD7N52K3, STP7N52K3 Electrical characteristics (curves) Figure 7. Normalized V(BR)DSS vs temperature AM08961v1 V(BR)DSS (norm) 1.10 Figure 8. Static drain-source on-resistance AM08956v1 R DS (on) (Ω) 0.88 VGS =10V 0.84 0.80 1.05 0.76 0.72 1.00 0.68 0.95 0.64 0.90 -75 0.60 -25 25 75 125 TJ (°C) Figure 9. Output capacitance stored energy AM08958v1 E os s (µJ ) 4.5 4.0 0 2 1 4 3 5 6 ID(A) Figure 10. Capacitance variations AM08957v1 C (pF) 1000 Cis s 3.5 3.0 100 2.5 2.0 Cos s 1.5 10 1.0 Crs s 0.5 0 0 100 200 300 400 500 VDS (V) Figure 11. Gate charge vs gate-source voltage VGS (V) AM08955v1 12 VDD=420V ID=6A VDS 300 8 250 6 200 150 4 100 2 0 0 1 100 10 VDS (V) Figure 12. Normalized on-resistance vs temperature AM08960v1 R DS (on) (norm) 2.5 VGS = 10 V 350 10 DS5889 - Rev 6 450 VDS (V) 400 1 0.1 2.0 1.5 1.0 0.5 50 10 20 30 0 Q g (nC) 0 -75 -25 25 75 125 TJ (°C) page 6/21 STD7N52K3, STP7N52K3 Electrical characteristics (curves) Figure 13. Normalized gate threshold voltage vs temperature Figure 14. Maximum avalanche energy vs temperature (norm) 120 1.10 110 100 90 80 70 60 ID = 50 μΑ 1.00 0.90 50 40 30 20 10 0 0 0.80 0.70 -75 -25 25 75 TJ (°C) 125 AM08963v1 E AS (mJ ) AM08959v1 VGS (th) ID=3A VDD=50 V 20 40 60 80 100 120 140 TJ (°C) Figure 15. Source-drain diode forward characteristics AM08962v1 VS D (V) 0.9 TJ =-50°C 0.8 TJ =25°C 0.7 0.6 0.5 0.4 0.3 DS5889 - Rev 6 TJ =150°C 0 1 2 3 4 5 6 7 8 IS D(A) page 7/21 STD7N52K3, STP7N52K3 Test circuits 3 Test circuits Figure 16. Test circuit for resistive load switching times Figure 17. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 18. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 19. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 21. Switching time waveform Figure 20. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS5889 - Rev 6 page 8/21 STD7N52K3, STP7N52K3 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS5889 - Rev 6 page 9/21 STD7N52K3, STP7N52K3 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 22. DPAK (TO-252) type A2 package outline 0068772_type-A2_rev25 DS5889 - Rev 6 page 10/21 STD7N52K3, STP7N52K3 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS5889 - Rev 6 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 11/21 STD7N52K3, STP7N52K3 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 23. DPAK (TO-252) type C2 package outline 0068772_C2_25 DS5889 - Rev 6 page 12/21 STD7N52K3, STP7N52K3 DPAK (TO-252) type C2 package information Table 9. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.30 2.38 A1 0.90 1.01 1.10 A2 0.00 0.10 b 0.72 0.85 b4 5.13 c 0.47 0.60 c2 0.47 0.60 D 6.00 D1 5.10 E 6.50 E1 5.20 e 2.186 2.286 2.386 H 9.80 10.10 10.40 L 1.40 1.50 1.70 L1 L2 6.20 5.60 6.60 6.70 5.50 0.90 1.25 0.51 BSC 0.60 L6 DS5889 - Rev 6 6.10 5.46 2.90 REF L3 L4 5.33 0.80 1.00 1.80 BSC θ1 5° 7° 9° θ2 5° 7° 9° V2 0° 8° page 13/21 STD7N52K3, STP7N52K3 DPAK (TO-252) type C2 package information Figure 24. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS5889 - Rev 6 page 14/21 STD7N52K3, STP7N52K3 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 25. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS5889 - Rev 6 page 15/21 STD7N52K3, STP7N52K3 DPAK (TO-252) packing information Figure 26. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS5889 - Rev 6 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 16/21 STD7N52K3, STP7N52K3 TO-220 type A package information 4.4 TO-220 type A package information Figure 27. TO-220 type A package outline 0015988_typeA_Rev_21 DS5889 - Rev 6 page 17/21 STD7N52K3, STP7N52K3 TO-220 type A package information Table 11. TO-220 type A package mechanical data Dim. mm Min. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 DS5889 - Rev 6 Typ. 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 page 18/21 STD7N52K3, STP7N52K3 Revision history Table 12. Document revision history Date Version Changes 07-Jul-2008 1 First release. 10-Sep-2009 2 Document status promoted from preliminary data to datasheet. 27-Jun-2011 3 Section 2.1: Electrical characteristics (curves) has been updated. 07-Mar-2012 4 Updated Section 4: Package mechanical data. Minor text changes. Part numbers STB7N52K3 and STF7N52K3 have been moved to a different datasheet, and the document has been updated accordingly. Updated features and description on cover page. 11-Jul-2018 5 Updated Table 1. Absolute maximum ratings. Updated Section 4.1 DPAK (TO-252) type A2 package information. Minor text changes. 01-Aug-2018 DS5889 - Rev 6 6 Updated Table 1. Absolute maximum ratings. page 19/21 STD7N52K3, STP7N52K3 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 DPAK (TO-252) type C2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 TO-220 type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DS5889 - Rev 6 page 20/21 STD7N52K3, STP7N52K3 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS5889 - Rev 6 page 21/21