STG4260
Low voltage 0.5 Ω dual SPDT switch with
break-before-make feature and 15 kV ESD protection
Features
■
Wide operating voltage range:
VCC (OPR) = 1.65 to 4.8 V
■
Low power dissipation:
ICC = 0.2 µA (max.) at TA = 85 °C
■
Low "ON" resistance:
– RON = 0.75 Ω (TA = 25 ºC) at
VCC = 2.25 V
– RON = 0.50 Ω (TA = 25 ºC) at
VCC = 3.0 V
– RON = 0.40 Ω (TA = 25 ºC) at
VCC = 4.3 V
■
Flip-chip 12
Separate supply voltage for switch and control
pin
■
Latch-up performance exceeds 100 mA per
JESD 78, Class II
■
ESD performance tested on common pin
(D pin):
– 15 kV IEC-61000-4-2 ESD, contact
discharge
– 8 kV HBM JESD22 A114-B Class II
■
ESD performance tested on S1 and S2 pin:
– 8 kV IEC-61000-4-2 ESD, contact
discharge
■
ESD performance test on all other pins:
– 4 kV HBM (JESD22 A114-B Class II)
– 400 V machine model (JESD22 A115-A)
– 1500 V charged-device model
(JESD22 C101)
Applications
■
Mobile phones
Table 1.
April 2009
Description
The STG4260 is a high-speed CMOS low voltage
dual analog SPDT (single pole dual throw) switch
or 2:1 multiplexer/demultiplexer switch fabricated
in silicon gate C2MOS technology. It is designed
to operate from 1.65 V to 4.8 V, making this device
ideal for portable applications. It offers low ONresistance (0.40 Ω typ.) at VCC = 4.3 V. The SEL
inputs are provided to control the switches.
The switch S1 is ON (connected to common port
D) when the SEL input is held high and OFF (high
impedance state exists between the two ports)
when SEL is held low; the switch S2 is ON (it is
connected to common Port D) when the SEL input
is held low and OFF (high impedance state exists
between the two ports) when SEL is held high.
Additional key features are fast switching speed,
break-before-make delay time and ultra low power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.
Device summary
Order code
Package
Packing
STG4260BJR
Flip-chip 12
Tape and reel
Doc ID 15168 Rev 2
1/19
www.st.com
19
Contents
STG4260
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
Doc ID 15168 Rev 2
STG4260
Pin settings
1
Pin settings
1.1
Pin connections
Figure 1.
Pin connection
"UMPVIEW
3%,
4OPVIEW
3
$
3
,
6
'.$
'.$
##
6
3%,
3
$
3
!-6
1.2
Pin description
Table 2.
Pin assignment
Pin number
Symbol
1
SEL2
2
VL
3
SEL1
4
1S1
Independent channel for switch 1
5
GND
Ground (0 V)
6
2S1
Independent channel for switch 2
7
D2
Common channel for switch 2
8
GND
9
D1
Common channel for switch 1
10
1S2
Independent channel for switch 1
11
VCC
Positive supply voltage
12
2S2
Independent channel for switch 2
Doc ID 15168 Rev 2
Name and function
Selection control for switch 2
Logic supply voltage
Selection control for switch 1
Ground (0 V)
3/19
Logic diagram
2
STG4260
Logic diagram
Figure 2.
Functional diagram
SEL1
1S1
D1
1S2
2S1
D2
2S2
SEL2
Figure 3.
Circuit equivalent logic
S2
S1
Table 3.
Truth table
SEL
Switch S1
Switch S2
H
ON
OFF (1)
L
OFF (1)
ON
1. High impedance
4/19
Doc ID 15168 Rev 2
STG4260
3
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4.
Absolute maximum ratings
Symbol
Value
Unit
Supply voltage
-0.5 to 5.5
V
VL
Logic supply voltage
-0.5 to 5.5
V
VI
DC input voltage
-0.5 to VCC + 0.5
V
VIC
DC control input voltage
-0.5 to VL + 5.5
V
VO
DC output voltage
-0.5 to VCC + 0.5
V
IIKC
DC input diode current on control pin (VSEL < 0 V)
- 50
mA
IIK
DC input diode current (VSEL < 0 V)
± 50
mA
IOK
DC output diode current
± 20
mA
IO
DC output current
± 300
mA
IOP
DC output current peak (pulse at 1ms, 10% duty cycle)
± 500
mA
± 100
mA
500
mW
-65 to 150
°C
260
°C
VCC
Parameter
ICC or IGND DC VCC or ground current
PD
Power dissipation at TA = 70ºC
Tstg
Storage temperature
TL
1.
(1)
Lead temperature (10 sec)
Derate above 70 ºC by 18.5 mW/C
Table 5.
Recommended operating conditions
Symbol
VCC
Parameter
Supply voltage
voltage(1)
Value
Unit
1.65 to 4.8
V
1.65 to VCC
V
0 to VCC
V
0 to VL
V
VL
Logic supply
VI
Input voltage
VIC
Control input voltage
VO
Output voltage
0 to VCC
V
Top
Operating temperature
-40 to 85
°C
dt/dv
Input rise and fall time control
input
VL = 1.65 to 2.7 V
0 to 20
VL= 3.0 to 4.8 V
0 to 10
ns/V
1. VL pin should not be left floating.
Doc ID 15168 Rev 2
5/19
Electrical characteristics
STG4260
4
Electrical characteristics
Table 6.
DC specifications
Value
Symbol
VIH
VIL
Parameter
High level
input voltage
Low level
input voltage
VCC
(V)
VL
(V)
Test
condition
Typ
Max
Min
Max
1.65 – 1.95
1.25
–
–
1.25
–
2.3 – 2.7
1.75
–
–
1.75
–
3.0 – 3.6
2.34
–
–
2.34
–
4.3
2.80
–
–
2.80
–
1.65 – 1.95
–
–
0.6
–
0.6
2.3 – 2.7
–
–
0.8
–
0.8
3.0 – 3.6
–
–
1.05
–
1.05
4.3
–
–
1.5
–
1.5
–
1.5
2.5
–
3.7
–
0.75
1.0
–
1.3
–
0.50
0.65
–
0.8
–
0.45
0.55
–
0.7
4.3
–
0.40
0.50
–
0.65
1.8
–
40
–
–
–
–
20
–
–
–
–
10
–
–
–
–
10
–
–
–
4.3
–
10
–
–
–
1.8
–
1000
1700
–
2000
–
300
430
–
550
–
170
220
–
270
–
160
210
–
270
–
160
210
–
270
1.65 – 4.3
1.65 – 4.3
3
V
1.65 – 4.3
3.7
ΔRON
ON resistance
match
between
channels (1)
2.25
3
1.65 – 4.3
3.7
2.25
RFLAT
ON resistance
flatness(2)
3
Unit
V
2.25
ON resistance
-40 to 85 °C
Min
1.8
RON
TA = 25 °C
1.65 – 4.3
3.7
VS = 0 V to
VCC
IS = 100 mA
VS = 0 V to
VCC
IS = 100 mA
VS = 0 V to
VCC
IS = 100 mA
4.3
Ω
mΩ
mΩ
IOFF
Sn OFF state
leakage
current
4.3
4.3
VS = 0.3 to 4.0
VD = 0.3 to 4.0
-30
–
30
-300
300
nA
ION
Sn ON state
leakage
current
4.3
4.3
VS = 0.3 to 4.0
VD = open
-30
–
30
-300
300
nA
ID
D ON state
leakage
current
4.3
4.3
-30
–
30
-300
300
nA
6/19
VS = open
VD = 0.3 to 4.0
Doc ID 15168 Rev 2
STG4260
Table 6.
Electrical characteristics
DC specifications (continued)
Value
Symbol
VCC
(V)
Parameter
VL
(V)
Test
condition
TA = 25 °C
-40 to 85 °C
Min
Typ
Max
Min
Max
Unit
ICC
Quiescent
1.65 – 4.3
supply current
1.65 – 4.3
VSEL= VCC or
GND
-0.05
–
0.05
-0.2
0.2
μA
ISEL
SEL leakage
current
1.65 – 4.3
VSEL= 4.3V or
GND
-0.2
–
0.2
-2
2
μA
1.65 – 4.3
1. ΔRON = RON(Max) - RON(Min)
2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal ranges.
Table 7.
AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤5 ns)
Value
Symbol
Parameter
VCC
VL
(V)
(V)
Test
conditions
Propagation
delay
2.3 – 2.7
3.0 – 3.3
Typ
Max
Min
Max
–
0.18
–
–
–
–
0.14
–
–
–
–
0.12
–
–
–
–
0.12
–
–
–
–
70
123
–
160
RL = 50 Ω
–
48
62
–
80
CL = 30 pF
–
33
43
–
56
–
29
38
–
49
–
36
45
–
60
RL = 50 Ω
–
35
47
–
62
CL = 30 pF
–
30
40
–
51
–
29
38
–
50
10
42
–
–
–
RL = 50 Ω
10
22
–
–
–
VS = VCC/2
5
15
–
–
–
5
12
–
–
–
1.65 –
4.3
tON
TURN-ON time
2.3 – 2.7
1.65 –
4.3
3 – 3.6
VS = VCC
4.3
1.65 –
1.95
tOFF
TURN-OFF
time
2.3 – 2.7
1.65 –
4.3
3 – 3.6
tD
Break-beforemake time
delay
2.3 – 2.7
3 – 3.6
1.65 –
4.3
ns
VS = VCC
4.3
1.65 –
1.95
Unit
ns
3.6 – 4.3
1.65 –
1.95
-40 to 85°C
Min
1.65-1.95
tPLH, tPHL
TA = 25°C
ns
CL = 35 pF
4.3
Doc ID 15168 Rev 2
ns
7/19
Electrical characteristics
Table 7.
STG4260
AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤5 ns) (continued) (continued)
Value
Symbol
Parameter
VCC
VL
(V)
(V)
Test
conditions
1.65 –
1.95
Q
Charge
injection
2.3 – 2.7 1.65-4.3
3.0 – 3.3
CL = 1nF
VGEN = 0 V
3.6 – 4.3
VS = 1VRMS
f = 100 kHz
OIRR
Off isolation(1)
1.65 –
4.3
4.3
VS = 1VRMS
f = 1 MHz
VS = 1VRMS
f = 5 MHz
VS = 1VRMS
f = 100 kHz
Xtalk
Crosstalk
1.65 –
4.3
4.3
VS = 1VRMS
f = 1 MHz
VS = 1VRMS
f = 5 MHz
TA = 25°C
-40 to 85°C
Unit
Min
Typ
Max
Min
Max
–
83
–
–
–
–
98
–
–
–
–
114
–
–
–
–
140
–
–
–
–
77
–
–
–
–
67
–
–
–
–
50
–
–
–
–
80
–
–
–
–
67
–
–
–
–
50
–
–
–
–
0.01
–
–
–
%
–
50
–
–
–
MHz
pC
dB
dB
RL = 600 Ω
THD
Total harmonic
distortion
CL = 50 pF
2.3 – 4.3
4.3
VS = VCC VPP
f = 600 Hz to
20 kHz
BW
1.
-3dB bandwidth
(switch ON)
1.65 –
4.3
4.3
RL = 50 Ω
OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch
8/19
Doc ID 15168 Rev 2
STG4260
Table 8.
Electrical characteristics
Capacitive characteristics
Value
Symbol
Parameter
VCC
VL
(V)
(V)
Test
condition
TA = 25 °C
-40 to 85 °C
Min
Typ
Max
Min
Max
Unit
CSEL
Control pin
input
capacitance
1.8 – 4.3
1.8 – 4.3 VL = VCC
–
30
–
–
–
pf
CSN
Sn port
capacitance
1.8 – 4.3
1.8 – 4.3 VL = VCC
–
94
–
–
–
pf
CD
D port
capacitance
1.8 – 4.3
when the switch
is enabled
1.8 – 4.3 VL = VCC
–
227
–
–
–
pf
Doc ID 15168 Rev 2
9/19
Test circuits
5
STG4260
Test circuits
Figure 4.
ON resistance
I
DS
V
V CC
D
S1
VS
S2
IN
GND
GND
CS14071
Figure 5.
Bandwidth
V
CC
D
S1
V
OUT
S2
V
IN
CC
GND
CS00371
10/19
Doc ID 15168 Rev 2
STG4260
Test circuits
Figure 6.
OFF leakage
V
CC
I
I
S(OFF)
D(OFF)
D
A
A
V
SS
V
D
S2
IN
V
CC
GND
CS14081
Figure 7.
Channel-to-channel crosstalk
CS14091
Doc ID 15168 Rev 2
11/19
Test circuits
STG4260
Figure 8.
OFF isolation
V
CC
S1
V OUT
50 Ω
S2
IN
GND
VS
GND
CS00381
Figure 9.
Test circuit
1. CL = 5/35 pF or equivalent: (includes jig capacitance)
2. RL = 50 Ω or equivalent
3. RT = ZOUT of pulse generator (typically 50 Ω )
12/19
Doc ID 15168 Rev 2
STG4260
Test circuits
Figure 10. Break-before-make time delay
Figure 11. Switching time and charge injection
(VGEN = 0 V, RGEN = 0 Ω, RL = 1 MΩ, CL = 100 pF)
Figure 12. Turn ON, turn OFF delay time
Doc ID 15168 Rev 2
13/19
Package mechanical data
6
STG4260
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. Package outline for Flip-chip 12 (1.9 x 1.4 x 0.58 mm) - 0.50 mm pitch
8153682
14/19
Doc ID 15168 Rev 2
STG4260
Package mechanical data
Table 9.
Mechanical data for Flip-chip 12 (1.9 x 1.4 x 0.58 mm) - 0.50 mm pitch
Millimeters
Symbol
Min
Typ
Max
A
0.535
0.58
0.625
A1
0.18
0.205
0.23
A2
0.355
0.375
0.395
b
0.215
0.255
0.295
D
1.85
1.9
1.95
D1
–
1.5
–
e
0.45
0.5
0.55
E
1.35
1.4
1.45
E1
–
1
–
SD
–
0.25
–
f
0.19
0.2
0.21
ccc
–
0.08
–
Figure 14. Footprint recommendation
8153682
Doc ID 15168 Rev 2
15/19
Package mechanical data
STG4260
Figure 15. Tape information for Flip-chip 12 (1.9 x 1.4 x 0.58 mm) - 0.50 mm pitch
Figure 16. Tape orientation for Flip-chip 12 (1.9 x 1.4 x 0.58 mm) - 0.50 mm pitch
5SERDIRECTIONOFFEED
!-6
16/19
Doc ID 15168 Rev 2
STG4260
Package mechanical data
Figure 17. Reel information for Flip-chip 12 (1.9 x 1.4 x 0.58 mm) - 0.50 mm pitch
Doc ID 15168 Rev 2
17/19
Revision history
7
STG4260
Revision history
Table 10.
18/19
Document revision history
Date
Revision
Changes
19-Nov-2008
1
Initial release.
20-Apr-2009
2
Document status promoted from preliminary data to datasheet.
Modified: Table 6: DC specifications on page 6 and Section 6.
Doc ID 15168 Rev 2
STG4260
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Doc ID 15168 Rev 2
19/19