STLQ020J33R

STLQ020 Datasheet 200 mA ultra-low quiescent current LDO Features Flip-Chip4 DFN6-2x2 S OT323-5L • • • • Operating input voltage range: 2 V to 5.5 V Output current up to 200 mA Ultra-low quiescent current: – 300 nA typ. at no load – 100 μA typ. at 200 mA load Controlled Iq in dropout conditions • • • • • • • • Very low-dropout voltage: 160 mV at 200 mA Output voltage accuracy: 2% at room temperature, 3% in full temperature range Output voltage versions: from 0.8 V to 4.5 V, with 50 mV step and adjustable Logic-controlled electronic shutdown Output discharge feature (optional) Internal overcurrent and thermal protections Temperature range: from -40 °C to +125 °C Packages: DFN6-2x2, SOT323-5L, Flip-Chip4 Applications Maturity status link STLQ020 • • • • • Smartphones/tablets Image sensors Wearable accessories Healthcare devices Metering Description The STLQ020 is a 200 mA low-dropout voltage regulator, able to work with an input voltage ranging from 2 V to 5.5 V. The typical dropout voltage at maximum load is 160 mV. The ultra-low quiescent current, which is just 0.3 μA at no load, extends battery-life of applications requiring very long standby time. Even though the device intrinsic consumption is ultra-low, STLQ020 is able to provide fast transient response and good PSRR performance, thanks to its adaptive biasing circuit. Enable pin puts the STLQ020 in shutdown mode, reducing total current consumption to 5 nA. The STLQ020 is designed to keep the quiescent current under control and at a low value also during dropout operation, helping to extend even more the operating time of battery- powered devices. It also includes short-circuit constant-current limiting and thermal protection. Several small package options are available. DS12072 - Rev 4 - October 2021 For further information contact your local STMicroelectronics sales office. www.st.com STLQ020 Block diagram 1 Block diagram Figure 1. Block diagram (fixed version) Figure 2. Block diagram (adjustable version) VIN VOUT Bias generator OPAMP EN Enable Thermal protection ADJ Bandgap reference * GND Note: DS12072 - Rev 4 (*) output discharge function is optional. page 2/31 STLQ020 Pin configuration 2 Pin configuration Figure 3. Pin configuration Table 1. Pin description DS12072 - Rev 4 Symbol SOT323-5L DFN6-2x2 Flip-Chip4 Description VIN 1 6 A1 LDO supply voltage VOUT 5 1 A2 LDO output voltage GND 2 3 B2 Ground EN 3 4 B1 Enable input: set VEN = high to turn on the device; VEN = low to turn off the device. Not internally pulled-up, don’t leave floating. NC/ADJ 4 2 - Adjustable pin (only on ADJ version). Connect to external resistor divider. Not connected on the fixed version NC - 5 - Not internally connected: it can be connected to GND Exposed pad - Exposed pad - Must be connected to GND page 3/31 STLQ020 Typical application diagram 3 Typical application diagram Figure 4. Typical application diagram (fixed version) VIN VI ON EN OFF S TLQ020 C In C Out GND 1µF VOUT VO 1µF AMG270320170900MT Figure 5. Typical application diagram (adjustable version) VIN VI S TLQ020 C In 1µF ON OFF VOUT VO EN R1 C Out ADJ 1µF GND R2 Adjus ta ble ve rs ion AMG270320170901MT Note: DS12072 - Rev 4 R1 and R2 are calculated according to the following formula: R1 = R2 x (VOUT / VADJ - 1). page 4/31 STLQ020 Maximum ratings 4 Maximum ratings Table 2. Absolute maximum ratings Symbol VIN Parameter Value Unit -0.3 to 7 V -0.3 to VIN + 0.3 V -0.3 to 2 V Input supply voltage VOUT Output voltage VADJ Adjustable pin voltage IOUT Output current Internally limited A EN Enable pin voltage -0.3 to VIN + 0.3 V PD Power dissipation Internally limited W ESD Charged device model ±500 Human body model ±2000 V TJ-OP Operating junction temperature -40 to 125 °C TJ-MAX Maximum junction temperature 150 °C -55 to 150 °C TSTG Storage temperature Table 3. Thermal data Symbol DS12072 - Rev 4 Parameter DFN6-2x2 Rthjc Thermal resistance, junction-to-case 15 Rthja Thermal resistance, junction-to-ambient 65 Flip-Chip4 180 SOT323-5L Unit 130 °C/W 250 °C/W page 5/31 STLQ020 Electrical characteristics 5 Electrical characteristics TJ = 25 °C, VIN = VOUT + 0.5 V or 2 V, whichever is greater; VEN = VIN; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA. Table 4. Electrical characteristics (fixed version) Symbol VIN Parameter Test conditions Max. Unit 2 5.5 V TJ = 25 °C -2 2 -40 °C < TJ < 125 °C -3 3 Operating input voltage range VOUT Output voltage accuracy ∆VOUT%/ ∆VIN Static line regulation ∆VOUT%/ ∆IOUT Static load regulation VDROP eN Dropout voltage (2) Output noise voltage Min. VOUT + 0.5 V < VIN < 5.5 V (1) 0.005 -40 °C < TJ < 125 °C 1 mA < IOUT < 0.2 A; TJ = 25 °C -40 °C < TJ < 125 °C 0.005 160 mV VOUT = 2.5 V; IOUT = 20 mA 15 mV f = 10 Hz to 100 kHz 135 µVRMS/ VOUT 52 VOUT = 2.5 V; VRIPPLE = 0.2 Vpp 45 IOUT = 0 A 300 IOUT = 0 A; -40 °C < TJ < 125 °C 1000 IOUT = 0.2 A 100 IOUT = 0.2 A; -40 °C < TJ < 125 °C ISC RLOW (3) VEN IEN TSHDN dB 35 IOUT = 10 mA ; f = 1 kHz IOUT = 10 mA; f = 10 kHz Quiescent current %/mA VOUT = 2.5 V; IOUT = 0.2 A VOUT = 2.5 V; VRIPPLE = 0.2 Vpp Iq %/V 0.0015 IOUT = 10 mA; f = 100 Hz Supply voltage rejection % 0.05 VOUT = 2.5 V; VRIPPLE = 0.2 Vpp SVR Typ. 150 nA µA Shutdown current VEN = 0 V, VIN = VOUT + 0.5 V (1) Short-circuit current VOUT = 0 V 380 mA Output discharge resistance VEN = 0 V 100 Ω Enable input logic low Enable input logic high -40 °C < TJ < 125 °C Enable pin input current VEN = VIN; 1.25 < VIN < 6.0 V Thermal shutdown (4) IOUT > 1 mA Hysteresis 0.005 0.05 0.4 1.2 1 160 20 µA V nA °C 1. VIN = VOUT + 0.5 V or 2 V, whichever is greater. 2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. 3. On specific version only. 4. The thermal protection is not active when the load current is lower than 1 mA. DS12072 - Rev 4 page 6/31 STLQ020 Electrical characteristics TJ = 25 °C, VIN = 2 V, VEN = VIN; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA. Table 5. Electrical characteristics (adjustable version) Symbol VIN Parameter Test conditions Operating input voltage range VADJ Reference voltage accuracy IADJ Adjustable pin current ∆VADJ%/∆VIN Static line regulation ∆VADJ%/∆IOUT Static load regulation VDROP eN Dropout voltage (1) Output noise voltage SVR Supply voltage rejection Min. Typ. 2 TJ = 25 °C -40 °C < TJ < 125 °C 0.784 0.8 -3 Quiescent current 2 V< VIN < 5.5 V RLOW (2) VEN IEN TSHDN 5.5 V 0.816 V 3 % nA 0.005 -40 °C < TJ < 125 °C 0.05 1 mA < IOUT < 0.2 A; TJ = 25 °C 0.0015 -40 °C < TJ < 125 °C 0.005 %/V %/mA VOUT = 2.0 V; IOUT = 0.2 A 200 mV VOUT = 2.0 V; IOUT = 20 mA 20 mV f = 10 Hz to 100 kHz 135 µVRMS/ VOUT VOUT = 2.5 V; VRIPPLE = 0.2 Vpp IOUT = 10 mA; f = 100 Hz 60 VOUT = 2.5 V; VRIPPLE = 0.2 Vpp IOUT = 10 mA ; f = 1 kHz 40 VOUT = 2.5 V; VRIPPLE = 0.2 Vpp IOUT = 10 mA; f = 10 kHz 60 IOUT = 0 A 300 dB 1000 IOUT = 0.2 A nA 80 IOUT = 0.2 A; -40 °C < TJ < 125 °C ISC Unit 1 IOUT = 0 A; -40 °C < TJ < 125 °C Iq Max. 150 µA Shutdown current VEN = 0 V, VIN = 2 V Short-circuit current VOUT = 0 V 380 mA Output discharge resistance VEN = 0 V 100 Ω Enable input logic low Enable input logic high -40 °C < TJ < 125 °C Enable pin input current VEN = VIN; 1.25 < VIN < 5.5 V Thermal shutdown (3) IOUT > 1 mA Hysteresis 0.005 0.05 0.4 1.2 1 160 20 µA V nA °C 1. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. 2. On specific version only. 3. The thermal protection is not active when the load current is lower than 1 mA. DS12072 - Rev 4 page 7/31 STLQ020 Typical characteristics 6 Typical characteristics The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 °C. Figure 7. Output voltage vs. temperature Figure 6. Output voltage vs. temperature I OUT = 1 mA V IN = 2 V, V OUT = VADJ, 0.820 0.815 0.815 0.810 0.810 0.805 0.805 VOUT [V] VOUT [V] V IN = 2 V, V OUT = VADJ, 0.820 0.800 0.800 0.795 0.795 0.790 0.790 0.785 0.785 0.780 -60 -40 -20 0 20 40 60 80 100 120 0.780 140 -60 -40 -20 0 Temperature [ºC] 1.840 1.840 1.830 1.830 1.820 1.820 1.810 1.810 1.800 1.790 1.780 1.770 1.760 1.760 1.750 40 60 Temperature [ºC] DS12072 - Rev 4 100 120 140 1.790 1.770 20 80 1.800 1.780 0 60 V IN = 2.3 V, VOUT = 1.8 V, I OUT = 200 mA 1.850 VOUT [V] VOUT [V] V IN = 2.3 V, VOUT = 1.8 V, I OUT = 1 mA -20 40 Figure 9. Output voltage vs. temperature 1.850 -40 20 Temperature [ºC] Figure 8. Output voltage vs. temperature -60 I OUT = 200 mA 80 100 120 140 1.750 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [ºC] page 8/31 STLQ020 Typical characteristics Figure 10. Line regulation vs. temperature Figure 11. Load regulation vs. temperature VIN = 2.3 V to 5.5 V, VOUT = VADJ, IOUT = 1 mA VIN = 2.3 V , VOUT = 1.8 V, IOUT = 1 mA to 200 mA 0.005 0.040 0.004 0.030 0.003 Line regulation [%/mA] 0.050 Line regulation [%/V] 0.020 0.010 0.000 -0.010 -0.020 0.002 0.001 0.000 -0.001 -0.002 -0.030 -0.003 -0.040 -0.004 -0.005 -60 -0.050 -60 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 Temperature [ºC] Temperature [ºC] Figure 12. Short-circuit current vs. temp. Figure 13. Quiescent current vs. temperature VIN = 2 V, V OUT = GND VIN = 2 V, VOUT = VADJ , IOUT = 0 mA 700 1000 900 600 800 700 Iq [nA] ISHORT [mA] 500 400 600 500 300 400 200 300 200 100 100 0 -60 -40 -20 0 20 40 60 80 100 120 0 140 -60 -40 -20 0 Temperature [ºC] 20 40 60 80 100 120 140 Temperature [ºC] Figure 14. Quiescent current vs. temperature Figure 15. Shutdown current vs. temperature VIN = 2 V, VOUT = VADJ, IOUT = 200 mA VIN = 5.5 V, EN = GND 160 0.2 0.18 140 0.16 120 Iq-Off [µA] Iq [µA] 0.14 100 80 0.12 0.1 0.08 60 0.06 40 0.04 20 0.02 0 -60 -40 -20 0 20 40 60 Temperature [ºC] DS12072 - Rev 4 80 100 120 140 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [ºC] page 9/31 STLQ020 Typical characteristics Figure 17. Quiescent current vs. load current (magnification) Figure 16. Quiescent current vs. load current VIN = 2 V, VOUT = VADJ, IOUT = 0 to 200 mA VIN = 2 V, VOUT = VADJ, IOUT = 0 to 1 mA 100.0 90.0 11.0 80.0 10.0 70.0 9.0 8.0 Iq [µA] Iq [µA] 60.0 50.0 40.0 7.0 6.0 5.0 30.0 4.0 20.0 3.0 2.0 10.0 1.0 0.0 0 20 40 60 80 100 120 140 160 180 200 0.0 0.000001 IOUT [mA] 0.00001 0.0001 0.001 0.01 0.1 1 IOUT [mA] Figure 18. Quiescent current vs. input voltage Figure 19. Output voltage vs. input voltage VIN = 0 to 5.5 V, VOUT = 2.5 V, I OUT = 0 mA VIN = 0 to 5.5 V, VOUT = 2.5 V, I OUT = 0 mA 4.0 1.8 1.6 3.5 1.4 3.0 2.5 1.0 V OUT (V) Iq [µA] 1.2 0.8 2.0 1.5 0.6 1.0 0.4 0.5 0.2 0.0 0 1 2 3 4 5 0.0 6 0 1 2 3 Input Voltage [V] 4 5 6 VIN [V] Figure 20. Enable pin current vs. temperature Figure 21. Dropout voltage vs. temperature VOUT = 2 V, I OUT = 20 mA VIN = 2 V 100 50 90 80 40 60 VDROP [mV] IEN [nA] 70 50 40 30 20 30 20 10 10 0 -60 -40 -20 0 20 40 60 Temperature [ºC] DS12072 - Rev 4 80 100 120 140 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [ºC] page 10/31 STLQ020 Typical characteristics Figure 22. Dropout voltage vs. temperature Figure 23. Enable threshold vs. temperature VOUT = 2 V, I OUT = 200 mA 1200 500 1100 VEN-ON VEN-OFF 400 1000 VEN [mV] VDROP [mV] 900 300 800 700 200 600 100 500 400 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [ºC] Temperature [ºC] Figure 25. Line transient (trise = 5 µs) Figure 24. PSRR vs. frequency IOUT = 10 mA 100 90 Vout=0.8V Vout=1.8V 80 PSRR [dB] 70 60 50 40 30 20 10 0 10 100 1000 10000 100000 f [Hz] Figure 26. Line transient (trise = 1 µs) DS12072 - Rev 4 Figure 27. Line transient page 11/31 STLQ020 Typical characteristics Figure 28. Load transient Figure 29. Load transient (trise = 5 µs) Figure 30. Load transient (VOUT = 1.8 V) Figure 31. Load transient (VOUT = VADJ) Figure 32. Startup transient Figure 33. Startup transient (trise = 10 µs) DS12072 - Rev 4 page 12/31 STLQ020 Application information 7 Application information 7.1 External capacitors The STLQ020 voltage regulator requires external low ESR capacitors to assure the control loop stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance defined in the following chapters. Input and output capacitors should be located as close as possible to the relevant pins. Input capacitor An input capacitor, with a minimum value of 1 μF, must be located as close as possible to the input pin of the device and returned to a clean analog ground. A good quality, low-ESR ceramic capacitor is suggested. It helps to ensure stability of the control loop, reduces the effects of inductive sources and improves ripple rejection. Capacitance higher than 1 µF can be chosen in case of fast load transients in application. Output capacitor STLQ020 requires a low-ESR capacitor connected on its output, to keep the control loop stable and reduce the risk of ringing and oscillations. The control loop is designed to be stable with any good quality ceramic capacitor (such as X5R/X7R types) with a minimum value of 1 µF and equivalent series resistance in the [3 – 500 mΩ] range. It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR variations must be taken into account in the design phase to ensure the device works in the expected stability region. There is no maximum limit to the output capacitance, provided that the above conditions are respected. 7.2 Output voltage adjustment (adjustable version) In the adjustable version, available on the DFN6-2x2 and SOT323-5L packages, the output voltage can be adjusted to any voltage, starting from 0.8 V (VADJ) up to the input voltage minus the voltage drop (VDROP) across the internal power pass element, by connecting a resistor divider between the ADJ pin and the output, allowing the remote voltage sensing. The resistor divider should be selected using the following equation: Equation 1 VOUT = VADJ (1 + R1 / R2) with VADJ = 0.8 V (typ.) and VOUT < VIN-VDROP(MAX) For best accuracy and stability the resistor divider should be designed in order to allow that a current of at least 500 nA flows across it. The current flowing into the ADJ pin is typically less than 1 nA, therefore causing negligible change in final the output voltage. 7.3 Enable pin operation This is a logic control pin, CMOS level-compatible, which can be used to turn On/Off the regulator.It is active high, so when it is pulled down, the device enters the shutdown mode, drastically reducing the current consumption, to less just few nA. Since it is not internally pulled-up, when the enable feature is not used, this pin must not be left floating. It can be tied to VIN to keep the regulator output in ON state all the time. To assure reliable operation, the signal source used to drive the EN pin, must be able to swing above and below the specified thresholds listed in the electrical characteristics table (VEN). 7.4 Power dissipation A proper PCB design is recommended, to ensure that the device internal junction temperature is kept below 125°C, in all the operating condition. Depending on the package option, the thermal energy generated by the device flows from the die surface to the PCB copper area through the package leads, solder bumps and/or exposed pad. DS12072 - Rev 4 page 13/31 STLQ020 Protection features The PCB copper area acts as a heat sink. The footprint copper pads should be as wider as possible to spread and dissipate the heat to the surrounding environment. Thermal vias to the inner or backside copper layers improve the overall thermal performance of the device. The power dissipation of the LDO depends on the input voltage, output voltage and output current, and is given by: Equation 2 PD = (VIN -VOUT) IOUT The junction temperature of the device is: Equation 3 TJ_MAX = TA + RthJA x PD where: TJ_MAX is the maximum junction of the die, 125 °C; TA is the ambient temperature; RthJA is the thermal resistance junction-to-ambient. With the above equation it is possible to calculate the maximum allowable power dissipation, therefore the maximum load current for a certain voltage drop. Appropriate de-rating of the operating condition can be applied accordingly. 7.5 Protection features Current limit The STLQ020 embeds a constant-current limit circuit, which acts in case of overload or short-circuit on the output, clamping the load current to a safe value (typ. 380 mA). Normal operation is restored if the overload disappears, but prolonged operation in current limit may lead to high power dissipation inside the LDO and subsequently to thermal shutdown. Thermal protection An internal thermal feedback loop disables the output voltage if the die temperature reaches approximately 160 °C. This feature protects the device from excessive temperature that could lead to permanent damage to the LDO. Once the thermal protection is triggered and the device is shut down, normal operation is automatically recovered if the die temperature falls below 140 °C (thermal protection hysteresis of 20 °C typically) Important note: to keep the device power consumption below 500 nA in low load/no load condition, the internal thermal protection is kept disabled for load current below 1 mA. Current and thermal limit protections are designed to protect the LDO from excessive power dissipation and not intended to replace a proper thermal and electrical design of the application. Continuous operation above the maximum ratings may lead to permanent damage to the device. DS12072 - Rev 4 page 14/31 STLQ020 Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 8.1 SOT323-5L package information Figure 34. SOT323-5L package outline 7091413_G DS12072 - Rev 4 page 15/31 STLQ020 SOT323-5L package information Table 6. SOT323-5L package mechanical data Dim. mm Min. Typ. Max. A 0.80 1.10 A1 0 0.10 A2 0.80 b 0.15 0.30 c 0.10 0.22 D 1.80 2 2.20 E 1.80 2.10 2.40 E1 1.15 1.25 1.35 0.90 e 0.65 e1 1.30 L 0.26 < 0° 0.36 1 0.46 8° Figure 35. SOT323-5L recommended footprint DS12072 - Rev 4 page 16/31 STLQ020 SOT323-5L package information 8.1.1 SOT323-5L tape and reel information Figure 36. SOT323-5L tape outline DS12072 - Rev 4 page 17/31 STLQ020 SOT323-5L package information Figure 37. SOT323-5L reel outline DS12072 - Rev 4 page 18/31 STLQ020 Flip-Chip4 package information 8.2 Flip-Chip4 package information Figure 38. Flip-Chip4 package outline Table 7. Flip-Chip4 mechanical data Dim. mm Min. Typ. Max. A 0.51 0.56 0.61 A1 0.17 0.20 0.23 A2 0.34 0.36 0.38 b 0.23 0.26 0.29 D 0.743 0.773 0.803 D1 E DS12072 - Rev 4 0.40 0.743 0.773 E1 0.40 SD 0.20 SE 0.20 f 0.187 ccc 0.075 0.803 page 19/31 STLQ020 Flip-Chip4 package information Figure 39. Flip-Chip4 recommended footprint DS12072 - Rev 4 page 20/31 STLQ020 Flip-Chip4 package information 8.2.1 Flip-Chip4 reel information Figure 40. Flip-Chip4 reel outline DS12072 - Rev 4 page 21/31 STLQ020 Flip-Chip4 package information Figure 41. Flip-Chip4 tape outline DS12072 - Rev 4 page 22/31 STLQ020 DFN6 2x2 package information 8.3 DFN6 2x2 package information Figure 42. DFN6 2x2 package outline Bottom view Side view Top view DM00205706 DS12072 - Rev 4 page 23/31 STLQ020 DFN6 2x2 package information Table 8. DFN6 2x2 package mechanical data Dim. mm Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 0.02 0.05 A3 0.10 0.20 0.30 b 0.18 0.23 0.28 D 1.90 2.00 2.10 D2 1.33 1.43 1.53 E2 0.68 0.78 0.88 e 0.50 E 1.90 2.00 2.10 L 0.25 0.35 0.45 N 6 Figure 43. DFN6 2x2 recommended footprint DS12072 - Rev 4 page 24/31 STLQ020 DFN6 2x2 package information 8.3.1 DFN6 2x2 tape information Figure 44. DFN6 2x2 tape outline DS12072 - Rev 4 page 25/31 STLQ020 Ordering information 9 Ordering information Table 9. Order codes Order code Package Output voltage Marking Packing STLQ020C18R SOT323-5L 1.8 V QLJ Tape and reel STLQ020C22R SOT323-5L 2.2 V QLS Tape and reel STLQ020C28R SOT323-5L 2.8 V QM3 Tape and reel STLQ020C33R SOT323-5L 3.3 V QMB Tape and reel STLQ020J18R Flip-Chip 4 1.8 V LJ Tape and reel STLQ020J25R Flip-Chip 4 2.5 V LX Tape and reel STLQ020J30R Flip-Chip 4 3.0 V M7 Tape and reel STLQ020J33R Flip-Chip 4 3.3 V MB Tape and reel STLQ020PU19R DFN6-2x2 1.9 V QLL Tape and reel STLQ020PU28R DFN6-2x2 2.8 V QM3 Tape and reel STLQ020PU33R DFN6-2x2 3.3 V QMB Tape and reel STLQ020PUR DFN6-2x2 ADJ QAD Tape and reel Figure 45. Marking composition (flip-chip) A1 xy DS12072 - Rev 4 page 26/31 STLQ020 Revision history Table 10. Document revision history Date Revision Changes 27-Mar-2017 1 Initial release. 05-Dec-2017 2 Added: Section 6 Typical characteristics and Section 7 Application information. 07-Jun-2019 3 Section 8.1.1 SOT323-5L tape and reel information, Section 8.2.1 Flip-Chip4 reel information and Section 8.3.1 DFN6 2x2 tape information 27-Oct-2021 4 Added new order codes Table 9. Order codes Added: order codes Table 9. Order codes and reel information DS12072 - Rev 4 page 27/31 STLQ020 Contents Contents 1 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 8 7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Output voltage adjustment (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 Enable pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 8.1 SOT323-5L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 8.2 Flip-Chip4 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.1 8.3 Flip-Chip4 reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DFN6 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3.1 9 SOT323-5L tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DFN6 2x2 reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DS12072 - Rev 4 page 28/31 STLQ020 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Pin description. . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics (fixed version). . . . . Electrical characteristics (adjustable version) . SOT323-5L package mechanical data . . . . . Flip-Chip4 mechanical data . . . . . . . . . . . . . DFN6 2x2 package mechanical data . . . . . . Order codes . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . DS12072 - Rev 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 5 . 5 . 6 . 7 16 19 24 26 27 page 29/31 STLQ020 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. DS12072 - Rev 4 Block diagram (fixed version) . . . . . . . . . . . . . . . Block diagram (adjustable version) . . . . . . . . . . . Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . Typical application diagram (fixed version) . . . . . . Typical application diagram (adjustable version) . . Output voltage vs. temperature . . . . . . . . . . . . . . Output voltage vs. temperature . . . . . . . . . . . . . . Output voltage vs. temperature . . . . . . . . . . . . . . Output voltage vs. temperature . . . . . . . . . . . . . . Line regulation vs. temperature. . . . . . . . . . . . . . Load regulation vs. temperature . . . . . . . . . . . . . Short-circuit current vs. temp. . . . . . . . . . . . . . . . Quiescent current vs. temperature. . . . . . . . . . . . Quiescent current vs. temperature. . . . . . . . . . . . Shutdown current vs. temperature. . . . . . . . . . . . Quiescent current vs. load current . . . . . . . . . . . . Quiescent current vs. load current (magnification) . Quiescent current vs. input voltage . . . . . . . . . . . Output voltage vs. input voltage . . . . . . . . . . . . . Enable pin current vs. temperature . . . . . . . . . . . Dropout voltage vs. temperature . . . . . . . . . . . . . Dropout voltage vs. temperature . . . . . . . . . . . . . Enable threshold vs. temperature . . . . . . . . . . . . PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . Line transient (trise = 5 µs) . . . . . . . . . . . . . . . . . Line transient (trise = 1 µs) . . . . . . . . . . . . . . . . . Line transient . . . . . . . . . . . . . . . . . . . . . . . . . . Load transient . . . . . . . . . . . . . . . . . . . . . . . . . Load transient (trise = 5 µs). . . . . . . . . . . . . . . . . Load transient (VOUT = 1.8 V) . . . . . . . . . . . . . . . Load transient (VOUT = VADJ) . . . . . . . . . . . . . . . Startup transient . . . . . . . . . . . . . . . . . . . . . . . . Startup transient (trise = 10 µs) . . . . . . . . . . . . . . SOT323-5L package outline . . . . . . . . . . . . . . . . SOT323-5L recommended footprint. . . . . . . . . . . SOT323-5L tape outline. . . . . . . . . . . . . . . . . . . SOT323-5L reel outline . . . . . . . . . . . . . . . . . . . Flip-Chip4 package outline . . . . . . . . . . . . . . . . . Flip-Chip4 recommended footprint . . . . . . . . . . . Flip-Chip4 reel outline . . . . . . . . . . . . . . . . . . . . Flip-Chip4 tape outline. . . . . . . . . . . . . . . . . . . . DFN6 2x2 package outline . . . . . . . . . . . . . . . . . DFN6 2x2 recommended footprint. . . . . . . . . . . . DFN6 2x2 tape outline . . . . . . . . . . . . . . . . . . . . Marking composition (flip-chip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 2 . 3 . 4 . 4 . 8 . 8 . 8 . 8 . 9 . 9 . 9 . 9 . 9 . 9 10 10 10 10 10 10 11 11 11 11 11 11 12 12 12 12 12 12 15 16 17 18 19 20 21 22 23 24 25 26 page 30/31 STLQ020 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12072 - Rev 4 page 31/31