TDA7801
Digital input quad power amplifier with built-in diagnostics features
Datasheet - production data
Two I2C bus addresses and 8-ch TDM mode
(only in PowerSO package)
Optional non I2C bus mode
Offset detector (play or mute mode)
'!0'03
PowerSO36
(slug-up)
Clipping detector (selectable level) and
diagnostics pin
'!0'03
Flexiwatt27
(horizontal)
CMOS compatible enable pin (3.3/5 V)
Full fault protection
Four independent short circuit protections
'!0'03
Linear thermal protection (four thermal
warnings)
'!0'03
Flexiwatt27
(vertical)
Flexiwatt27
(SMD)
ESD protection
Features
Description
Integrated 110 dB D/A conversion
The TDA7801 is a new BCD technology quad
bridge amplifier for car audio applications.
I2S digital input (3.3/1.8 V) with TDM option
Selectable input sampling frequency:
44.1 kHz, 48 kHz, 96 kHz, 192 kHz
Thanks to the BCD6 technology it is possible to
integrate a high performance D/A converter
together with powerful MOSFET outputs.
MOSFET power outputs
High output power capability 4x28 W/ 4 @
14.4 V, 1 kHz, 10 % THD
Max. output power 4x72 W/2
Full I2C bus driving (3.3/5 V):
– Independent front/rear soft play/ mute
– Selectable gain (four levels) for very low
noise line-out function
– I2C bus digital diagnostics (including DC
and AC load detection)
The possibility of having the D/A conversion on
board allows the performance to reach an
outstanding 115 dB S/N ratio with more than
105 dB of dynamic range.
This device is equipped with a full diagnostics
array that communicates the status of each
speaker through the I2C bus. The possibility to
control the configuration and behavior of the
device by means of the I2C bus makes TDA7801 a
very flexible machine.
Table 1. Device summary
Order code
Package
Packing
TDA7801PD
PowerSO36 (slug-up)
Tube
TDA7801PDTR
PowerSO36 (slug-up)
Tape and reel
TDA7801
Flexiwatt27 (vertical)
Tube
TDA7801H
Flexiwatt27 (horizontal)
Tube
TDA7801SM
Flexiwatt27 (SMD)
Tube
September 2013
This is information on a product in full production.
DocID022674 Rev 4
1/48
www.st.com
1
Contents
TDA7801
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
2
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
3
4
5
6
2/48
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Electrical characteristics typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Tristate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
Amplifier mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
"PLL-filter /enable" pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2
Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
Voltage supplies timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2
Turn-on diagnostic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3
Permanent diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4
AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5
Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6
Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7
Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.8
I2C programming/reading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.9
Legacy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DocID022674 Rev 4
TDA7801
Contents
6.11
6.12
7
8
9
Under-voltage threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11.1
Supply voltage auto-mute threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11.2
Digital mute disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11.3
Power-on reset threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fast mute features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2S bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1
Interface timings requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2
Group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1
Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2
Reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.5
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.6
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1
IB0-Addr:"00000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2
IB1-Addr:"00001" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3
IB2-Addr:"00010" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4
IB3-Addr:"00011" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.5
IB4-Addr:"00100" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.6
DB0-Addr:"10000" - Channel 1 (left front) . . . . . . . . . . . . . . . . . . . . . . . . 39
9.7
DB1-Addr:"10001" - Channel 2 (left rear) . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8
DB2-Addr:"10010"" - Channel 3 (right front) . . . . . . . . . . . . . . . . . . . . . . 41
9.9
DB3-Addr:"10011" - Channel 4 (right rear) . . . . . . . . . . . . . . . . . . . . . . . . 42
9.10
DB4-Addr:"10100" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DocID022674 Rev 4
3/48
List of tables
TDA7801
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/48
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Flexiwatt27 (vertical/SMD/horizontal) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PowerSO36 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start-up diagnostic pulse typical timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multiple faults priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System clock frequencies for common audio sampling frequencies . . . . . . . . . . . . . . . . . 32
Example timing for tck = 1/fSCK, where fSCK is stated in the Table 9 . . . . . . . . . . . . . . . . . 33
IB0-Addr:"00000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
IB1-Addr:"00001" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
IB3-Addr:"00010" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IB3-Addr:"00011" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
IB4-Addr:"00100" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DB0-Addr:"10000" - Channel 1 (left front). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DB1-Addr:"10001" - Channel 2 (left rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DB2-Addr:"10010"" - Channel 3 (right front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DB3-Addr:"10011" - Channel 4 (right rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DB4-Addr:"10100". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DocID022674 Rev 4
TDA7801
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Block diagram (Flexiwatt27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I2C bus mode application diagram (TDA7801/H/SM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C bus mode application diagram (TDA7801PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Legacy mode application diagram (TDA7801/H/SM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Legacy mode application diagram (TDA7801PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output power vs. supply voltage (4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output power vs. supply voltage (2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Distortion vs. output power (4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Distortion vs. output power (2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. frequency (4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. frequency (2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Vo vs. Vin (Gv1-2-3-4 settings). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Vo vs. Vin (Gv1-2-3-4 settings + 6 dB dig. gain). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. output voltage (LD-Gv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. output voltage (LD-Gv3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Distortion vs. output voltage (LD-Gv4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output attenuation vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Total power dissipation & efficiency vs. Po (4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power dissipation vs. average Po (audio program simulation, 4 ) . . . . . . . . . . . . . . . . . . 20
Power dissipation vs. average Po (audio program simulation, 2 ) . . . . . . . . . . . . . . . . . . 20
ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 20
Standby driving circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-on diagnostic cycle. Positive and negative output behaviour . . . . . . . . . . . . . . . . . . . 23
Turn-on diag. cycle with transition in amp. mode. Positive and negative output behaviour 24
Short to GND and short to Vs, threshold description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Short across the speaker and open load threshold description, in amplifier mode. . . . . . . 25
Short across the speaker and open load threshold description, in line driver mode. . . . . . 25
Thermal muting diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Low voltage mute attenuation, supply voltage variation (Vs); result digital attenuation (At) 29
TDM setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I2S format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Audio data input format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Audio interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
I2C bus protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PowerSO36 (slug-up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 43
Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 44
Flexiwatt27 (horizontal) mechanical data and package dimensions. . . . . . . . . . . . . . . . . . 45
Flexiwatt27 (SMD) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . 46
DocID022674 Rev 4
5/48
Block diagram and pins description
TDA7801
1
Block diagram and pins description
1.1
Block diagram
Figure 1. Block diagram (Flexiwatt27)
)#
0,,FIL%.!",%
$IAGN
3#+
3$?
3$?
)3
INTERFACE
3CRAMBLER
ARRAY
#URRENT
GENERATORS
3SCRAMBLER
ARRAY
#URRENT
GENERATORS
3CRAMBLER
#URRENT
GENERATORS
3CRAMBLER
$6 $GND
6/48
/54,&
4RANSRESISTANCE
0OWER&ILTER
/54,&
&ULLY"ALANCED
/54,2
4RANSRESISTANCE
0OWER&ILTER
/54,2
&ULLY"ALANCED
/542&
&ULLY"ALANCED
4RANSRESISTANCE
0OWER&ILTER
ARRAY
&ULLY"ALANCED
4RANSRESISTANCE
0OWER&ILTER
ARRAY
34
"9
.OISE
SHAPER
#URRENT
GENERATORS
)NTERPOL
6##
)#
0,,
73
#$$)!'
!6
!GND
DocID022674 Rev 4
4!"
07?'.$
/542&
/5422
/5422
'!0'03
TDA7801
2
Application diagrams
Application diagrams
Figure 2. I2C bus mode application diagram (TDA7801/H/SM)
6S
#
&
#
&
6CC
$.
6CC
0,,%.
2K7
2
7
/542&/54
#
P&
#
N&
)#"53
)3).054
$!4!
#,+
73
4$!
4$!(
7'$60
3#+
3$?
/54,&/54
3$?
/5422/54
/54,2/54
4!"
2
#
&
$'.$ !'.$
#
&
6
K7
#$$)!'
'!0'03
Figure 3. I2C bus mode application diagram (TDA7801PD)
6S
#
&
#
&
6CC
6CC
6CC
6CC
$.
0,,%.
2K7
2
7
#
N&
/542&/54
#
P&
/5422/54
)#"53
)3).054
$!4!
#,+
73
3#+
3$?
3$?
4$!0$
/54,&/54
!$$SELECT
!$$
SELECT
/54,2/54
4!"
2
$'.$ !'.$
#
&
#
&
6
K7
#$$)!'
DocID022674 Rev 4
'!0'03
7/48
Application diagrams
TDA7801
Figure 4. Legacy mode application diagram (TDA7801/H/SM)
6S
#
&
#
&
6CC
$.
6CC
0,,%.
2K7
2
7
/542&/54
#
P&
#
N&
/5422/54
2
-54%
4$!
4$!(
4$!3-
K7 #
&
73
3#+
3$?
3$?
%.!",%
)3).054
/54,&/54
/54,2/54
4!"
2
$'.$ !'.$
#
&
#
&
6
K7
#$$)!'
'!0'03
Figure 5. Legacy mode application diagram (TDA7801PD)
6S
#
&
#
&
6CC
6CC
6CC
6CC
$.
0,,%.
2K7
2
7
#
N&
2
%.!",%
73
/542&/54
/5422/54
#
&
#
P&
-54%
K7
4$!0$
)3).054
3#+
3$?
3$?
/54,&/54
/54,2/54
4!"
2
$'.$ !'.$
#
&
#
&
#$$)!'
8/48
DocID022674 Rev 4
6
K7
'!0'03
TDA7801
2.1
Application diagrams
Pin description
Figure 6. Pin connection diagrams
)##LOCK
&LEXIWATT
VERTICAL
)##LOCK
) #$ATA
)#$ATA
07?'.$
07?'.$
/54
22
/54
22
#$$)!'
#$$)!'
/54 22
/54 22
6##
6##
/54
2&
/54
2&
07?'.$
07?'.$
/54 2&
/54 2&
!6
!6
$6
$6
!GND
!GND
$GND
$GND
3$?
3$?
3$?
3$?
3#+
3#+
/54 ,&
/54 ,&
&LEXIWATT
3-$HORIZONTAL
07?'.$
07?'.$
/54
,&
/54
,&
6##
6##
/54 ,2
/54 ,2
73
73
/54
,2
/54
,2
07?'.$
07?'.$
0LL
FILTER%.!",%
0LL
FILTER%.!",%
4!"
4!"
/54
4!"
.#
#$$)!'
.#
/54
07?'.$
6##
/54
07?'.$
!6
6##
$6
/54
!GND
) #$ATA
$GND
3$?
3$?
0OWER3/
SLUG
UP
) ##LOCK
) #!DDRESS
0LLLOOPFILTER%NABLE
3#+
/54
.#
6##
/54
.#
07?'.$
07?'.$
.#
6##
.#
/54
/54
73
'!0'03
DocID022674 Rev 4
9/48
Application diagrams
TDA7801
Table 2. Flexiwatt27 (vertical/SMD/horizontal) pin description
N°
Pin
1
TAB
2
10/48
Function
TAB connection (GND)
Pll-filter / ENABLE Pll loop filter / ENABLE
3
PW_GND
4
OUT 2- / LR-
5
WS
6
OUT 2+ / LR+
7
Vcc
8
OUT 1- / LF-
9
PW_GND
10
OUT 1+ / LF+
11
SCK
12
SD2_4
Serial data channels 2 and 4 (I2S bus, logic input)
13
SD1_3
Serial data channels 1 and 3 (I2S bus, logic input)
14
Dgnd
Digital ground
15
Agnd
Analog ground
16
D3V
Digital 3.3 V supply filter
17
A3V
Analog 3.3 V supply filter
18
OUT3+ / RF+
19
PW_GND
20
OUT3- / RF-
21
Vcc
22
OUT4+ / RR+
Channel 4 (right rear) positive output
23
CD/DIAG
Clip detector and diagnostic output:
– Overcurrent protection intervention
– Thermal warning
– POR
– (Open drain output)
24
OUT4- / RR-
Channel 4 (right rear) negative output
25
PW_GND
2
Power ground channel 2
Channel 2 (Left Rear) negative output
Word select (I2S bus, logic input)
Channel 2 (Left Rear) positive output
Channel 1 and 2 positive supply
Channel 1 (Left Front) negative output
Power ground channel 1
Channel 1 (Left Front) positive output
Serial clock (I2S bus, logic input)
Channel 3 (right front) positive output
Power ground channel 3
Channel 3 (right front) negative output
Channels 3 and 4 positive supply
Power ground channel 4
26
I C Data
I2C data/legacy mode mute
27
I2C Clock
I2C clock/enable legacy mode
DocID022674 Rev 4
TDA7801
Application diagrams
Table 3. PowerSO36 pin description
N°
Pin
1
TAB
Function
TAB connection (GND)
2
CD/DIAG
Clip detector and diagnostic output:
Overcurrent protection intervention
Thermal warning
Offset detection
POR (Open drain output)
3
OUT4-
Channel 4 (right rear) negative output
4
VCC
5
PW_GND
Channels 3-4 positive supply
Power ground channel 4
6
VCC
7
OUT4+
Channels 3-4 positive supply
8
I2C Data
I2C Data / legacy mode mute
9
I2C Clock
I2C Clock / enable legacy mode
10
I2C Address
I2C Address
11
Pll loop
filter/Enable
Pll loop filter / Enable
12
OUT2+
13
VCC
14
NC
15
PW_GND
Channel 4 (right rear) positive output
Channel 2 (left rear) positive output
Channel 1-2 positive supply
Not connected
Power ground channel 2
16
VCC
17
OUT2-
Channel 1-2 positive supply
18
WS
19
OUT1-
20
NC
Not connected
21
NC
Not connected
22
PW_GND
23
OUT1+
24
NC
25
SCK
26
SD2_4
Serial data channels 2 and 4 (I2S bus, logic input)
27
SD1_3
Serial data channels 1 and 3 (I2S bus, logic input)
28
Dgnd
Digital ground
29
Agnd
Analog ground
30
D3V
Digital 3.3 V supply filter
31
A3V
Analog 3.3 V supply filter
Channel 2 (left rear) negative output
Word Select (I2S bus, logic input)
Channel 1 (left front) negative output
Power ground channel 1
Channel 1 (left front) positive output
Not connected
Serial clock (I2S bus, logic input)
32
OUT3+
33
PW_GND
Channel 3 (right front) positive output
34
NC
Not connected
35
NC
Not connected
36
OUT3-
Power ground channel 3
Channel 3 (right front) negative output
DocID022674 Rev 4
11/48
Electrical specifications
TDA7801
3
Electrical specifications
3.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol
Parameter
Value
Unit
Vop
Operating supply voltage
18
V
VS
DC supply voltage
28
V
Vpeak1
Peak supply voltage (for t = 50 ms)
50
V
Vpeak2
Peak supply voltage (for t = 500 ms)
34
V
Vi2cdata
I2C
bus data pin voltage / legacy mode mute
20
V
Vi2ck
I2C bus clock pin voltage / enable legacy mode
50
V
Vi2s
I2S
3.6
V
bus pins voltage
IO
Output peak current (not repetitive t = 100 µs)
8
A
IO
Output peak current (repetitive f > 10 Hz)
6
A
Power dissipation Tcase = 70 °C
85
W
Maximum input sample rate
200
kHz
-40 to 105
°C
-55 to 150
°C
10
nF
Ptot
Fs max
Tamb
Tstg, Tj
Cmax
Operative temperature
range(1)
Storage and junction temperature
Maximum capacitor vs. ground connected to the output
1. A suitable heatsink/dissipation system should be used to keep Tj inside the specific limits.
3.2
Thermal data
Table 5. Thermal data
Symbol
Rth j-case
12/48
Parameter
Thermal resistance junction-to-case
Max
DocID022674 Rev 4
PowerSO36
Flexiwatt 27
Unit
1
1
°C/W
TDA7801
3.3
Electrical specifications
Electrical characteristics
Refer to the test circuit, VS = 14.4 V; RL = 4 ; f = 1 kHz; Tamb = 25 °C; unless otherwise
specified.
Table 6. Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
8
-
18
V
VS
Supply voltage range
-
Id
Total quiescent drain current
in amplifier mode
enable on amplifier mode muted
150
260
350
mA
It
Total quiescent drain current
in tristate mode
enable on tristate mode
30
45
60
mA
RL = 4 ; max power
41
45
-
W
THD = 10 %
25
28
-
W
THD = 1 %
20
22
-
W
RL = 2 ; max power
70
78
-
W
RL = 2 ; THD 10%
43
49
-
W
RL = 2 ; THD 1%
34
38
-
W
PO = 1 W to 10 W, f=1 kHz, GV1
-
0.03
0.05
%
PO = 1 W to 10 W, f=10 kHz, GV1
-
0.2
0.5
%
RL =100 input=-10 dBFS,
f=1 kHz, GV1,2,3,4
-
0.01
0.02
%
60
80
-
dB
14.9
-
16.9
dB (Vp)
9.45
-
11.45 dB (Vp)
6.9
-
8.9
dB (Vp)
1.45
-
3.45
dB (Vp)
12.7
-
-
Vrms
6.65
-
8.35
Vrms
4.9
-
6.2
Vrms
2.65
-
3.35
Vrms
-0.5
-
0.5
dB
105
100
100
98
110
105
105
103
-
dB
PO
THD
Output power
Total harmonic distortion
CT
Cross talk
GV1
Voltage gain 1
GV2
Voltage gain 2
GV3
Voltage gain 3
GV4
Voltage gain 4
FSV1
Full scale voltage GV1
FSV2
Full scale voltage GV2
FSV3
Full scale voltage GV3
FSV4
Full scale voltage GV4
f = 1 kHz to 10 kHz
Output voltage @ -10 dBFS
Output voltage @ 0 dBFS
VS=18 V; RL = 100
Output voltage @ 0 dBFS
DG
Delta voltage gain
20 Hz – 20 kHz
Po =1 W
DR
Dynamic range
GV = GV1
GV = GV2
GV = GV3
GV = GV4
Bw=20 Hz to 20 kHz, un
weighted
DocID022674 Rev 4
13/48
Electrical specifications
TDA7801
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
EIN
Output noise voltage
GV = GV1
GV = GV2
GV = GV3
GV = GV4
Bw =20 Hz to 20 kHz, un
weighted
SNR
Signal to noise ratio
GV = GV1
GV = GV2
GV = GV3
GV = GV4
Bw=20 Hz to 20 kHz, un
weighted
GB
Gain balance
Min.
-
Typ.
Max.
25
25
19
19
35
35
26
26
111
105
105
100
115
109
109
104
-1
Unit
µV
-
dB
-
+1
dB
50
70
-
dB
-
-
10
µA
Supply voltage rejection
f = 1 kHz;
Vr = 1 Vpk;
ISB
Stand-by current
Vpin ENABLE = 0v
AM
Mute attenuation
-
80
-
VOS
Offset voltage
Mute & Play
-50
-
50
mV
Above this voltage the device is
in play
7.8
-
-
V
Below this voltage the device is
in mute
-
-
6.8
V
-
-
4.5
5
V
-
18
24
V
SVR
VAM
VPOWONRESET
Supply automute range
Supply voltage of power-on
reset
VOVERVOLTAGE Over voltage shut-down
dB
CDLK
Clip det high Leakage current CD off
-
0
5
µA
CDSAT
Clip det sat. voltage
CD on; ICD = 1 mA
-
150
300
mV
CD1THD
Clip det THD level 1 %
-
-
1
2
%
CD2THD
Clip det THD level 5 %
-
3
5
7
%
CD3THD
Clip det THD level 10 %
-
7
10
13
%
-
1.45
-
-
5.8
-
-
11.6
-
-
23.2
-
-
34.8
-
-
69.6
-
-
140
-
-
278
-
-
-102
-
Tmute
NGL
14/48
Mute and unmute
commutation time
Noise gating input level
Programmable by
register IB1(6:4)
Fs =44.1 kHz
I2C
bus
Under this level the device is in
mute
DocID022674 Rev 4
ms
dB
TDA7801
Electrical specifications
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
92
-
ms
44.2
42
31.2
21
88
84
63
42
NGT
Noise gating time
Fs = 44100 Hz
-
EIN2
Output noise voltage
GV=GV1
GV=GV2
GV=GV3
GV=GV4
Bw=20 Hz to 20 kHz, un
weighted, noise gating off,
No input signal
-
µV
Turn on diagnostics speaker mode
Pgnd
Short to GND det. (below this
limit, the output is considered in short circuit to GND)
-
-
1
V
Pvs
Short to Vs det. (above this
limit, the output is considered in short circuit to VS)
Vs – 1
-
-
V
Pnop
Normal operation thresholds.
(Within these limits, the
output is considered without
faults).
2
-
Vs – 2
V
Lsc
Shorted load det.
-
-
-
0.5
Lop
Normal load det.
-
1.65
-
25
Lnop
Open load det.
-
75
-
-
Max diagnostic time
Input sampling frequency
Fs = 44100 Hz
-
-
190
ms
Td
Turn on diagnostics booster mode
Pgnd
Short to GND det. (below this
limit, the output is considered in short circuit to GND)
-
-
1
V
Pvs
Short to Vs det. (above this
limit, the output is considered in short circuit to Vs)
Vs – 1
-
-
V
Pnop
Normal operation thresholds.
(Within these limits, the
output is considered without
faults).
2
-
Vs – 2
V
Lsc
Shorted load det.
-
-
-
15
Lop
Normal load det.
-
0.065
-
1
k
Lnop
Open load det.
-
3.5
-
-
k
AC diagnostic current
threshold
IB4 – D6= ‘0’
250
375
500
mA
IB4 – D6= ‘1’
125
187
250
mA
AC-diagnostic
IACTRESH
DocID022674 Rev 4
15/48
Electrical specifications
TDA7801
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
-
-
1
V
Vs – 1
-
-
V
2
-
Vs – 2
V
Speaker mode
-
-
0.5
Booster mode
-
-
15
Speaker mode
1.65
-
-
Booster mode
0.065
-
-
k
1.5
-
2.5
V
Permanent diagnostics
Pgnd
Pvs
Pnop
Short to GND det. (below this
limit, the output is considered in short circuit to GND)
Short to Vs det. (above this
limit, the Output is
considered in short circuit to
Vs)
-
Normal operation thresholds.
(Within these limits, the
output is considered without
faults)
LSC
Shorted load det.
Lop
Normal load det.
VO
Offset detection
Absolute value
Tph
Thermal protection junction
temperature
Gain attenuation of 60 dB
-
175
-
°C
Gain attenuation of 0.5 dB
-
165
-
°C
-
-
Tpl-10
-
°C
-
-
Tpl-27
-
°C
-
-
Tpl-45
-
°C
-
-
Tpl-62
-
°C
Gain Attenuation of 80 dB
-
-
1.2
V
Gain Attenuation of 0.1 dB
2.6
-
-
V
Vs-2
-
Vs
V
Tpl
Tw1
Tw2
Tw3
Thermal warning junction
temperature
Tw4
Legacy mode
VLM_MUTE
VLM_ON
ILKG_MUTE
Legacy mode mute threshold
Legacy mode threshold
Device in legacy mode
Mute pin leakage
-
-5
-
+5
µA
I2C Bus interface
fSCL
Clock frequency
-
-
-
400
kHz
VIL
Input low voltage
-
-
-
1.5
V
VIH
Input high voltage
-
2.3
-
-
V
Pll-filter /ENABLE pin
VILENB
Input low voltage
-
-
-
1.5
V
VIHENB
Input high voltage
-
2.3
-
-
V
IILENB(1)
Logic ‘0’ output current
VIN = 0.45 V
-
-
2
mA
Logic ‘1’ input current
VIN = 2.3 V (IB0 D4=0)
-
-
2
µA
IIHENB
16/48
DocID022674 Rev 4
TDA7801
Electrical specifications
Table 6. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
I2S pin
VIL-I2S
Input low voltage
-
-
-
0.8
V
VIH-I2S
Input high voltage
-
1.3
-
-
V
IIH
Input high current except WS
VI = 3.3 V
pin
-
-
5
µA
IIL
Input low current
VI = 0 V
-
-
5
µA
Input high current for WS
VI = 3.3 V
-
70
150
µA
IIH_WS
1. This has to be considered the maximum current value for a short time and not the standby current.
3.4
Electrical characteristics typical curves
Figure 7. Quiescent current vs. supply voltage Figure 8. Output power vs. supply voltage (4 )
,G P$
9L
5/ c
9V 9
5/ 7
I N+]
3R :
7+'
7+'
9V 9
'!0'03
Figure 10. Distortion vs. output power (4 )
5/ 7
I N+]
3RPD[
'!0'03
Figure 9. Output power vs. supply voltage (2
)
3R :
7+'
9V 9
5/ 7
3RPD[
7+'
I N+]
7+'
I N+]
9V 9
'!0'03
DocID022674 Rev 4
3R :
'!0'03
17/48
Electrical specifications
TDA7801
Figure 11. Distortion vs. output power (2 )
7+'
Figure 12. Distortion vs. frequency (4 )
7+'
9V 9
5/ 7
3R :
9V 9
5/ 7
I N+]
I N+]
3R :
I +]
'!0'03
Figure 13. Distortion vs. frequency (2 )
'!0'03
Figure 14. Vo vs. Vin (Gv1-2-3-4 settings)
9R 9UPV
7+'
9V 9
5/ 7
3R :
*Y
9V 9
I N+]
5/ 7 *Y
5/ 7 *Y
*Y
I +]
9R 9UPV
9LQ G%)V
9V 9I N+]
G%GLJJDLQ
5/ 7 *Y
5/ 7 *Y
*Y
'!0'03
7+'
/'PRGH*Y
9V 9
5/ 7
Figure 16. Distortion vs. output voltage
(LD-Gv2)
18/48
*Y
'!0'03
Figure 15. Vo vs. Vin (Gv1-2-3-4 settings + 6 dB
dig. gain)
9LQ G%)V
'!0'03
DocID022674 Rev 4
I N+]
I N+]
9R 9UPV
'!0'03
TDA7801
Electrical specifications
Figure 17. Distortion vs. output voltage
(LD-Gv3)
Figure 18. Distortion vs. output voltage
(LD-Gv4)
7+'
/'PRGH*Y
9V 9
5/ 7
I N+]
I N+]
9R 9UPV
'!0'03
Figure 20. Crosstalk vs. frequency
&52667$/. G%
5/ 7
3R :UHI
9R 9UPV
'!0'03
9R G%
I N+]
Figure 19. Output attenuation vs. Vs
/'PRGH*Y
9V 9
5/ 7
I N+]
7+'
5/ 7
3R :
5J 7
9V 9
695 G%
'!0'03
H
3WRW :
9V 9
5/ [7
I N+]6,1(
I +]
Figure 22. Total power dissipation & efficiency vs. Po
(4 )
9ULSSOH 9UPV
'!0'03
Figure 21. Supply voltage rejection vs.
frequency
H
3WRW
I +]
'!0'03
DocID022674 Rev 4
3R :
'!0'03
19/48
Electrical specifications
TDA7801
Figure 23. Power dissipation vs. average Po
(audio program simulation, 4 )
3WRW :
3WRW :
9V9
5/ [7
6WHUHR3LQN1RLVH
Figure 24. Power dissipation vs. average Po
(audio program simulation, 2 )
9V9
5/ [7
6WHUHR3LQN1RLVH
&/,367$57
&/,367$57
DYJ3R :
'!0'03
Figure 25. ITU R-ARM frequency response,
weighting filter for transient pop
/UTPUTATTENUATIOND"
20/48
(Z
'!0'03
DocID022674 Rev 4
DYJ3R :
'!0'03
TDA7801
4
Operation mode
Operation mode
The device has three main operation modes:
4.1
Standby mode
Tristate mode
Amplifier mode
Standby mode
When the ENABLE pin is low the device is in standby-mode. The current consumption is
ISB.
4.2
Tristate mode
When the ENABLE pin is high and the bit D7 of register DB0 is low the device is in tristatemode. In that state the amplifier outputs are "high impedance", the I2C bus is ready to
receive command.
4.3
Amplifier mode
When the ENABLE pin is high and the bit D7 of register DB0 is high the device is in
amplifier-mode ready to play. To move the device in that state it is enough to write '1' on bit
D7 of register IB1 from tristate-mode. Note that the device starts with all channels muted by
default (see I2C registers description, Section 9).
DocID022674 Rev 4
21/48
"PLL-filter /enable" pin description
TDA7801
5
"PLL-filter /enable" pin description
5.1
Functionality
The pin 2 has the functions to:
ENABLE
PLL filter
When the pin 2 is set to logic level low the TDA7801 is in standby-mode and the current
consumption is ISB. The device is waked-up and put in tristate-mode setting the same pin to
logic level high. In tristate-mode the TDA7801 is ready to receive I2C bus instructions. The
device is set in amplifier-mode writing '1' on bit D7 of byte IB1.
In amplifier-mode the PIN2 works as PLL filter pin. The TDA7801 will place this pin to have
a precise voltage value.
During the transition from amplifier-mode to standby-mode, the device will try to force the
Pin2 level sourcing a current IILENB.
5.2
Driving
In Figure 26 an applicative schematic to drive the Pin 2 is reported. In the schematic, it is
supposed that the TDA7801 is interfaced with a µP.
Figure 26. Standby driving circuit
.
BUFFER
0,,
2 K7 2F 7
0
#F N&
# P&
%NABLE
4$!
'!0'03
The Rf and Cf components are respectively resistance and capacitance of the PLL filter. The
resistance R1 and diode 1N4848 allows the Pin 2 to force to logic level low and the
TDA7801 to force its voltage level in amplifier-mode. During the transition amplifiermode/standby-mode the TDA7801 tries to forces the voltage on the PLL/Enable by sourcing
a current flow. Since the PLL/ENABLE pin is forced at a voltage lower than VILENB in the
above described conditions, the buffer input resistance should be chosen small enough to
take this effect into account.
It’s important to keep the PLL-Filter ground as close as possible to digital ground in the
application board in order to minimize the PLL reference movement.
22/48
DocID022674 Rev 4
TDA7801
Functional description
6
Functional description
6.1
Voltage supplies timing
TDA7801 internal voltage supplies rise time and fall time are determined by the two
capacitors at pin 16 and 17, respectively digital supply pin (D3V3) and analog supply pin
(A3V3). Capacitor on analog supply pin, (pin 17), and capacitor on digital supply, (pin 16),
should respect the ratio 2:1. It is suggested to fix a minimum value of 22 µF on digital supply
pin and 47 µF on analog supply pin, which correspond to a typical Turn-on time of 1.5 ms
and a typical turn-off time of 8.5 ms.
6.2
Turn-on diagnostic description
Turn-on diagnostic is activated under I2C bus request. Detectable output faults are:
Short to GND
Short to Vs
Short across the speaker
Open load
In the TDA7801 a new diagnostic that exploits the presence of D/A converters has been
implemented. To verify if some of the above connections are in place, a subsonic (inaudible)
voltage pulse is digitally and internally generated and converted (Figure 27). The amplitude
of this pulse is stopped when the current flowing through the speaker is the same as the
prefixed one corresponding to a specified load. The exact knowledge of the voltage drop
across the load in any phase of the diagnostic time gives the possibility to know the
connected load.
During the observation time, the measured load is compared with tabled values in order to
determine the result.
The turn-on diagnostic status is internally stored until a successive diagnostic pulse is
requested.
Figure 27. Turn-on diagnostic cycle. Positive and negative output behaviour
/UT /UT
6
6CC
TSEC
4D
!#
'!0'03
A turn-on diagnostic cycle is activated writing '1' on the D7 of byte IB0 only when the
amplifier is in Tristate-mode. Note that the turn-on diagnostic state machine is sensible to
the rise edge of this bit. To run another cycle of turn-on diagnostic it is necessary to:
1.
wait that the previous cycle ends;
2.
clear the D7-IB0 bit.
3.
write '1' on D7-IB0 bit.
DocID022674 Rev 4
23/48
Functional description
TDA7801
It is possible to run the turn-on diagnostic several times by simply resetting the D7-IB0
meanwhile the amplifier is in amplifier mode and writing back '1' on D7-IB0 when the
amplifier is in tristate mode.
Between two diagnostic sequences it is necessary to reset the data register by an I2C
reading instruction. Note that the reading instruction has been placed during the second
diagnostic pulse.
The µP can program the TDA7801 in order to run a cycle of turn-on diagnostic and to move
in amplifier-mode at the end of this cycle (Figure 28)); the I2C bus instructions needed to
program this sequence are:
11011000 -00100000-1XXXXXXX-1XXXXXXX
Note:
The diagnostic enable bit (D7-IB0) has to be set before the amplifier mode bit (D7-IB1)
Figure 28. Turn-on diag. cycle with transition in amp. mode. Positive and negative
output behaviour
/UT /UT
6
6CC
TSEC
T342 T3(
T0,
T34&
T342 T$%,!9
T$
'!0'03
Table 7. Start-up diagnostic pulse typical timing
Value
Symbol
tSTR(1)
tSH
(2)
Parameter
Start-up diagnostic rise
Typ.
Max
0.8
1.5
3
Short to Vcc/Gnd check
tPL(2)
Plateau time
tSTF(1)
Start-up diagnostic fall
tDELAY(2)
Delay time before play
tD
Unit
Min.
Diagnostic pulse
6
ms
5
ms
162
ms
8.5
14
5
182
ms
ms
190
ms
1. These tSTR and tSTF values are relative to capacitors on A3V3 and D3V3 respectively equal to 47 µF and
22 µF. The tSTR and tSTF are proportional to capacitors value.
2. Values relative to fs = 44100Hz.
The information related to the outputs status is read and memorized at the end of the
voltage pulse top. The diagnostic cycle last no more than Td. No audible noise is generated
in the process. As for short to GND / Vs the fault-detection thresholds remain unchanged
independently of the gain setting. They are as in Figure 29.
24/48
DocID022674 Rev 4
TDA7801
Functional description
Figure 29. Short to GND and short to Vs, threshold description
3#TO '.$
6
8
.ORMAL /PERATION
6 6
8
6S
6
3#TO 6S
6S
6
6S
'!0'03
Concerning short across the speaker / open speaker, the threshold varies from speaker
mode to booster mode diagnostic setting, since different loads are expected (either normal
speaker's impedance or high impedance). The speaker or booster mode is selected with bit
D6-IB0 (channel 1 and 3) and bit D5-IB0 (channel 2 and 4). The values in case of speaker
mode gain are as in Figure 30.
Figure 30. Short across the speaker and open load threshold description, in amplifier
mode.
3#ACROSS ,OAD
8
.ORMAL ,OAD
8
/PEN,OAD
INFINITE
'!0'03
If the booster mode is selected, the same thresholds will change as in Figure 31.
Figure 31. Short across the speaker and open load threshold description, in line
driver mode.
3#ACROSS ,OAD
8
.ORMAL ,OAD
8
K
/PEN,OAD
K
INFINITE
'!0'03
When the amplifier is biased and the diagnostic is still enabled the permanent diagnostic
takes place. The previous turn-on state is kept until a short appears at the outputs because
only in this case a new diagnostic cycle can start.
6.3
Permanent diagnostic
Detectable conventional faults are:
Short to GND
Short to Vs
Short across the speaker
The following additional features are provided:
Output offset detection
AC diagnostic
The TDA7801 diagnostic has 2 different cycles:
1.
Restart cycle. It is a 1 ms pulse. During this period a check of the outputs is made.
2.
Plateau cycle. It is a 100 ms pulse. During this period a check of the outputs is
performed and the result of diagnostic analysis is communicated by means of I2C bus.
The TDA7801 has 2 different operating behaviors when a fault occurs:
1.
Restart mode, (D6-IB0='0'). The diagnostic is not enabled. Each audio channel
operates independently of each other. If any of the a.m. faults occurs, only the
DocID022674 Rev 4
25/48
Functional description
TDA7801
channel(s) concerned are shut down. The diagnostic performs restart cycles every
1 ms until a fault condition is present. The amplifier restarts in play only once the
overload is removed.
DIagnostic mode, (D6-IB0='1'). It is enabled via I2C bus and self activates if an output
overload (so as to cause the intervention of the short-circuit protection) occurs to the
speakers outputs. Once activated, the diagnostics procedure develops as below:
–
The diagnostic performs 1 restart cycle in order to avoid momentary re-circulation
spikes which could give erroneous diagnostic results. If normal situation (no
overloads) is detected the channel returns active.
–
Instead, if after 1 restart cycle an overload is detected then the diagnostic circuit
performs a plateau cycle.
–
After the plateau cycle, the fault audio channel generates restart cycles every
1 ms until a fault condition is present. The relevant data acquired during plateau
cycle are stored and can be read by the microprocessor. A new plateau cycle can
be activated by an I2C reading only if the fault condition persists. This is to ensure
continuous diagnostics throughout the car-radio operating time.
The diagnostic performs another plateau cycle after each I2C bus registers read if the
diagnostic bit is activated, (IB0-d7="1"). If I2C read is performed during the diagnostic
permanent plateau cycle then, once the short is removed, the amplifier waits for another I2C
read before starting to play again, in order to communicate the diagnostic plateau cycle
results.
6.4
AC diagnostic
It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more
in general, presence of capacitive (AC) coupled loads. This diagnostic is based on the
notion that the overall speaker's impedance (woofer + parallel tweeter) will tend to increase
towards high frequencies if the tweeter gets disconnected, because the remaining speaker
(woofer) would be out of its operating range (high impedance).
To determine the load impedance, a sinewave tone at a suitable (F > 10 kHz or even
ultrasonic) frequency should be fed to the output pins. Depending on the test's result the AC
diagnostic is able to determine if the tweeter is connected or not. The tweeter is not
connected if for four consecutive sine wave the current threshold on the load is not respassed.
AC diagnostic is managed by I2C commands. The AC diagnostic is enabled by bit D7 of
register IB4, while the bit D6 is used to choose the current level threshold. The result of AC
test are stored in the data register DB4 (bits D7:D4) which are set to logic level '1' if a
tweeter is detected on the correspondent channel.
Note, the results on D7:D4 are valid only if the bit D3 is zero; in order to avoid this condition
the pulse generated has to respect the condition Vout_peak < Vbattery-4V.
6.5
Output DC offset detection
Any DC output offset exceeding ± VO are signalled out. This inconvenient might occur as a
consequence of improper DC input signal. The offset detection is performed at the end of
the digital chain by a low pass digital filter. The offset detection is permanent, and also works
in play mode. The results of the DC offset detection are obtained from the right pin for each
channel (see I2C table in Section 9); the bits are continuously refreshed.
26/48
DocID022674 Rev 4
TDA7801
6.6
Functional description
Multiple faults
Faults can occur simultaneously. If this happens, faults are read out according to a "priority
table" (see Table 8); this guarantees that the most dangerous fault is signalled. This is true
only for the turn-on diagnostic but not in case of permanent diagnostic (only the faults
causing protection intervention are recognized).
Table 8. Multiple faults priority
1.
S. GND
S. Vs
S. Across L.
Open L.
S. GND
S. GND
S. Vs + S. GND
S. GND
S. GND
S. Vs
/
S. Vs
S. Vs
S. Vs
S. Across L.
/
/
S. Across L.
N.A.
Open L.
/
/
/
Open Load (1)
Only in Startup Diagnostic
In permanent diagnostic mode the table is the same, with only a difference concerning open
load, which is not among the recognizable faults. If an open load is present during the
device's normal operation, it should be detected at a subsequent turn-on diagnostic cycle
(i.e. at the successive car radio turn-on).
6.7
Faults availability
All the results coming from I2C bus, by read operations, are the consequence of
measurements inside a defined period of time. If the fault is stable throughout the whole
period, it will be sent out.
The turn-on diagnostic faults are reported on the byte DB 0-3 at the bits D 4-0. The faults
are consistent when the bit D6 of DB0 is '1'. The byte DB 0-3 is reset when read.
During Amplifier-mode, when the bit D4 of byte DB 0-3 is '1' an overload on the
correspondent channel has been detected and a 100 ms permanent diagnostic cycle has
been done. The data on the bits D 4-0 reports the results of this diagnostic cycle. If the bits
are all zero it means that an overload event has been detected, a 100ms cycle has been
performed and the fault has not been detected or removed.
6.8
I2C programming/reading sequence
A correct turn on/off sequence respectful of the diagnostic timings and producing no audible
noises could be as follows (after battery connection):
a)
Turn-on: (Stand-by out + DIag Enable) 200 ms (min.) Muting out
b)
Turn-off: Muting in 10 ms (Diag disable + stand-by in)
c)
Car radio installation: DIag enable (write) 200 ms I2C read (repeat until all
faults disappear).
DocID022674 Rev 4
27/48
Functional description
6.9
TDA7801
Legacy mode
In case of applications without the I2C bus the TDA7801 could be turned on in legacy mode.
In order to put the device in legacy mode it is enough to tie the IC clock pin (PIN 27) at Vcc.
In this mode the device is turned on, as usual, with the ENABLE pin (PIN 2). The I2C Data
pin (PIN26) acts as analog mute. The device is set with all the instruction registers equal to zero.
In legacy mode the I2S interface does not support the TDM format.
6.10
Thermal protection
The TDA7801 has four thermal warnings (Tw1, Tw2, Tw3, Tw4) at different temperatures
which are stored on the I2C bus. Only one of the four thermal warnings could be sent to the
DIAG pin. The selection is done by an I2C bus.
A mute function dependent on temperature is present in order to protect the junction by
over-temperature with limited effects on the sound quality. For junction temperature over the
thermal warning threshold Tpl, the device is gradually carried in mute. The mute level
depends on the temperature: when the junction temperature reaches the Tpl threshold (refer
to Figure 32), the output signal is attenuated of 0.5 dB, while when the junction temperature
reaches Tph the output attenuation is 60 dB. This attenuation is performed without output
signal distortion.
Figure 32. Thermal muting diagram
6OUT
47
47
47
47
40,
40(
40,
40(
4J #
6OUT
28/48
DocID022674 Rev 4
4J #
'!0'03
TDA7801
Functional description
6.11
Under-voltage threshold
6.11.1
Supply voltage auto-mute threshold
The device in play-mode is put in mute when the supply voltage gets lower than the VAM
threshold.
When the supply voltage gets lower than the VAM threshold the device is put in mute. The
muting strategy in this case is reported in Figure 33: once the supply voltage Vs becomes
lower than VAM_HIGH, analog mute and digital mute are activated. The analog mute
attenuation is proportional to the Vs voltage and becomes equal to AM when the Vs gets
lower than VAM_LOW. Note that once the digital mute procedure is started, it cannot be
stopped to move back the device in play, the procedure is going on until the attenuation
level has reached AM. This mechanism avoids that a fast oscillation on Vs cause a similar
oscillation on the output.
Figure 33. Low voltage mute attenuation, supply voltage variation (Vs); result digital
attenuation (At)
6S!TTENUATION!T
6S
6 !-
()'(
6 !-
,/7
!T
TSEC
4-54%
6.11.2
4-54%
'!0'03
Digital mute disabling
The digital mute is disabled in the following conditions:
when TW1 threshold is trespassed (to avoid simultaneous intervention of digital mute
and thermal mute)
when the bit IB3-D5 is set to '1'
during the start-up diagnostic
When the digital mute is disabled, the analog mute is kept active.
6.11.3
Power-on reset threshold
When the ENABLE pin is low or the supply voltage value doesn't guarantee the integrity of
The I2C bus registers (VPOWERONRESET) the TDA7801 is put in tristate-mode and the
registers are set to the initial state. The event is signalled by the low value of DIAG pin and
the '0' value of bit D7 of byte DB0. The DIAG pin is set to high after a POR when the bit D7
of byte IB1 is set to '1' (amplifier mode on) if no other event on DIAG pin is present. The
same I2C bus write operation automatically set to '1' the bit D7 of byte DB0. When the
device is programmed with the D7=1 of IB0 and D7=1 of byte IB1 the device turns-on after a
diagnostic cycle and the DIAG pin stays low for the whole duration of the diagnostic cycle.
DocID022674 Rev 4
29/48
Functional description
6.12
TDA7801
Fast mute features
The TDA7801 is put in mute by a fast-mute procedure by one of the following event:
the ENABLE pin is set to low
the PLL loses the locking
the VS voltage level is under the auto-mute threshold.
30/48
by an I2C programming
DocID022674 Rev 4
I2S bus interface
TDA7801
7
I2S bus interface
The TDA7801 accepts the I2S standard format that could be time division multiplexed
(TDM), however the WS still needs a 50% duty-cycle to work correctly. The Figure 34 shows
the different I2C settings allowed for the I2S interface (2,4 or 8 channels transmission on a
single serial data line (SD) can be selected). By I2C programming it is possible to choose
between the following interface settings:
a)
channel 1 and channel 3 channel on SD1_3 and channel 2 and channel 4 on
SD2_4
b)
all four channels on SD2_4. SD1_3 has not function.
c)
eight channels transferred on the SD2_4 line. This setting is feasible in the
PowerSO36 and Flexiwatt27 package.
Figure 34. TDM setting
3#+
73
#(
#(
#(
#(
#(
#(
3$?
)" hv
3$?
)" hv
#(
3$?
#(
)" hv
3$?
#(
#(
8
8
#(
#(
8
8
8
8
#(
#(
8
8
#(
#(
)" hv
3$?
)" hv
'!0'03
The TDA7801 accepts the I2S standard format with a bit clock (SCK) equal to 64 fs.
Note, TDM setting is guaranteed for a maximum Fs = 96 kHz.
Figure 35. I2S format
F3
,
#HANNEL
2
#HANNEL
"IT
-3"
,3"
"IT
-3"
,3"
DocID022674 Rev 4
'!0'03
31/48
I2S bus interface
7.1
TDA7801
Interface timings requirements
The data interface timings are described below. In the TDA7801 the TDM format as shown
in Figure 34, is an I2S extended: if the four channels option is set then the serial clock is
multiplied by two while it will be multiplied by four when the eight channels option is set. This
means that it is important to keep a duty-cycle of 50% for the Word Select signal and
moreover, all the timings for serial clock and data don't change in every I2S configuration.
Table 9. System clock frequencies for common audio sampling frequencies
Frequency
sampling (fs)
System clock frequency (fSCK), (MHz)
I2S standard
(fs*64)
TDM 4ch (fs*128)
TDM 8ch md1
(fs*256)
TDM 8ch md2
(fs*256)
44.1 (kHz)
2.82
5.64
11.29
11.29
48.0 (kHz)
3.07
6.14
12.29
12.29
96.0 (kHz)
6.14
12.29
24.58
24.58
192.0 (kHz)
12.29
24.58
N.A.
N.A.
Table 9 shows the values of system clock frequencies (serial clock SCK) for common audio
sampling frequencies.
Figure 12 shows the detail of the audio input format as specified by the standard I2S
specification. When more channels are sent the input format does not change and they
follow the sequence as shown in Figure 34.
Figure 36. Audio data input format
3#+
73
-3"
,3"
3$
,3"
-3"
'!0'03
Figure 37. Audio interface timing
43+(
43+,
43+9
4$3
4$(
6() 6
6,/ 6
'!0'03
32/48
DocID022674 Rev 4
I2S bus interface
TDA7801
Table 10. Example timing for tck = 1/fSCK, where fSCK is stated in the Table 9
Parameter
MIN
TYP
MAX
Clock period TSKY
0.9*Tck
Tck
1.1*Tck
Clock HIGH TSKH
0.4*Tck
Measured from
VHI to VHI
Clock LOW TSKL
0.4*Tck
Measured from
VLO to VLO
Setup time SD to fSCK rising edge TDS
0.2*Tck
Hold time SD from fSCK rising edge THD
0.2*Tck
0.8*Tck (1)
40%
60%
fSCK duty-cycle
VHI
Note
1.3
VLO
0.8
1. Measured from VLO to VHI.
7.2
Group delay
The group delay of the amplifier is basically due the FIR filter of the interpolator and it is
given by:
t DELAY = 32
------ , (fs < 48 kHz)
fs
DocID022674 Rev 4
33/48
I2C bus interface
8
TDA7801
I2C bus interface
Data transmission from microprocessor to the TDA7801 and viceversa takes place through
the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be connected).
When I2C bus is active any operating mode of the IC may be modified and the diagnostic
may be controlled and results read back.
The protocol used for the bus is depicted in Figure 38 and comprises:
a start condition (S)
a chip address byte (the LSB bit determines read/write transmission)
a subaddress byte
a sequence of data (N-bytes + acknowledge)
a stop condition (P)
Figure 38. I2C bus protocol description
3
!DDRESS
!
3UBADDRESS
!
$ATA
0
!DDRESS
27
3UBADDRS
8
8
)
35"!
35"!
35"!
35"!
35"!
$ATA
$!4!
$!4!
$!4!
$!4!
$!4!
$!4!
$!4!
$!4!
'!0'03
Description:
S = Start
R/W = '0' => Receive-Mode (Chip could be programmed by µP)
I = Auto increment; when 1, the address is automatically increased for each byte transferred
X: not used
A = Acknowledge
P = Stop
MAX CLOCK SPEED 400kbit/sec
* = available in PowerSO36
34/48
DocID022674 Rev 4
I2C bus interface
TDA7801
8.1
Writing procedure
There are two possible procedures:
8.2
1.
without increment: the I bit is set to 0 and the register is addressed by the subaddress.
Only this register is written by the data following the subaddress byte.
2.
with increment: the I bit is set to 1 and the first register written is the one addressed by
subaddress. Then all the registers starting from the one indicated by this address up to
stop bit (or up to last register) are written.
Reading procedure
There are two possible procedures:
1.
without increment: the I bit is set to 0 and the register is addressed by the subaddress
sent in the previous write procedure. Only this register is read by the data following the
address.
2.
with increment: the I bit is set to 1 and the first register read is the one addressed by
subaddress sent in the previous write procedure. Then all registers starting from the
one indicated by this address up to stop bit (or up to last register) are read.
Note:
the reading procedure reset the register that has been read.
8.3
Data validity
The data on the SDA line must be stable during the high period of the clock. The high and
low state of the data line can only change when the clock signal on the SCL line is low.
8.4
Start and stop conditions
A start condition is a high to low transition of the SDA line while SCL is high.
The stop condition is a low to high transition of the SDA line while SCL is high.
8.5
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
8.6
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse. The receiver** has to pull-down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low using this clock pulse.
* Transmitter
= master (µP) when it writes an address to the TDA7801
= slave (TDA7801) when the µP reads a data byte from TDA7801
** Receiver
= slave (TDA7801) when the µP writes an address to the TDA7801
= master (µP) when it reads a data byte from TDA7801
DocID022674 Rev 4
35/48
I2C registers
TDA7801
9
I2C registers
9.1
IB0-Addr:"00000"
Table 11. IB0-Addr:"00000"
Bit
D7
0: diagnostic defeat
1: diagnostic enable
D6
0: Speaker mode diagnostic ch. 1 and 3 (FRONT)
1: Booster mode diagnostic ch. 1 and 3
D5
0: Speaker mode diagnostic ch. 2 and 4 (REAR)
1: Booster mode diagnostic ch. 2 and 4
D4
D3
D2
D1
D0
9.2
Instruction decoding bit
Gain channel 1 and 3 (FRONT)
D4 D3
00 GV1
01 GV2
10 GV3
11 GV4
Gain channel 2 and 4 (REAR)
D2 D1
00 GV1
01 GV2
10 GV3
11 GV4
0: No increase of digital gain
1: +6dB increase of digital gain
IB1-Addr:"00001"
Table 12. IB1-Addr:"00001"
Bit
D7
D6
D5
D4
D3
36/48
Instruction decoding bit
0: Amplifier mode off - Amplifier not working
1: Amplifier mode on - Amplifier working
Mute Time Setting
D6 D5 D4
mute timing(Fs=44.1kHz)
000
1.45 ms
001
5.8 ms
010
11.6 ms
011
23.2 ms
100
34.8 ms
101
69.6 ms
110
140 ms
111
278 ms
0: Mute channel 1 and 3 (FRONT)
1: Unmute channel 1 and 3
DocID022674 Rev 4
I2C registers
TDA7801
Table 12. IB1-Addr:"00001" (continued)
Bit
D2
D1
D0
Instruction decoding bit
0: Mute channel 2 and 4 (REAR)
1: Unmute channel 2 and 4
Sample Frequency Range(1)
D1 D0
00
44.1/48 kHz
01
44.1/48 kHz
10
96 kHz
11
192 kHz
1. When the amplifier is in Tristate Mode (IB0-D7=0 and IB1-D7=0), any accidental change of Frequency
sample is ignored.
9.3
IB2-Addr:"00010"
Table 13. IB3-Addr:"00010"
Bit
Instruction decoding bit
D7
0: no short fault information on diag. pin
1: short fault information on diag. pin
D6
0: Offset information on diag pin
1: no offset information on diag pin
D5
D4
D3
D2
D1
D0
Temperature warning information on diag. pin
D5 D4 D3
000 Tw1
001 Tw2
010 Tw3
011 Tw4
1xx no thermal warning information on diag. pin
Clip detection level
D2 D1
00 1 %
01 5 %
10 10 %
11 clip detection disabled
0 (no selectable from user)
DocID022674 Rev 4
37/48
I2C registers
9.4
TDA7801
IB3-Addr:"00011"
Table 14. IB3-Addr:"00011"
Bit
9.5
Instruction decoding bit
D7
0: Noise gating on
1: Noise gating off
D6
0 (not used)
D5
0: under-voltage digital mute on
1: under-voltage digital mute off
D4
Tristate channel 3 (right front)
0: ch.3 not in tristate
1: ch.3 in tristate
D3
Tristate channel 1 (left front)
0: ch.1 not in tristate
1: ch.1 in tristate
D2
Tristate channel 4 (right rear)
0: ch.4 not in tristate
1: ch.4 in tristate
D1
Tristate channel 2 (left rear)
0: ch.2 not in tristate
1: ch.2 in tristate
D0
0: Input high pass filter off
1: Input high pass filter on
IB4-Addr:"00100"
Table 15. IB4-Addr:"00100"
Bit
D7
AC diagnostic On (D7='1')
D6
AC diagnostic current threshold
D6 = '0': high
D6 = '1': low
D5
D4
38/48
Instruction decoding bit
TDM
00 I2S standard
01 I2S - 4 ch
10 I2S - 8 ch (first channels)
11 I2S - 8 ch (last channels)
D3
0 (not used)
D2
0 (not used)
D1
0 (not used)
D0
0 (not used)
DocID022674 Rev 4
I2C registers
TDA7801
9.6
DB0-Addr:"10000" - Channel 1 (left front)
Table 16. DB0-Addr:"10000" - Channel 1 (left front)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Instruction decoding bit
Power on reset (POR)
0: After a POR the device is in tristate
1: The device has been put out of tristate at least one time after POR
Start-up diagnostic status
0: Turn-On diag. cycle not activated or not terminated
1: Turn-On diag. cycle terminated
Channel 1 offset detection
0: No output offset
1: Output offset detected
Channel 1(1)
0: Permanent diagnostic cycle not activated or not terminated
1: Permanent diagnostic cycle terminated
Channel 1
0: Normal load
1: Short load
Channel 1
0: No open load
1: Open load detection
(only during turn-on diagnostic)
Channel 1
0: No short to Vcc
1: Short to Vcc
Channel 1
0: No short to GND
1: Short to GND
1. The permanent diagnostic cycle is activated after each register reading if the permanent diagnostic is still
present, (IB0-d7="1").
DocID022674 Rev 4
39/48
I2C registers
9.7
TDA7801
DB1-Addr:"10001" - Channel 2 (left rear)
Table 17. DB1-Addr:"10001" - Channel 2 (left rear)
Bit
Instruction decoding bit
D7
TW1 active
0: TW1 threshold not trespassed
1: TW1 threshold tress-passed
D6
TW2 active
0: TW2 threshold not trespassed
1: TW2 threshold tress-passed
D5
Channel 2 offset detection
0: No output offset
1: Output offset detected
D4
Channel 2(1)
0: permanent diag. cycle not activated or not terminated
1: Permanent diag. cycle terminated
D3
Channel 2
0: Normal load
1: Short load
D2
Channel 2
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 2
0: No short to Vcc
1: Short to Vcc
D0
Channel 2
0: No short to GND
1: Short to GND
1. The permanent diagnostic cycle is activated after each register reading if the permanent diagnostic is still
present.
40/48
DocID022674 Rev 4
I2C registers
TDA7801
9.8
DB2-Addr:"10010"" - Channel 3 (right front)
Table 18. DB2-Addr:"10010"" - Channel 3 (right front)
Bit
Instruction decoding bit
D7
TW3 active
0: TW3 threshold not trespassed
1: TW3 threshold tress-passed
D6
TW4 active
0: TW4 threshold not trespassed
1: TW4 threshold tress-passed
D5
Channel 3 offset detection
0: No output offset
1: Output offset detected
D4
Channel 3(1)
0: Permanent diag. cycle not activated or not terminated
1: Permanent diag. cycle terminated
D3
Channel 3
0: Normal load
1: Short load
D2
Channel 3
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 3
0: No short to Vcc
1: Short to Vcc
D0
Channel 3
0: No short to GND
1: Short to GND
1. The permanent diagnostic cycle is activated after each register reading if the permanent diagnostic is still
present.
DocID022674 Rev 4
41/48
I2C registers
9.9
TDA7801
DB3-Addr:"10011" - Channel 4 (right rear)
Table 19. DB3-Addr:"10011" - Channel 4 (right rear)
Bit
1.
9.10
Instruction decoding bit
D7
0: channel 2 and 4 in play (FRONT)
1: channel 2 and 4 in mute
D6
0: channel 1 and 3 in play (REAR)
1: channel 1 and 3 in mute
D5
Channel 4 offset detection
0: No output offset
1: Output offset detected
D4
Channel 4(1)
0: permanent diag. cycle not activated or not terminated
1: Permanent diag. cycle terminated
D3
Channel 4
0: Normal load
1: Short load
D2
Channel 4
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 4
0: No short to Vcc
1: Short to Vcc
D0
Channel 4
0: No short to GND
1: Short to GND
The permanent diagnostic cycle is activated after each register reading if the permanent diagnostic is still present.
DB4-Addr:"10100"
Table 20. DB4-Addr:"10100"
Bit
42/48
Instruction decoding bit
D7
Ch1 tweeter present
D6
Ch2 tweeter present
D5
Ch3 tweeter present
D4
Ch4 tweeter present
D3
Signal to high
D2
0
D1
0
D0
0
DocID022674 Rev 4
TDA7801
10
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 39. PowerSO36 (slug-up) mechanical data and package dimensions
$)-
!
!
!
!
A
B
C
$
$
$
%
%
%
%
%
E
E
'
(
H
,
.
S
-).
MM
490
-!8
-).
INCH
490
-!8
h$AND%vDONOTINCLUDEMOLDFLASHORPROTUSIONS
-OLDFLASHORPROTUSIONSSHALLNOTEXCEEDMMv
.OINTRUSIONALLOWEDINWARDSTHELEADS
/54,).%!.$
-%#(!.)#!,$!4 !
0OWER3/3,5'50
'
'!0'03
DocID022674 Rev 4
43/48
Package information
TDA7801
Figure 40. Flexiwatt27 (vertical) mechanical data and package dimensions
',0
0,1
$
%
&
'
(
)
*
*
+
+
+
+
/
/
/
/
/
/
0
0
1
2
5
5
5
5
5
9
9
9
9
PP
7
工商网监
湘ICP备2023018690号
