VP0300L

– LETE VP0300 – OBSO P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / BVDGS -30V RDS(ON) (max) 2.5Ω ID(ON) (min) -1.5A Order Number / Package TO-92 VP0300L 7 Features ■ Free from secondary breakdown ■ Low power drive requirement ■ Ease of paralleling ■ Low CISS and fast switching speeds ■ Excellent thermal stability ■ Integral Source-Drain diode ■ High input impedance and high gain ■ Complementary N- and P-channel devices Advanced DMOS Technology These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. 9 Applications ■ Motor controls ■ Converters ■ Amplifiers ■ Switches ■ Power supply circuits ■ Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Package Options Absolute Maximum Ratings Drain-to-Source Voltage Drain-to-Gate Voltage Gate-to-Source Voltage Operating and Storage Temperature Soldering Temperature* * Distance of 1.6 mm from case for 10 seconds. 7-227 BVDSS BVDGS ± 20V -55°C to +150°C 300°C SGD TO-92 Note: See Package Outline section for dimensions. VP0300 Thermal Characteristics Package TO-92 ID (continuous)* -0.32A ID (pulsed) -0.87A Power Dissipation TC = 25°C 1.0W θja θjc °C/W 170 °C/W 125 * ID (continuous) is limited by max rated Tj. Electrical Characteristics (@ 25°C unless otherwise specified) Symbol BVDSS VGS(th) IGSS IDSS Parameter Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate Body Leakage Zero Gate Voltage Drain Current Min -30 -1.0 -1.8 -4.5 -100 -10 -500 ID(ON) RDS(ON) GFS CISS COSS CRSS t(ON) t(OFF) VSD ON-State Drain Current Static Drain-to-SourceON-State Resistance Forward Transconductance Input Capacitance Common Source Output Capacitance Reverse Transfer Capacitance Turn-ON Time Turn-OFF Time Diode Forward Voltage Drop -1.2 200 150 120 60 30 30 V ns pF -1.5 -1.7 2.5 µA A Ω m Typ Max Unit V V nA LETE – – OBSO Conditions VGS= 0V, ID =-10µA VGS = VDS, ID = -1mA VGS = ±30V, VDS = 0V VGS = 0V, VDS = -25V VGS = 0V, VDS = -25V TA = 125°C VGS = -12V, VDS = -10V VGS = -12V, ID = -1A VDS = -10V, ID = -0.5A VGS = 0V, VDS = -15V f = 1MHz VDD = -25V, ID = -1A RGEN = 25Ω VGS = 0V, ISD = -1.5A Notes 1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V 10% INPUT -10V PULSE GENERATOR 90% t(ON) Rgen t(OFF) tr td(OFF) tF INPUT td(ON) 0V 90% OUTPUT VDD 90% 10% 10% 7-228 Ω D.U.T. OUTPUT RL VDD