Si8457DB
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Vishay Siliconix
P-Channel 12 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
RDS(on) () MAX.
ID (A) a, e
0.0190 at VGS = -4.5 V
-10.2
0.0234 at VGS = -2.5 V
-9.2
0.0350 at VGS = -1.8 V
-7.5
VDS (V)
-12
Qg (TYP.)
37 nC
6
1.
7
845xx
x
m
m
mm
1.6
Backside View
1
• Ultra-small 1.6 mm x 1.6 mm maximum outline
• Ultra-thin 0.6 mm maximum height
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
MICRO FOOT® 1.6 x 1.6
D
3
• TrenchFET® p-channel Gen III and MICRO FOOT
power MOSFET technology provide extremely
low on-resistance per outline area
D
2
APPLICATIONS
S
• Power management
1
G
G
4
S
Bump Side View
Marking Code: 8457
D
Ordering Information:
Si8457DB-T1-E1 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
-12
Gate-Source Voltage
VGS
±8
TA = 70 °C
TA = 25 °C
ID
Continuous Source-Drain Diode Current
IDM
TA = 25 °C
TA = 25 °C
IS
TA = 70 °C
TA = 25 °C
PD
Package Reflow Conditions c
A
-25
-2.3 a
-0.92 b
1.8 a
1.1 b
W
0.73 b
TA = 70 °C
Operating Junction and Storage Temperature Range
-6.5 b
2.7 a
TA = 25 °C
Maximum Power Dissipation
-8.2 a
-5.2 b
TA = 70 °C
Pulsed Drain Current (t = 100 μs)
V
-10.2 a
TA = 25 °C
Continuous Drain Current (TJ = 150 °C)
UNIT
TJ, Tstg
-55 to 150
VPR
260
IR / convection
260
°C
Notes
a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s.
b. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s.
c. Refer to IPC / JEDEC® (J-STD-020), no manual or hand soldering.
d. In this document, any reference to case represents the body of the MICRO FOOT device and foot is the bump.
e. Based on TA = 25 °C.
S15-1692-Rev. B, 20-Jul-15
Document Number: 64267
1
For technical questions, contact: pmostechsupport@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8457DB
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient a,b
Maximum Junction-to-Ambient c,d
SYMBOL
RthJA
RthJA
t=5s
t=5s
TYPICAL
35
85
MAXIMUM
45
110
UNIT
°C/W
Notes
a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s.
b. Maximum under steady state conditions is 85 °C/W.
c. Surface mounted on 1" x 1" FR4 board with minimum copper, t = 5 s.
d. Maximum under steady state conditions is 175 °C/W.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
IGSS
VGS = 0 V, ID = -250 μA
IDSS
On-State Drain Current a
ID(on)
-5
1.8
0.0150
0.0190
0.0280
26
-0.9
± 100
-1
-10
0.0190
0.0234
0.0350
-
V
Zero Gate Voltage Drain Current
-12
-0.4
-5
-
2900
715
620
62
37
4.2
10
16
27
60
300
210
7
13
400
215
93
56
50
120
600
420
15
25
800
430
-
-0.72
240
640
93
147
-2.3 c
-25
-1.2
480
1280
-
Drain-Source On-State Resistance a
RDS(on)
Forward Transconductance a
Dynamic b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
gfs
Ciss
Coss
Crss
Total Gate Charge
Qg
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
Qgs
Qgd
Rg
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
IS
ISM
VSD
trr
Qrr
ta
tb
ID = -250 μA
VDS = VGS, ID = -250 μA
VDS = 0 V, VGS = ± 8 V
VDS = -12 V, VGS = 0 V
VDS = -12 V, VGS = 0 V, TJ = 70 °C
VDS -5 V, VGS = -4.5 V
VGS = -4.5 V, ID = -3 A
VGS = -2.5 V, ID = -3 A
VGS = -1.8 V, ID = -1 A
VDS = -6 V, ID = -3 A
VDS = -6 V, VGS = 0 V, f = 1 MHz
VDS = -6 V, VGS = -8 V, ID = -3 A
VDS = -6 V, VGS = -4.5 V, ID = -3 A
VGS = -0.1 V, f = 1 MHz
VDD = -6 V, RL = 2
ID -3 A, VGEN = -4.5 V, Rg = 1
VDD = -6 V, RL = 2
ID -3 A, VGEN = -8 V, Rg = 1
TA = 25 °C
IS = -3 A, VGS = 0 V
IF = -3 A, dI/dt = 100 A/μs, TJ = 25 °C
mV/°C
V
nA
μA
A
S
pF
nC
ns
A
V
ns
nC
ns
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %.
b. Guaranteed by design, not subject to production testing.
c. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S15-1692-Rev. B, 20-Jul-15
Document Number: 64267
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8457DB
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
25
10
VGS = 5 V thru 2 V
8
ID - Drain Current (A)
ID - Drain Current (A)
20
15
10
VGS = 1.5 V
5
TC = 25 °C
6
4
TC = 125 °C
2
0
TC = - 55 °C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Transfer Characteristics
Output Characteristics
0.10
4000
3500
Ciss
3000
VGS = 1.8 V
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
0.08
0.06
0.04
VGS = 2.5 V
2500
2000
1500
1000
Coss
Crss
0.02
500
VGS = 4.5 V
0
0
0
5
10
15
20
25
0
2
4
ID - Drain Current (A)
8
10
12
Capacitance
On-Resistance vs. Drain Current
1.4
ID = 3 A
RDS(on) - On-Resistance (Normalized)
8
VGS - Gate-to-Source Voltage (V)
6
VDS - Drain-to-Source Voltage (V)
VDS = 6 V
6
VDS = 3 V
4
VDS = 9.6 V
2
0
0
10
20
30
40
50
Qg - Total Gate Charge (nC)
Gate Charge
S15-1692-Rev. B, 20-Jul-15
60
70
1.3
VGS = 4.5 V, 2.5 V; ID = 3 A
1.2
1.1
VGS = 1.8 V; ID = 3 A
1.0
0.9
0.8
-50
-25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
Document Number: 64267
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Si8457DB
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.10
100
ID = 3 A
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
0.08
TJ = 150 °C
10
TJ = 25 °C
1
0.06
0.04
TJ = 125 °C
0.02
TJ = 25 °C
0
0.1
0.0
0.2
0.4
0.6
0.8
1.0
0
1.2
1
VSD - Source-to-Drain Voltage (V)
2
3
4
5
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.9
80
0.8
60
Power (W)
VGS(th) (V)
0.7
0.6
ID = 250 μA
40
0.5
20
0.4
0.3
- 50
- 25
0
25
50
75
100
125
0
150
0.001
0.01
TJ - Temperature (°C)
Threshold Voltage
0.1
1
Time (s)
10
100
600
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)*
IDM Limited
ID Limited
ID - Drain Current (A)
10
1 ms
10 ms
1
0.1
100 ms
1s
10 s
DC
TA = 25 °C
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
S15-1692-Rev. B, 20-Jul-15
Document Number: 64267
4
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8457DB
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Vishay Siliconix
10
1.5
8
1.2
6
0.9
Power (W)
ID - Drain Current (A)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
4
2
0.6
0.3
0
0.0
0
25
50
75
100
125
TA - Ambient Temperature (°C)
Current Derating a
150
25
50
75
100
125
150
TA - Ambient Temperature (°C)
Power Derating
Notes
• When mounted on 1" x 1" FR4 with full copper.
a. The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S15-1692-Rev. B, 20-Jul-15
Document Number: 64267
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8457DB
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 85 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
0.01
10 - 4
10 - 3
4. Surface Mounted
10 - 2
10 -1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient (1" x 1" FR4 Board with Full Copper)
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 175 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
Single Pulse
0.01
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient (1" x 1" FR4 Board with Minimum Copper)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?64267.
S15-1692-Rev. B, 20-Jul-15
Document Number: 64267
6
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
MICRO FOOT®: 4-Bumps
(1.6 mm x 1.6 mm, 0.8 mm Pitch, 0.290 mm Bump Height)
4x Ø b1
4x 0.30 to .31
(Note 3)
Solder mask-0.4
S
Mark on backside of die
D
S
G
e
e
Recommended land pattern
S
XXX
D
e
E
XXXX
S
e
S
D
b
Note 5
A1
A
A2
b1
K
Notes
1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
DIM.
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.550
0.575
0.600
0.0217
0.0226
0.0236
A1
0.260
0.275
0.290
0.0102
0.0108
0.0114
A2
0.290
0.300
0.310
0.0114
0.0118
0.0122
b
0.370
0.390
0.410
0.0146
0.0153
0.0161
b1
0.300
e
0.0118
0.800
0.0314
s
0.360
0.380
0.400
0.0141
0.0150
D
1.520
1.560
1.600
0.0598
0.0614
0.0157
0.0630
E
1.520
1.560
1.600
0.0598
0.0614
0.0630
K
0.155
0.185
0.215
0.0061
0.0073
0.0085
Note
• Use millimeters as the primary measurement.
ECN: T15-0175-Rev. A, 27-Apr-15
DWG: 6038
Revision: 27-Apr-15
1
Document Number: 69378
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Si8900EDB
3
2
1
0.18 ~ 0.25
A
1.08
0.5
B
0.285
0.285
0.5
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
www.vishay.com
1
AN824
Vishay Siliconix
TABLE 1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
MICRO FOOT CSP MOSFET
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
Bump Pitch*
Bump Diameter*
Bump Height*
0.8
0.37-0.41
0.26-0.29
0.5
0.18-0.25
0.14-0.19
0.5
0.32-0.34
0.21-0.24
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
TABLE 2
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MICRO FOOT Reliability Results
Test Condition C: −65_ to 150_C
>500 Cycles
Test condition B: −40_ to 125_C
>1000 Cycles
121_C @ 15PSI 100% Humidity Test
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Copper
FIGURE 3. SMD
www.vishay.com
2
Solder Mask
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
AN824
Vishay Siliconix
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Pitch
Copper Pad
Solder Mask
Opening
Stencil
Aperture
0.80 mm
0.30 " 0.01 mm
0.41 " 0.01 mm
0.33 " 0.01 mm
in ciircle aperture
0.50 mm
0.17 " 0.01 mm
0.27 " 0.01 mm
0.30 " 0.01 mm
in square aperture
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
Thermal Profile
250
200
Temperature (_C)
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
150
100
50
Stencil Design
IIncoming Tape and Reel Inspection
0
0
Solder Paste Printing
100
200
300
400
Time (Seconds
Chip Placement
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
FIGURE 5. SMT Assembly Process Flow
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
1.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
2.
Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
Resurface the pads using a temperature-controlled
soldering iron.
4.
Apply gel flux to the pad.
5.
Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
6.
Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
www.vishay.com
3
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