TC94A09F

TC94A09F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A09F Single-Chip CD Processor with Built-in Controller The TC94A09F is a single-chip CD processor for digital servo. The IC has a built-in 4-bit microcontroller. The controller features an LCD/LED driver, 4-channel 6-bit AD converter, 2/3-line serial interface, buzzer, interrupt function, and 8-bit timer/counter. The CPU can select one of three crystal oscillator operating clocks (16.9344 MHz, 4.5 MHz, and 75 kHz), facilitating interface with the CD processor. The CD processor incorporates sync separation protection and interpolation, EFM decoder, error correction, digital equalizer for servo, and servo controller. The CD processor also incorporates a Weight: 1.6 g (typ.) 1-bit DA converter. In combination with a RF amp TA2153FN and TA2109F, the TC94A09F can very simply configure an adjustment-free CD player. Thus, the IC is suitable for CD systems for automobiles and radio-cassette players. Features · · · Single-chip CD processor with built-in CMOS LCD/LED driver and 4-bit microcontroller Operating voltage Current dissipation At CD on: VDD = 4.5 to 5.5 V (typ. 5.0 V) At CD off: VDD = 3.0 to 5.5 V (only CPU on) At CD on: IDD = 50 mA (typ.) At CD off: IDD = 2 mA (with 4.5 MHz crystal oscillator, only CPU on) At CD off: IDD = 0.3 mA (with 75 kHz crystal oscillator, only CPU on) Ta = -40 to 85°C QFP100-P-1420-0.65A (0.65 mm pitch, 2.7 mm thick) TC94AP09F · · · Operating temperature range Package One-time PROM version 1 2001-10-15 TC94A09F 4-bit Microcontroller · · · · · · · · · Program memory (ROM): 16-bit ´ 12-k step Data memory (RAM): 4-bit ´ 512-word Instruction execution time: 1.89/1.78/40 ms (all one-word instructions) Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz Stack level: 8 AD converter: 6-bit ´ 4-channel LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max LED driver: 4-digit ´ 14-segment (max), also used as LCD driver switched by software I/O port: CMOS I/O port: 16 N-channel open drain I/O port: 4 (max) Output-only port: 4 (max), also used as CD processor pins Input-only port: 4 Timer/counter: 8 bit (INTR, instruction cycle, 100/1 kHz selectable as timer clock) 10, 100, or 500 Hz: internal port 2 Hz: Flip-flop port Serial interface: Supports 2/3-line method (data length: 4 or 8 bits) Buzzer: Four types: 0.75, 1, 1.5, and 3 kHz Four modes: Continuous, Single-Shot, 10 Hz Intermittent, and 10 Hz Intermittent at 1 Hz Interval Interrupts: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer) Back-up mode: three types Clock stop mode: X’tal operation stop Hardware wait mode: X’tal oscillation operation, no operation in CPU Software wait mode: Intermittent operation Reset function: Power-on reset, Built-in supply voltage detection circuit (Detection voltage = 2.5 V typ.) · · · · · · CD Processor · · · Reliable sync pattern detection, sync signal protection and interpolation Built-in EFM decoder and sub code decoder High-correction capability using cross interleave read Solomon code (CIRC) logical equation C1 correction: dual C2 correction: quadruple Supports variable speeds Jitter absorption capability of ±6 frames Built-in 16 KB RAM Built-in digital output circuit Built-in L/R independent digital attenuators Bilingual audio output (Note) Sub code Q data are read-timing free and can be output in sync with audio data. (Note) Built-in data slice and analog PLL (adjustment-free VCO used) circuit Auto adjustment of loop gain, offset, and balance at focus servo and tracking servo RF gain auto adjustment circuit Built-in digital equalizer for phase compensation Supports different pickups using digital equalizer coefficient RAM. Built-in focus and tracking servo control circuit Search control supports all modes and realizes high-speed, stable search. Lens kick and feed kick use speed control method. Built-in AFC circuit and APC circuit for disc motor CLV servo Built-in defect/shock detector Built in 8 times oversampling digital filter and 1-bit DA converter Output pins for sub code Q data and audio data are also used as LCD driver pins. The function of the pins can be switched by program. · · · · · · · · · · · · · · · · · · (Note) 2 2001-10-15 TC94A09F Pin Connections SLCO PVREF 2VREF RFGC VCOF SBAD RFRP TEBC RFCT XVDD LPFO * A AVDD LPFN * A 51 50 3 * TMAX 3 * PDO R * P2VREF M*V SS XVSS VSS M 80 DVSR * M RO * DVRR * R DVDD * M DVRL * R LO * DVSL * M TESTM IN2/(VPP) RST M * 3 * 3 75 * 3 * R * 3 * 3 * 3 70 * 3 * R * A * A * A 65 * A * A * A * A * A 60 * A * 3 RFI XO XI * A * A AVSS * 3 55 VREF DMO FMO RFZI FOO TEZI TRO VDD SEL TEI FEI * A * R 81 CD processor input/output 85 45 M*V DD * SBOK * SBSY * DOUT M * OT22 (COFS) M Controller test input M M M M M OSC M M M M M M M 100 LCD driver/LED driver output ports (LCD: 4 ´ 18 = 72 segments max, LED: 18 segments) 1 M S1 (OT5) M S2 (OT6) M S3 (OT7) M S4 (OT8) 5 M S5 (OT9) M S6 (OT10) M S7 (OT11) M S8 (OT12) M S9 (OT13) 10 M S10 (OT14/ZDET) M S11 (OT15/CLCK) M S12 (OT16/DATA) M S13 (OT17/SFSY) M S14 (OT18/LRCK) 15 M P8-0 (S15/BCK) M P8-1 (S16/AOUT) M P8-2 (OT17/MBOV) M P8-3 (OT18/IPF) M MVDD Power supply for controller 20 M MVSS M P1-0 M P1-1 M P1-2 M P1-3 I/O ports (16) 25 M P3-0 M P3-1 (ADin1) M P3-2 (ADin2) M P3-3 (ADin3) M P4-0 (ADin4/BUZR) 30 M P4-1 (SI2) 95 Power supply for controller 90 Reset input Hold input Interrupt input CD test input TC94A09F (QPF100 pin) M * OT21 (SPDA) 40 M * OT20 (SPCK) M * OT19 ( HSO ) M M M 35 M M M M 31 M TESTC IN1/BCKin P2-3/DATAin P2-2/LRCKin P2-1/ HSO in P2-0/EMPHin P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA) CD function pins switched together HOLD INTR MXO MXI MVSS MVDD COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) CD function pins switched together (Note) Symbols for the pins used above indicate the following pin functions: * M 3 A R M : CD processor-dedicated pin : Power supply pin : CD processor tri-state output pin : CD processor analog input/output pin : Reference input pin : Controller-dedicated pin (Note) When the CD is off, the power supply pins for the controller (MVDD) and the power pins supply for the CD oscillator (XVDD) are on and the CD processor-dedicated power supply (indicated by an asterisk *) pins are off. 3 2001-10-15 TC94A09F Block Diagram 2VREF RFGC SBAD TEBC RFRP AVDD AVSS VREF VREF DMO TRO SEL XVSS XI XO XVDD X’tal OSC Clock gene. PWM CD clock VREF DA Data slicer RFI SLCO ZDET DVSR RO 1 bit DAC DVRR DVDD DVRL LO DVSL Sub code decoder LPF SERVO control VREF AD RFCI FMO RFZI FOO TEZI TEI FEI PLL TMAX TMAX PDO P2VREF VCOF ROM RAM Digital equalizer Automatic adjustment circuit CLV servo Synchronous guarantee EFM decode VCO PVREF LPFO LPFN SBOK Address VDD VSS P2-0~P2-3 IN1 CD Reset Audio out Digital out 16 k SRAM Correction circuit SBSY DOUT MXO MXI P1-3 (K3) Port1 P1-0 (K0) Timer Data Reg (16 bit) SBSY Interrupt INTR Cont. Serial Interface P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA) Port4 P4-1 (SI2) P4-0 (Adin4/BUZR) Program Counter Instruction Decoder F/F BUZR Reset Stack Reg. (8Level) Power on Reset Port3 P3-1 (Adin1) P3-0 LCD Driver/Output Port Port8 Bias ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF Port2 ROM (16 ´ 12288 Step) RAM (4 ´ 512 word) ALU G-Reg. R/W Buf. CPU clock SBSY CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF Reset X’tal OSC MPX Micon interface OT22 (COFS) OT21 (SPDA) OT19-22 OT20 (SPCK) OT19 ( HSO ) HOLD TESTM TESTC IN1 IN2 P2-0 (EMPHin) P2-1 ( HSO in) P2-2 (LRCKin) P2-3 (DATAin) AD Conv. P3-3 (Adin3) P3-2 (Adin2) RST MVDD MVSS P8-1 (S16/AOUT) P8-0 (S15/BCK) S10 (OT14/ZDET) S11 (OT15/CLCK) S12 (OT16/DATA) S13 (OT17/SFSY) 4 S14 (OT18/LRCK) P8-2 (S17/MBOV) P8-3 (S18/IPF) COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) S1 (OT5) S2 (OT6) 2001-10-15 TC94A09F Pin Descriptions Pin Number Symbol Pin Name Function and Operation Common signal output pins for the LCD panel. Those pins configure matrix with S1 to S18 and display up to 72 segments. The LCD can be driven by the 1/2 or 1/3 bias method. When the 1/2 bias method is set three levels, MVDD, 1/2MVDD, and GND, are output at 2-ms intervals. When the 1/3 bias method is set four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are output at a 62.5 Hz cycle (when MVDD either the 4.5 MHz or 75 kHz crystal oscillator is used). After system reset or clock stop execution is released, the non-selected waveform (bias voltage) is output. The DISP OFF bit is set to 0 and the common signal is output. 100 COM4/OT4 These pins can be switched to an output port (Note1) or LED driver pins by program. They are usually used for digit output to drive the LEDs. Segment signal output pins for the LCD panel. Those pins configure a matrix with COM1 to COM4 and display up to 72 segments. When the 1/2 bias method is set two levels, MVDD and GND, are output. When the 1/3 bias method is set four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are output. The S1 to S14 pins can be switched to an output port (Note1) by program. Port 8 and S15 to S18 pins can be switched pin by pin to an I/O port and segment output pins. When the pins are set to an I/O port, output is N-channel open drain. The S10 to S14 and P8-0 to P8-3 pins can be switched to CD signal input/output pins by program. Setting the CD10 bit to 1 switches the pins to the LRCK, BCK, and AOUT pins as the CD pins in batches. The other pins can be individually switched according to the S14/S15/S16 segment data. ･CLCK Inputs/outputs sub code P to W data reading clock. ･DATA Outputs sub code P to W data. ･SFSY Outputs frame sync signal for playback. ･LRCK Outputs channel clock (44.1 kHz). When L channel, outputs Low. When R channel, outputs High. The polarity Input can be inverted by command. ･BCK Outputs bit clock (1.4112 MHz). instruction ･AOUT Outputs audio data. ･MBOV Outputs buffer-memory-overflow signal. When buffer memory overflows, outputs H. ･IPF Outputs interpolation pointing flag. If AOUT output is C2 error detection/correction, outputs High to indicate correction is impossible. ･ZDET Outputs 1-bit DAC zero detection flag. Remarks 97 COM1/OT1 98 COM2/OT2 LCD common output /output port MVDD Bias voltage 99 COM3/OT3 1~9 S1/OT4 ~ S9/OT13 LCD segment output /output port 10 S10/OT14 /ZDET 11 S11/OT15 /CLCK 12 S12/OT16 /DATA LCD segment output /output port /CD signal MVDD MVDD 13 S13/OT17 /SFSY 14 S14/OT18 /LRCK MVDD 15 P8-0/S15 /BCK Bias potential 16 P8-1/S16 /AOUT 17 P8-2/S17 /MBOV I/O port /LCD segment output /CD signal Pins set as an output port are used for segment output for the LED driver. The output port can increment OT1 to OT18 by instruction, facilitating access to data in external RAM and ROM. (Note1) After a system reset, pins also used as output ports are set to LCD output; pins also used as I/O ports are set to I/O port input. 18 P8-3/S18 /IPF 5 2001-10-15 TC94A09F Pin Number Symbol Pin Name Function and Operation Remarks MVDD 4-bit CMOS I/O port. Input/output can be set for each bit by program. 21~24 P1-0~P1-3 I/O port 1 The pins can be set to be pulled-up or pulled-down by program. Thus, they can be used as key input pins. When the pins are set to I/O port input, Clock Stop mode and Wait mode can be released, according to the change in input to the pins. RIN1 MVDD MVDD 5-bit CMOS I/O port. Input/output can be set for each bit by program. 25 P3-0 I/O port 3 P3-1 and P4-0 pins are also used as built-in 6-bit 4-channel AD converter analog input pins. The built-in AD converter uses successive approximation. The conversion time is 6 instruction cycles (280 ms) when the 75 kHz crystal oscillator is used; 198 ms when the 4.5 MHz crystal oscillator is used; 180 ms when the 16.9344 MHz crystal oscillator is used. AD analog input can be set for each pin by program. The internal power supply (MVDD) is used as the reference voltage. The P4-0 pin is also used as the buzzer output pin. One of four frequencies: 0.75, 1, 1.5, and 3 kHz, can be selected for buzzer output. The buzzer is output at the selected frequency at 1 Hz intervals in one of four modes: Continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz interval. Settings for the AD converter and buzzer, and their control can be performed by program. P2-0 /EMPHin P2-1/HSOin P2-2 /LRCKin P2-3 /DATAin I/O port 2 /1-bit DAC input MVDD 26~28 P3-1/ADin1 ~ P3-3/ADin3 I/O port 3 /AD analog voltage input To AD converter Input instruction 29 P4-0 /ADin4 /BUZR I/O port 4 /AD analog voltage input /buzzer output 33 34 MVDD I/O port 2 is a 4-bit CMOS I/O port. IN1 and IN2 are a 2-bit general-purpose input port. Input/output can be set for each bit of I/O port 2 by program. I/O port 2 and the IN1 pin can be switched to 1-bit DAC input pins by the CD command to support shock-proofing functions. In this case, the I/O port must be set to input. MVDD 35 36 MVDD 37 89 IN1/BCKin IN2/ (VPP) General-purpose input port /1-bit DAC input (VPP input) With the OTP version, the IN2 pin is also used as the program power supply pin. 6 2001-10-15 TC94A09F Pin Number Symbol Pin Name Function and Operation 3-bit CMOS I/O port. Input/output can be set for each bit by program. These pins are also used as serial interface (SIO) circuit input/output pins. SIO is a serial interface supporting 2-line and 3-line methods. Starting from the MSB or LSB, 4 or 8-bit serial data are output to the SO/SDA pin, or data on the S11 and S12 pins are input to the device at the clock edge on the SCK/SCL pin. As the serial operating clock (SCK/SCL), an internal (450/225/150/75 kHz) or external clock can be selected. Rising or falling shift can also be selected. The clock and data output can be N-channel open drain. These selections facilitate controlling the LSI and communications between the controllers. When SIO interrupts are enabled, an interrupt is generated as soon as execution of the SIO completes, and the program jumps to address 4. This is effective for performing serial communications at high speed. All SIO inputs incorporate a Schmidt circuit. SIO and its control can be set by program. MVDD Remarks I/O port 4 30 31 32 P4-1/S12 P4-2 /SI0/SI1/ SDA P4-3 /SCK/SCL /Serial data input /Serial data input/output /Serial clock input/output Input instruction + SI0ON 38 TESTC Test mode control input MVDD Input pins for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). RIN2 88 TESTM 4-bit general-purpose output port. After system reset, the pins are set to a Low-level output port. The pins can be switched to CD control output pins by program. Setting OT19 to OT22 to 0 switches all four pins to CD control output pins. Setting the CDIO bit to 1 enables the pins to be switched as follows according to the segment data contents of the S15 and S16 pins: ･ HSO Outputs playback speed mode. Normal speed: High Double speed: Low MVDD OT19/ HSO OT20/SPCK 39~42 OT21/SPDA OT22/COFS Output port /CD control signal output ･SPCK Outputs clock for reading processor status signal (176.4 kHz). ･SPDA Outputs processor status signal. ･COFS Outputs frame clock for correction (7.35 kHz). 7 2001-10-15 TC94A09F Pin Number 43 Symbol Pin Name Function and Operation Remarks DOUT Digital out output pin. Sub code block sync output pin. VDD 44 SBSY When sub code sync is detected, outputs High at the S1 position. Sub code Q data CRCC result output pin. 45 SBOK When the result is OK, outputs High. Power supply pins for CD digital block. Normally, 5 V is applied. 46, 75 VDD VDD 47, 76 VSS When CD is not used (CD off), the power supply can be set to off, but only the controller power supply can be set to on, enabling the controller to operate. At this time, 1 must be set in the CDoff bit. If pins from 11 to 18 and 39 to 42 are set as CD control signal input/output pins, setting the CDoff bit to 1 switches all the pins to an output port. 2VREF pin for PLL block ¾ P2VREF MVSS 48 P2VREF 49 PDO Outputs phase error signal between the EFM and PLCK signals. CD processor control input/output TMAX detection result output pin. Selected by command bit TMPS. 50 TMAX Longer than the specified cycle: Outputs P2VREF. Shorter than the specified cycle: Outputs Low level (VSS). Within the specified cycle: at high impedance 51 52 53 54 55 LPFN LPFO PVREF VCOF AVSS Inverted input pin for low-pass filter amp. Output pin for low-pass filter amp. VREF pin for PLL block VCO filter pin Ground pin for analog block PVREF P2VREF AVDD PVREF LPFN LPFO PVREF VCO VCOF ¾ Zin1 56 SLCO DAC output pin for generating data slice level RFI AVDD VREF 57 RFI RF signal input pin SLCO DAC ¾ 58 AVDD Power supply pin for analog block 8 2001-10-15 TC94A09F Pin Number Symbol Pin Name Function and Operation Remarks AVDD RFZI 59 RFCT RFRP signal center level input pin 60 RFZI RFRP zero-cross signal input pin RFCT 1 kW typ. 32 kW typ. 61 RFRP RF ripple signal input pin AVDD RFRP 62 FEI Focus error signal input pin FEI 63 SBAD Sub beam addition signal input pin Tracking error input pin. SBAD TEI 64 TEI The pin is read at tracking servo on. AVDD TEZI 65 TEZI Tracking error/zero-cross signal input pin VREF Zin2 1 kW typ. 32 kW typ. 66 FOO CD processor control input/output Focus equalizer output pin Rout3 Tracking equalizer output pin AVDD 2VREF~ AVSS 67 TRO 68 VREF Analog reference voltage power supply pin Control signal output pin for adjusting RF amplitude. ¾ 69 RFGC Outputs tri-state PWM signal (PWM carrier = 88.2 kHz). Tracking balance control signal output pin. P2VREF 70 TEBC Outputs tri-state PWM signal (PWM carrier = 88.2 kHz). Focus equalizer output pin. Rout3 71 FMO Outputs tri-state PWM signal (PWM carrier = 88.2 kHz). Disc equalizer output pin. VREF 72 DMO Outputs tri-state PWM signal (PWM carrier = 88.2 kHz for DSP block, in sync with PXO). Analog reference voltage power supply pin (2 ´ VREF) ¾ VDD APC circuit on/off signal output pin. 73 2VREF 74 SEL At laser on, high impedance at UHS = High; H level output at UHS = High. 9 2001-10-15 TC94A09F Pin Number 77 Symbol XVSS Pin Name Function and Operation Power supply pins for CD crystal oscillator. To control the CD processor power supply and the controller power supply individually, connect the MVDD and MVSS pins to the power supply lines used in common for the VDD and VSS pins. CD crystal oscillator input/output pins. Connect a 16.9344 MHz crystal oscillator. The clock is used as the CD system clock and controller system clock. After system reset, this clock is supplied as the controller system clock and starts the CPU. The crystal oscillator can be halted by program. If the 4.5 MHz or 75 kHz oscillator is selected as the controller system clock, the oscillator is halted by program when the CD processor is off. 79 XO (Note) When switching the controller system clock from the controller oscillator to the CD crystal oscillator, make sure that the CD crystal oscillator is in stable state. XO RfXT1 XVDD ¾ Remarks 80 XVDD 78 XI CD processor crystal oscillator pins Rout1 XI XVSS 81 DVSR R-channel DA converter block ground pin 82 RO R-channel data forward rotation output pin DVDD DVRR/DVRL 83 DVRR R-channel reference voltage pin 84 DVDD CD processor control DA converter block power supply pin input/output RO/LO DVDD 85 DVRL L-channel reference voltage pin DVSL/DVSR VSS 86 LO L-channel data forward rotation output pin 87 DVSL L-channel DA converter block ground pin Device system reset signal input pin While the RST is at Low level, reset is applied. When the RST is at High level, the CD block is in operation, and the controller program starts from address 0. Normally, when 2.7 V or higher voltage is supplied to the MVDD when at 0 V, system reset is applied (power-on reset). Fix the pin to High level. MVDD 90 RST Reset input 10 2001-10-15 TC94A09F Pin Number Symbol Pin Name Function and Operation Input pin used to request or release hold state. Normally, the pin is used for inputting the CD mode selection signal or battery detection signal. Halt states are Clock Stop mode (crystal oscillator stops oscillation) and Wait mode (CPU stops). The modes are entered using the CKSTP and WAIT instructions. By program, Clock Stop mode can be entered by detection of Low level on the HOLD pin or by forced execution. Clock Stop mode can be released by detection of High level on the HOLD pin or change in the HOLD pin input. Executing the CKSTP instruction stops the clock generator and the CPU, entering memory backup state. During memory backup state, current dissipation becomes low (1 mA or below). The display output and CMOS output port automatically become Low level. The N-channel open drain output becomes off. Regardless of the HOLD pin input state, Wait mode is executed and current dissipation becomes low. Crystal oscillator only on or CPU operation suspended can be programmed. When the crystal oscillator only is on, all displays are at Low level. The other pins are in hold state. When CPU operation is suspended, all states are held except that the CPU is suspended. Wait mode is released by a change of the HOLD pin input. (Note) For Backup mode, use the oscillator connected to the MXO and MXI pins. Turn off the VDD pin (power supply for CD), and enter Backup mode. External interrupt input pin. When interrupts are enabled and a pulse of 1.11 to 3.33 ms or more (13.3 to 40 ms when the 75 kHz clock is used) is input to this pin, an interrupt is generated and the program jumps to address 1. Input logic and rising/falling edge can be individually selected for interrupt inputs. The internal 8-bit timer clock can be selected for interrupt inputs. Interrupts can be generated (address 3) by pulse count or the count value. Interrupt inputs are Schmidt inputs. The pin can be used as an input port for inputs such as remote control signals. Remarks MVDD 91 HOLD Hold mode control input 92 INTR External interrupt input 11 2001-10-15 TC94A09F Pin Number Symbol Pin Name Function and Operation Crystal oscillator pins for the controller. The oscillator clock is used as a time base for the clock function as well as the system clock for the controller. After system reset, the CPU starts operation using the 16.9344 MHz CD oscillator (connected to the XI and XO pins). The oscillator is switched to the controller oscillator by program. Either a 4.5 MHz reference oscillator or a 75 kHz oscillator is connected to the MXO and MXI pins. MXO The oscillators are switched by a bit used to select a frequency of 4.5 MHz or 75 kHz. The oscillators incorporate a feedback resistor. Switching frequencies automatically switches the feedback resistor of the crystal oscillator. 75 kHz: Rout2 = 2 kW, RfXT2 = 10 MW typ. 4.5 MHz: Rout2 = 2 kW, RfXT2 = 1 MW typ. If the operating clock is the CD crystal oscillator, fix the MXI pin to GND. 94 MXI During execution of the CKSTP instruction, oscillation halts. Selection and control of crystal oscillators are done by program. (Note) When the 75 kHz crystal oscillator is used, externally add/connect a 100 kW output resistor. MXI Remarks 93 MXO Rout2 RfXT2 MVDD Crystal oscillator for controller Power supply pins for the controller block. 19, 96 MVDD Normally, VDD = 4.5 to 5.5 V. In backup state (when executing the CKSTP instruction), current dissipation becomes low (1 mA or below), dropping the power supply voltage to 2.0 V. MVDD Power supply pins for controller block If 2.7 V or more is applied to these pins when at 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). 20, 95 MVSS (Note) At power-on reset operation, allow 10 to 100 ms while the device power supply voltage rises. MVSS 12 2001-10-15 TC94A09F Maximum Ratings (Ta = 25°C, VDD = DVDD = AVDD, MVDD = XVDD) Characteristics Power supply voltage VDD power supply pin Input voltage MVDD power supply pin Power dissipation Operating temperature Storage temperature VIN2 PD Topr Tstg -0.3~MVDD + 0.3 1400 -40~85 -65~150 mW °C °C Symbol VDD MVDD VIN1 Test Condition -0.3~6.0 (MVDD > VDD) = -0.3~VDD + 0.3 V Unit V 13 2001-10-15 TC94A09F Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = MVDD = XVDD = DVDD = AVDD = 5 V, 2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V) VDD (power supply pins for CD processor block: VDD, XVDD, DVDD, and AVDD) Characteristics Operating power supply voltage range Symbol VDD IDD XIDD Crystal oscillator standby current Crystal oscillator frequency XSTBY fXT Test Circuit ¾ ¾ ¾ ¾ ¾ Test Condition MVDD = XVDD > VDD = DVDD = AVDD = (VDD, DVDD, AVDD) operating at 16.9344 MHz (XVDD) 16.9344 MHz crystal oscillator connected (XVDD) 16.9344 MHz crystal oscillator off Ci = Co = 15 pF (Note 1)* * Min 4.5 ¾ ¾ ¾ ¾ Typ. ~ 50 2.0 0.01 16.9344 Max 5.5 60 mA ¾ ¾ ¾ mA MHz Unit V Operating power supply current MVDD (power supply pins for CPU block: MVDD, XVDD) (Note 2) Characteristics Symbol MVDD1 Operating power supply voltage range ¾ Test Circuit Test Condition CPU and CD in operation MVDD = XVDD > VDD = DVDD = AVDD = CPU in operation (CD off, 4.5 MHz/16.9344 MHz crystal oscillator used) CPU in operation (CD off, 75 kHz crystal oscillator used) ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ CPU in operation Crystal oscillator stopped (executing CKSTP instruction) Min 4.5 Typ. ~ Max 5.5 Unit * MVDD2 4.5 * * * 3.0 2.0 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ~ 5.5 V MVDD3 Memory hold voltage range MVHD MIDD1 MIDD2 Operating power supply current (Note 3) MIDD3 MIDD4 MIDD5 MIDD6 Memory hold current MIHD fMXT1 Crystal oscillator frequency fMXT2 Crystal oscillator start time tst ~ ~ 3.0 1.4 0.3 1.5 0.25 0.1 0.1 4.5 75 ¾ 5.5 5.5 5.0 2.5 1.0 mA ¾ ¾ ¾ 1.0 ¾ ¾ 1.0 mA MHz kHz s XI = 16.9344 MHz crystal oscillator connected MXI = 4.5 MHz crystal oscillator connected MXI = 75 kHz crystal oscillator connected XI = 16.9344 MHz crystal oscillator connected Standby mode MXI = 4.5 MHz crystal (crystal oscillator oscillator connected only in operation) MXI = 75 kHz crystal oscillator connected Crystal oscillator stopped (executing CKSTP instruction) 4.5 MHz crystal oscillator set 75 kHz crystal oscillator set, MVDD = 2.7~5.5 V Crystal oscillator fmxt = 75 kHz (Note 1)* (Note 1)* ¾ ¾ ¾ Note 1: Design and set constants according to the crystal oscillator to be connected. Note 2: The power supply/memory hold current is the value obtained by summing the XVDD and MVDD pin currents. Note 3: The values are those when the power supply detector function is operating. Setting the function reduces current dissipation by 150 mA (typ.). (Except in Standby mode) An asterisk (*) indicates the values are guaranteed when VDD = MVDD = XVDD = DVDD = AVDD and Ta = -40 to 85°C. When CD is off, VDD = DVDD = AVDD = 0 V 14 2001-10-15 TC94A09F LCD common output/output port (COM1/OT1~COM4/OT4) Characteristics “H” level Output current “L” level 1/2 level Bias voltage 1/3 level 2/3 level Symbol IOH1 IOH2 IOL1 IOL5 VBS2 VBS1 VBS3 Test Circuit ¾ ¾ ¾ ¾ ¾ ¾ ¾ Test Condition VOH = 4.5 V (LCD output) VOH = 4.5 V (OT output) VOL = 0.5 V (LCD output) VOL = 0.5 V (OT output) No load (LCD output, 1/2 bias method set) No load (LCD output, 1/3 bias method set) 3.13 3.33 3.53 Min -200 -15 200 4.0 2.3 1.47 Typ. -600 -30 600 10 2.5 1.67 Max ¾ ¾ ¾ ¾ 2.7 1.87 V Unit mA mA mA mA Segment output, output ports, I/O ports, and CD function output (S1/OT4~S9/OT13, S10/OT14/ZDET~S14/OT18/LRCK, P8-0/S14/BCK~P8-3/S18/IPF, OT19) Characteristics Symbol IOH1 “H” level Output current “L” level Input leakage current “H” level Input voltage “L” level 1/3 level Bias voltage 2/3 level VIL VBS1 VBS3 ¾ ¾ ¾ (P8-0~P8-3, CLCK) IOH4 IOL1 IOL5 ILI VIH Test Circuit ¾ ¾ ¾ ¾ ¾ ¾ Test Condition VOH = 4.5 V (LCD output) VOH = 4.5 V (OT output, CD output, excluding P8-0~P8-3 pins) VOL = 0.5 V (LCD output) VOL = 0.5 V (OT output, CD output) VIH = 5.0 V, VIL = 0 V (P8-0~P8-3) (P8-0~P8-3, CLCK) Min -200 -1.5 200 4.0 ¾ MVDD ´ 0.8 0 1.47 No load (LCD output, 1/3 bias method set) 3.13 3.33 3.53 Typ. -600 -4.0 600 10 ¾ ~ ~ 1.67 Max ¾ ¾ ¾ ¾ ±1.0 MVDD V MVDD ´ 0.2 1.87 V Unit mA mA mA mA mA I/O port (P1-0~P4-3) Characteristics “H” level Output current “L” level Symbol IOH3 IOL3 IOL5 Input leakage current “H” level Input voltage “L” level Input pull-up/down resistance VIL RIN1 ¾ ¾ ¾ (P1-0~P1-3 pins) pull-down/up set ILI VIH Test Circuit ¾ ¾ ¾ ¾ ¾ VOH = 4.5 V VOL = 0.5 V (excluding P4-1, P4-2, P4-3 pins) VOL = 0.5 V (P4-1, P4-2, P4-3 pins) VIH = 5.0 V, VIL = 0 V ¾ Test Condition Min -0.8 1.0 4.0 ¾ MVDD ´ 0.8 0 25 Typ. -2.0 3.0 10 ¾ ~ ~ 50 Max ¾ ¾ ¾ ±1.0 MVDD V MVDD ´ 0.2 120 kW mA mA Unit HOLD , INTR input port, RST input, 1-bit DAC data input (EMPHin/HSOin/LRCKin/DATAin/BCKin) Input port (IN1/IN2) Characteristics Input leakage current “H” level Input voltage “L” level VIL ¾ ¾ Symbol ILI VIH Test Circuit ¾ ¾ Test Condition VIH = 5.0 V, VIL = 0 V ¾ Min ¾ MVDD ´ 0.8 0 Typ. ¾ ~ ~ Max ±1.0 MVDD V MVDD ´ 0.2 Unit mA 15 2001-10-15 TC94A09F AD converter (ADin1~ADin4) Characteristics Analog input voltage range Resolution Total conversion error Analog input leakage Symbol VAD VRES ¾ ILI Test Circuit ¾ ¾ ¾ ¾ ADin1~ADin4 ¾ ¾ VIH = 5.0 V, VIL = 0 V (ADin1~ADin4) Test Condition Min 0 ¾ ¾ ¾ Typ. ~ 6 ±0.5 ¾ Max MVDD ¾ ±1.0 ±1.0 Unit V bit LSB mA DOUT, SBSY, SBOK, SEL, OT19/ HSO , OT20/SPCK, OT21/SPDA, OT22/COFS output Characteristics “H” level Output current “L” level Symbol IOH4 IOL4 Test Circuit ¾ ¾ VOH = 4.5 V VOL = 0.5 V Test Condition Min -1.5 1.5 Typ. -4.0 4.0 Max ¾ ¾ Unit mA PDO, TMAX, RFGC, TEBC, FMO, DMO, TRO, FOO output Characteristics Output current Output resistance VREF output resistance “H” level “L” level Symbol IOH6 IOL4 Rout3 Voref Test Circuit ¾ ¾ ¾ ¾ Test Condition VOH = 3.8 V, P2VREF = 4.2 V (PDO, TMAX) VOL = 0.5 V, P2VREF = 4.2 V (PDO, TMAX) (RFGC, TEBC, FMO, DMO, TRO, FOO) (RFGC, TEBC, FMO, DMO, PDD) VREF = PVREF = 2.1 V Min ¾ ¾ ¾ ¾ Typ. -2.0 6.0 3.3 2.1 Max ¾ ¾ ¾ ¾ Unit mA kW V Transfer delay time (AOUT, SPDA, DATA, SBSY, SBOK) Characteristics Transfer delay time “H” level “L” level Symbol tpLH tpHL Test Circuit ¾ ¾ Test Condition ¾ ¾ Min ¾ ¾ Typ. 10 10 Max ¾ ¾ Unit ns 1-bit DA converter Characteristics Total harmony distortion S/N ratio Dynamic range Crosstalk Analog output level Symbol THD + N S/N DR CT DACout Test Circuit ¾ ¾ ¾ ¾ ¾ Test Condition 1 kHz sine wave, full-scale input ¾ 1 kHz sine wave, -60dB input conversion 1 kHz sine wave, full-scale input 1 kHz sine wave, full-scale input Min ¾ 90 85 ¾ 1200 Typ. -85 98 90 -90 1250 Max -78 ¾ ¾ -85 1300 mVrms dB Unit 16 2001-10-15 TC94A09F Others Characteristics Input pull-down resistance XI amp feedback resistance XO output resistance MXI amp feedback resistance MXO output resistance Symbol RIN2 RfXT1 Rout1 RfXT2 Rout2 Test Circuit ¾ ¾ ¾ ¾ ¾ ¾ Test Condition (TESTC, TESTM) (XI-XO) (XO) When 4.5 MHz crystal set, (MXI-MXO) When 75 kHz crystal set, (MXI-MXO) (MXO) Min ¾ 1.0 ¾ 0.5 ¾ ¾ ¾ Zin1 ¾ Set resistance by (RFI) CD command ¾ ¾ ¾ Zin2 ¾ (TEZI) ¾ Typ. 10 2.0 0.5 1.0 10 2.0 10 5 2.5 1.25 10 Max ¾ 4.0 ¾ 2.5 ¾ ¾ ¾ ¾ ¾ ¾ ¾ kW Unit kW MW kW MW kW Input resistance 17 2001-10-15 TC94A09F Package Dimensions Weight: 1.6 g (typ.) 18 2001-10-15 TC94A09F RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 19 2001-10-15