SI9730DBY-T1

Si9730 Vishay Siliconix Dual-Cell Lithium Ion Battery Control IC FEATURES D D D D D D Over-Charge Protection Over-Discharge Protection Short Circuit Current Limiting Battery Open-Circuit Center Tap Protection Cell Voltage Balancing Undervoltage Lockout D D D D D D Individual Cell Voltage Monitoring Low Operating Current (30 mA) and Shutdown Current (1 mA) Internal N-Channel MOSFET Driver High Noise Immunity Accurate ("1.19%) Over-Charge Voltage Detection Four Different Cell Types Covered DESCRIPTION The Si9730 monitors the charging and discharging of dual-cell lithium-ion battery packs (carbon or coke chemistry) ensuring that battery capacity is fully utilized while ensuring safe operation. The Si9730 provides protection against overcharge, over-discharge, and short circuit conditions which are hazardous to the battery and the environment. Battery voltages of each individual cell are monitored at the center-tap connection by an internal A/D converter through the VC pin. If one or both of the cells is determined to be overcharged, an internal cell balancing network “bleeds” off current at 15 mA until both cells are charged to the same maximum level. Depending on the condition of each cell, the Si9730 will switch two external source-connected n-channel MOSFETs on or off to allow the cells to be charged or to provide current to the load. The Si9730 is available in an 8-pin SOIC package with an operating temperature range of −25 to 85°C. The Si9730 is available in both standard and lead (Pb)-free packages. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION C VDD Undervoltage Lockout Timer CDELAY Time Out CLK + VC1 − Cell Balancing Network VC A/D Converter OUT Control Logic + VC2 − Oscillator 1.2 VREF VSS SOUT VSS DCO ILIMIT IS VM GS Generator VM Document Number: 70658 S-40135—Rev. F, 16-Feb-04 www.vishay.com 1 Si9730 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD −15 V to VDD +15 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS −0.3 V to VSS +12 V VC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS −0.3 V to VDD +0.3 V IS (VSS w VM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VM −0.3 V to VDD +0.3 V (VM w VSS ) . . . . . . . . . . . . . . . . . . . . . . . . . . VSS −0.3 V to VDD +0.3 V Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW Thermal Impedance (PQJA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80_C/W Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 to 150_C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE CVC t10 pF from VC toVDD andVSS , Total CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open to 1.0 mF RIS series resistance to sense resistor . . . . . . . . . . . . . . . . . . . . . . . . t27 kW DCO Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2000 pF VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V VDD to VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 to 85_C SPECIFICATIONS Limits Parameter Power Supply Supply Current, Charging Operation Supply Current Normal Operation Current, Undervoltage Lockout Threshold VM Leakage Current VM Operating Current IDD_C IDD IDD_UVL VUVL IVM_UVL IVM VC1 = VC2 = 2.6 V, VDD − VM = 8.4 V VC1 = VC2 = 4.05 V, VM = VSS VM = VDD,VC1 = VC2 = 1.7 V Measured at VDD − VSS (Falling) VC1 = VC2, VDD − VM = 5.5 V VC1 = VC2 = 1.7 V, VDD = VM VC1 = VC2 = 2.6 V, VDD − VM = 8.4 V 3.5 3.7 60 30 1 4.0 1 30 V mA mA Symbol Test Condition Unless Otherwise Specified TA = −25 to 85_C Mina Typb Maxa Unit Control Logic DCO Output High Voltage DCO Rise Time (10% to 80%) DCO Fall Time (80% to 10%) DCO Output Low Voltage VOH tr tf VOL IOH = −10 mA, VC1 = VC2 = 3.3 V VDD − VM = 6.6 V VC1 = 2 V, VC2 = 2.4 V .4 VDD − VM = 8.4 V CL = 500 pF, DCO to VSS IOL = 10 mA VM = VDD VC1 = 2 V, VC2 = 2.4 V VM= VSS VC1 = VC2 = 4.4 V, IS = VDD VDD − 0.1 7.5 1 VSS +0.4 V VM +0.52 V ms Analog Section Current-Limit Comparator Trip Point Current-Limit Comparator Temperature Coefficient Current-Limit Comparator Response Time Current Limit Comparator Input Bias Current www.vishay.com VILIMIT dVILIMIT/dT tILIMIT IIS VC1 = VC2 =3.3 V, VM = VSS + 0.25 V CL = 50 pF, DCO to VSS, See Figure 2 VC1 = VC2 =3.3 V, VDD = VM, VIS = VSS −125 VC1 = VC2 =4.05 V, VM = VSS + 0.25 V IS Rising, TA = 25_C 25.5 28 0.18 25 32 mV %/_C ms nA 2 Document Number: 70658 S-40135—Rev. F, 16-Feb-04 Si9730 Vishay Siliconix SPECIFICATIONS Limits Parameter Analog Section (cont’d) VOC1 Cell Cell 1 A Suffix VOC2 Cell Cell 2 VC2 = 4.05 V 05 VDD − VM = 8.6 V .6 VC1 = 4.05 V 05 VDD − VM = 8.6 V .6 VC2 = 4.05 V 05 VDD − VM = 8.6 V .6 VC1 = 4.05 V 05 VDD − VM = 8.6 V .6 VC2 = 4.05 V 05 VDD − VM = 8.6 V .6 VC1 = 4.05 V 05 VDD − VM = 8.6 V .6 VC2 = 4.05 V 05 VDD − VM = 8.6 V .6 VC1 = 4.05 V 05 VDD − VM = 8.6 V .6 TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C TA = 25_C TA = −25_C TA = 85_C VC2 = 4.05 V VC1 = 4.05 V VC2 = 2.6 V VM = VSS VC1= 2.6 V VC1= 4.4 V, VC2= 4.05 V VC2= 4.4 V, VC1= 4.05 V VC2 = 3.3 V, VM = VSS VC = VSS, TA = 25_C VC1 = VC2 = 3.3 V, VDD = VM VDD − VC = 6.1 V, TA = 25_C VC1 = 4.05 V, VDD − VM = 10 V CD = 500 pF, TA = 25_C, See Figure 4 VC1 = 2.6 V, VM = VSS, CD = 500 pF TA = 25_C, See Figure 5 VC1 = VC2 = 4.4 V, VM = VDD VC1 = VC2 = 4.05 V, See Figure 3 VC1 = VC2 = 4.05 V, VM = VDD VC1 = VC2 = 4.4 V, CD = 500 pF CL = 500 pF, DCO to VSS, See Figure 1 VC1 = 2 V, VC2 = 2.4 V, See Figure 6 CL = 500 pF, DCO to VSS, See Figure 7 520 27 27 30 42 −2 60 2.1 2.1 9 9 2.2 2.2 15 15 −0.5 1.0 40 40 60 ms 60 300 100 2 40 1.1 mA mV mA ms V ms mA 4.15 4.1 4.1 4.15 4.1 4.1 4.2 4.15 4.15 4.2 4.15 4.15 4.18 4.12 4.12 4.18 4.12 4.12 4.28 4.22 4.22 4.28 4.22 4.22 4.32 4.32 4.22 4.22 4.25 4.25 4.20 4.20 4.25 4.27 4.27 4.25 4.27 4.27 4.30 4.32 4.32 4.30 4.32 4.32 4.25 4.30 4.25 4.25 4.30 4.25 4.35 4.40 4.35 4.35 4.40 4.35 20 VDD − VM = 8.6 V 6 10 10 2.3 2.3 30 30 mA V mV V Symbol Test Condition Unless Otherwise Specified TA = −25 to 85_C Mina Typb Maxa Unit VOC1 Cell Cell 1 B Suffix VOC2 Cell Cell 2 Over-Charge Detect Threshold (Rising) VOC1 Cell Cell 1 C Suffix VOC2 Cell Cell 2 VOC1 Cell Cell 1 D Suffix VOC2 Cell Cell 2 Over-Charge Threshold Difference Over-Charge Detect Threshold Hysteresisc Over-Discharge Detect Threshold (Falling) Cell Balancing Current Timer Charge Current Timer Discharge Current DL2 Time (Over-Charge) DL2 Time (Over-Discharge) External Short Circuit Sense Current Reset Threshold Center Tap, Average Bias Current Overcharge Load Detect Power-Down Charger Detect Threshold DCO Pulse Width Cell 1 Cell 2 Cell 1 Cell 2 Cell 1 Cell 2 VOC1 − VOC2 VOC_H1 VOC_H2 VODC1 VODC2 IBAL1 IBAL2 ITIMER(C) ITIMER(D) tDL2OC tDL2ODC IVMSHORT VRTH IVC tOCC VCHPD tPW Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Guaranteed by design, not subject to production test. Document Number: 70658 S-40135—Rev. F, 16-Feb-04 www.vishay.com 3 Si9730 Vishay Siliconix TIMING DIAGRAMS 200 mV 50% tr x 100 nS High DCO Waveform VSS tOCC 50% VM Waveform VSS FIGURE 1. OC Load Detect IS Input 50% VSS VDD DCO Waveform VSS tILIMIT 50% 60 mV tr x 100 nS VM Waveform (After Short is Removed) VDD VSS VRTH VDD VSS VRTH = VM − VSS at DCO Transition DCO Waveform FIGURE 2. Current-Limit Comparator Response Time FIGURE 3. Reset Threshold 4.4 V VC2 Waveform 4.0 V t30 C Waveform VSS 32 t DL20C + 30 t 30 1 31 2.6 V VC2 Waveform 2.0 V t30 C Waveform VSS 32 t DL20DC + 30 t 30 1 31 FIGURE 4. DL2 Time (Over-Charge) FIGURE 5. DL2 Time (Over-Discharge) VSS VM Waveform VCHPD + − VM Waveform VSS ^VRTH High DCO Waveform Low VCHPD = VSS − VM at DCO Transition DCO Waveform tpw VDD VSS FIGURE 6. Power-Down Charger Detect Threshold FIGURE 7. Load Detection in Overcharge Mode www.vishay.com 4 Document Number: 70658 S-40135—Rev. F, 16-Feb-04 Si9730 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) 100.0 DL2 Period (Over Charge) vs. Capacitance 25_C 100.0 DL2 Period (Over Discharge) vs. Capacitance 25_C −25_C t DL20DC− Time (s) t DL20C − Time (s) 10.0 TA = 85_C 10.0 TA = 85_C −25_C 1.0 1.0 0.1 0.01 0.1 CD - Capacitance (mF) 1 0.1 0.01 0.1 CD - Capacitance (mF) 1 Over Current Sense Voltage vs. Current Sense Time 120 100 V RTH − Threshold (Normalized) 80 60 40 20 0 20 40 60 VIS − VSS (mV) 80 100 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 −25 Reset Threshold vs. Temperature t ILIMIT ( m S) 0 25 50 75 100 Temperature (_C) 6.5 6.0 5.5 t OCC ( m s) 5.0 4.5 4.0 3.5 50 Load Detect Time vs. VM − VSS Overcharge Threshold vs. Opposing Cell Voltage 4.2050 OCC (V) Overcharge Threshold V 75 100 125 150 175 200 4.2025 4.2000 4.1975 4.1950 2.5 3.0 3.5 4.0 VM − VSS (mV) Opposing Cell Voltage (V) Document Number: 70658 S-40135—Rev. F, 16-Feb-04 www.vishay.com 5 Si9730 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) DCO Rise and Fall Times vs. Capacitance 1000.00 100.00 Time ( m s) 10.00 Rise 1.00 Fall TA = 85_C TA = −25_C 0.10 0.01 100 1000 DCO Capacitance (pF)) 10000 PIN CONFIGURATION SO-8 VM NC VDD CD 1 2 3 4 Top View 8 7 6 5 DCO VSS IS VC ORDERING INFORMATION Part Number Si9730ABY-T1 Si9730ABY-T1—E3 (Lead Free) Si9730BBY-T1 Si9730BBY-T1—E3 (Lead Free) Si9730CBY-T1 Si9730CBY-T1—E3 (Lead Free) Si9730DBY-T1 Si9730DBY-T1—E3 (Lead Free) VOC1/2 Typ. Temp Range 4.20 4 20 V 4.25 4 25 V −25_ to 85_C 25 85 4.22 4 22 V 4.32 4 32 V PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 Symbol VM NC VDD CD VC Is VSS DCO No Connection, do not connect this pin. Description Negative Battery Pack Terminal - connection for external negative terminal of the battery pack. Dual Cell Positive Terminal - connection for positive terminal of dual series connected LiI+ cells. Delay Capacitor Connection - an external capactior connected across CD and Vss allows additional charge time (DL2, see Detailed Description ) after a charge error has occured. Suggested capacitor values are shown in DL2 Period vs. Capacitance Curves. Dual Cell Center Tap Connection - monitors individual battery voltages for overcharge and overdischarge errors. Current Sense Comparator Input - monitors load current for short circuit conditions . If VILIMIT is exceeded, then DCO opens the low-side switch, disconnecting the cells. Dual Cell Negative Terminal - connection for negative terminal of dual series connected LiI+ cells. Low-side Switch Gate Driver Output - drives the gate of two external source connected n-channel MOSFETs. DCO swings from VOL to VDD. Document Number: 70658 S-40135—Rev. F, 16-Feb-04 www.vishay.com 6 Si9730 Vishay Siliconix DETAILED DESCRIPTION Overview The purpose of the Si9730 is to safely and reliably control the charging and discharging of a two-cell lithium-ion battery (carbon or coke chemistry). It provides protection against all possible fault conditions, including: D external short circuits D reversed charger D overcharged cell or cells D undervoltage D battery open center-tap (VOC ~ 4.2 V); and c) the center tap is connected to the VC pin. When a charger is present in these conditions, the switch will be on, charging the cells at the current limit of the charger. Normal Discharging The cells are in normal discharging conditions if a, b, and c above are satisfied, and if in addition d) the load current is less than the discharge current limit. With no charger present, the switch will be on, discharging the cells and powering the load. Overcharged Cell(s) Charging The most destructive condition that a LiI+ cell can experience is overcharging. If the cell becomes overcharged beyond its recommended limits, it can become permanently disabled. If one or both cells rise above the over-charge detect threshold (VOC1 and VOC2), and a charger is present, the Si9730 will open the switch (to prevent further charging) and begin bleeding off charge (15-mA typical) from the overcharged cell or cells. The details of this operation depend on the fact that the voltage level of lithium-ion batteries drops for a short time after charging ceases (due to momentary changes in battery chemistry, ESR, etc.). Because of this recovery, the Si9730 allows the battery to continue charging for a short time (the overcharge time, tDL2OC). This additional charge time only occurs if the overcharge condition persists for more than 8 msec (two periods of an internal 4msec oscillator). TDL2OC is determined by the capacitor attached to the CD pin, see Figure 8. Once the overcharge time has ended, the switch is opened, preventing the battery from further overcharging. Now, the Si9730 begins bleeding current off the overcharged cell or cells (IBAL1 and IBAL2), as long as a charger is present. Eventually, the cell(s) will return into their normal range, and charging will begin, starting the whole cycle over again. Overcharged Cell(s) Discharging If one or more cells is overcharged, and a load is connected, the switch is turned on, permitting the battery to power the load. Over-Discharged Cell(s) Discharging The cells are in normal charging conditions if a) both cells are above the Over-Discharge Detect Threshold (VODC ~ 2.2 V); b) both cells are under the Over-Charge Detect Threshold Document Number: 70658 S-40135—Rev. F, 16-Feb-04 General Concepts The Si9730 operates by connecting or disconnecting the negative terminal of the battery to the negative side of the load and/or charger (see Figure 8); that is, it does ground side switching. It is important to bear the distinction between these two “grounds” in mind in order to understand the operation of the Si9730. The switching is accomplished by controlling two “back-to-back” MOSFETs: having the two MOSFETs in this arrangement is mandatory to ensure that current cannot flow in either direction when the MOSFETs are off. To turn the switch on, the Si9730 applies a gate-source voltage to both MOSFETs (from the DCO pin) that is high with respect to the sources. The Si9730 DCO signal is referenced to the VM pin while the battery is being charged, and to the Vss pin while the battery is being discharged. The Si9730 causes the DCO to be referenced to the lower of the two voltages. This prevents the switch from turning on or off unintentionally. The Si9730 is designed to operate only with a current-limited lithium-ion battery charger. Specifically, the battery charger must have an open-circuit voltage that does not exceed the absolute maximum IC voltage, and it must have a limited short-circuit current that does not exceed the allowed charging current of the battery. The following descriptions cover all the common operational scenarios; additional information on unusual battery conditions can be found in the state transition table. Normal Charging Repeated over-discharging of LiI+ cells can cause irreversible reactions in the cells which lead to decreased cycle life. www.vishay.com 7 Si9730 Vishay Siliconix To avoid this, if one or both cells becomes over-discharged (VCELL < VODC) and no charger is present, the Si9730 opens the switch to prevent further discharging, and goes into a shutdown mode in which it draws minute power from the battery (IDD_UVL < 1 mA). IVMSHORT current causes the voltage on the VM pin to equal the voltage on the VDD pin while the short is present, or the voltage on the VM pin to equal the voltage on the VSS pin if the short is removed. If the short is not removed, IVMSHORT current will continue to flow until the battery voltage becomes overdischarged. Once the short is removed, the IC is allowed to turn the switch back on. The current limit threshold has a temperature coefficient of 0.18%/_C. This can partially compensate for a copper circuit board trace being used as the sense resistor. Over-Discharged Cell(s) Charging If one or both cells is over-discharged, and a charger is present, charging can begin, and so the Si9730 closes the switch. However, removal of the charger in this condition could potentially damage the battery if the removal is not recognized and the cells are discharged. Since the voltage drop across the switch is small, the Si9730 actually cycles the switch at a 7/8 duty cycle; during the 1/8 time when the switch is open, the IC checks that the charger is still present. Once both cells are back into the normal operating range, normal charging resumes. Open Center Tap An open center tap is a mechanical failure of the battery pack such that the Si9730’s VC pin is disconnected from the center point of the two-cell battery. If this connection is open, the IC opens the switch, as it cannot measure the cell voltages in this condition. The switch is left open until connection is re-established. If the battery is under-voltaged and the charger is present in this case, the battery is allowed to charge even with the center tap open. In this state, batteries are almost impossible to damage by 1/8 duty cycle charging. Once the battery voltage reaches the over-discharged voltage, the switch is turned off. Undervoltage Charging If for some reason the battery drops below about 3.7 V (VUVL), there is insufficient voltage for the Si9730 to properly monitor fault conditions. Of course, the switch is already open, since VUVL < VODC x 2. However, when a charger is detected, the Si9730 recovers and goes into an undervoltage mode. (A charger is detected if the VS pin is higher than the VM pin by at least VCHPD = 1.1 V, see Figure 6). In this undervoltage mode, the switch is on at a 1/8 duty cycle, to limit the power dissipation across the switch, and, again, to detect the continuing presence of the charger. Once the battery voltage is above VUVL, the charging continues in the over-discharged state. State Transition Table The number of different states of the Si9730 can seem overwhelming at first. This state transition table will help to organize thinking about the different operational conditions of the IC, by listing each possible transition from one condition to another. Reading the table is straightforward. There are two cells constituting the battery, one with its positive terminal connected to VDD and its negative terminal connected to VC, referred to as the high cell (see Figure 8); and one cell with its positive terminal connected to VC and its negative terminal connected to VSS, referred to as the low cell. Each cell can be in one of three voltages: D Over-discharge (ODC), where VCELL < VODC; D Normal Operation (NO), where VODC < VCELL < VOC; or D Overcharge (OC), where VOC < VCELL. Document Number: 70658 S-40135—Rev. F, 16-Feb-04 Output Short If too much current is drawn from the battery due to a load short, the switch must be opened quickly to prevent damage to the battery. The Si9730 monitors the load current by looking at the voltage across an external sense resistor (see Figure 8). If the voltage across the sense resistor exceeds VILIMIT ~ 28 mV, the switch is opened. The Si9730 leaves the switch open until the load is completely removed. Of course, the IC must have some way of detecting that the load has been removed. For this purpose, a small current (IVMSHORT) passes through the Si9730, from pin VM to pin VSS once the short is detected and the switch is turned off. The www.vishay.com 8 Si9730 Vishay Siliconix Additionally, the battery as a whole can be undervoltage (UV), where VBATTERY < VUVL. Note that this final condition is not necessarily (though normally) mutually exclusive with the other cell conditions: if one cell were at 0V, the other cell could be in NO, and the battery could still be in UV. The charger can be either present (ON) or not present (OFF); the “X” in the table means the condition is true regardless of the state of the charger. The load current can be either 0, normal (0 < ILOAD < IILIMIT) or a short (IILIMIT< ILOAD) where IILIMIT is set by VILIMIT/RSENSE; the “X” in the table refers to a load current that can be either 0 or normal. Finally, the switch can be either ON, OFF, or cycling at either 1/8 or 7/8 duty cycle, where the duty cycle refers to the portion of the period when the switch is on; the notation On−>On simply means that the switch does not change state, it remains on; the notation −>Off means that the switch turns off regardless of its previous state. STATE TRANSITION TABLE High-Cell Voltage NO NO−>OC NO NO−>OC NO OC NO OC NO OC NO NO−>ODC NO NO−>ODC NO ODC NO ODC UV NO−>ODC OC NO UV ODC NO ODC NO OC ODC ODC NO NO OC OC NO−>OC NO Low-Cell Voltage NO NO NO−>OC NO NO−>OC NO OC OC NO NO OC NO NO−>ODC NO NO−>ODC NO ODC ODC Charger On/Off Off>On Off Off Off Off Off−>On Off−>On Off−>On Off Off Off Off Off Off Off Off−>On Off−>On Off−>On Off−>On Off Off VShort Normal−>Short Normal−>Short 0 0 Normal Normal X X X X 0 0 X Center Tap−>Open Center Tap−>Open Center Tap−>Open Center Tap−>Open Center Tap−>Open Center Tap−>Open Switch State On−>On On−>Off On−>Off Cycles at very high duty cycle Cycles at very high duty cycle Off−>Off Off−>Off Off−>Off On−>Off On−>Off On−>Off On−>Off On−>Off On−>Off On−>Off Off−>Cycle at 7/8 duty cycle Off−>Cycle at 7/8 duty cycle Off−>Cycle at 7/8 duty cycle Off−>Cycle at 1/8 duty cycle Cycle−>Off Off Off Cycle at 1/8 duty cycle −.>Off −.>Off −.>Off −.>Off −.>Off Document Number: 70658 S-40135—Rev. F, 16-Feb-04 www.vishay.com 9 Si9730 Vishay Siliconix APPLICATION CIRCUIT Si9730 100 W CD C1 0.1 mF Undervoltage Lockout VDD 3 10 mF C 4 + Cell 1 VC1 Cell Balancing Network 100 W VC 5 A/D Converter OUT Control Logic Timer CDELAY Time Out CLK Load Cell 2 VC2 100 W VSS 7 Oscillator 1.2 VREF SOUT VSS Chgr. 8.4 V 1A Current Sense 14 MW C2 0.47 mF Filter IS RIS 47 kW DCO 6 Comparator ILIMIT 8 GS Gen. VM 1 VM Si9936DY FIGURE 8. Typical 2 -Cell Circuit General Considerations Figure 8 shows a typical application of the Si9730, controlling a 2-cell lithium-ion battery (carbon or coke chemistry). Specifics of the selection of MOSFETs, current sensing resistor, and output capacitor are detailed below. In addition, there are several typical features of this circuit to be observed. First, each connection from a cell to the IC has a 100-W resistor in series with it. The purpose of the resistor is to ensure that in the unlikely event of the IC shorting, the cells themselves will not see a short. The maximum size of this resistance is set by the current drain of the IC; for example, the VDD pin draws a maximum of 60 mA, which will drop V = 60 mA * 100 W = 6 mV www.vishay.com across the resistor. This drop constitutes an error in the measured cell voltage, and so the resistor must be small enough that the error voltage is acceptable. A second typical feature demonstrated in Figure 8 is the current sense filter formed by RIS and C2. This provides a noise filter, to prevent the Si9730 from opening the connection to the battery if there is noise on its current sense pin. It also causes a delay in the response of the IC to a genuine overcurrent, the amount of the delay being inversely proportional to the amount of overcurrent, since the Is pin senses a voltage. Increasing this filter’s time constant could be used to allow short-time surges of current out of the battery without compromising its ability to protect the battery. Document Number: 70658 S-40135—Rev. F, 16-Feb-04 10 Si9730 Vishay Siliconix Output Capacitor Depending on the MOSFET selected, the Si9730 can open the switch quite rapidly, in a matter of a few microseconds. However, the various monitoring operations take 10-100 times longer than this, and the basic period of the Si9730’s oscillator is 4 msec. In order to prevent false readings by the Si9730, it is necessary to attach a capacitor across the output of the battery charger/load (this is not in parallel with the battery, because of the switch). A 10-mF capacitor is recommended for this purpose; see Figure 8. For example, to get a 14-mW. resistor, we need length/width = 28; with a trace width of 0.01”, the length of the trace should be 0.28”. MOSFET Selection Two MOSFETs in series, with their sources and gates connected together, are used as the switch. This prevents current from flowing in either direction when the gate is low; if only one MOSFET were used, the body diode could conduct current in the opposing direction. LITTLE FOOT MOSFETs are recommended for this application, because of their size, performance and cost benefits. SO-8 and TSSOP-8 MOSFETs allow for space efficient designs with performance equal to or better than their DPAK and TO-220 predecessors. Further, their availability from multiple sources permits a cost effective solution. There are two important parameters to consider in MOSFET selection: gate threshold voltage; and on-resistance, which determines power dissipation. Even when the DCO pin of the Si9730 is low, the specification allows its value to be as high as 0.4 V. If this voltage were close to the gate threshold voltage, leakage current through the MOSFETs could be hundreds of microamps, which would result in the battery quickly becoming discharged. To ensure that leakage is minimized, n-channel MOSFETs with a minimum gate threshold voltage of 0.8 V should be chosen. On resistance of the MOSFETs needs to be selected to limit power dissipation into the MOSFETs’ package. For example, a dual MOSFET SO-8 package is rated at 2 W, and a dual MOSFET TSSOP-8 package is rated at 1 W (both at 25_C; if the ambient temperature is higher, the allowable power dissipation in these packages is less). For example, if the maximum current is 2 A, and a dual MOSFET SO-8 package is being used, the maximum on-resistance of the two MOSFETs in series must not exceed 1 W = (2 A)2 * RON or RON = 0.25 W; each MOSFET can be allotted half of this, RON = 125 mW. Account must also be taken of the fact that MOSFETs’ on-resistance is a function of temperature; a conservative approach would give a discount of 1/3, RON = 125 mW * (2/3) = 80 mW per MOSFET. A list of recommended MOSFETs, which Vishay Silicoix supplies, follows. www.vishay.com Selecting a Current Sense Resistor The current sense resistor should be selected based on the maximum current the battery can source or charge at; above this current, the Si9730 will open the switch, disconnecting the battery from its load or charger. Rsense = VILIMIT/IILIMIT  28 mV/IILIMIT Of course, the resistor must be rated to take the power dissipated in it as well: PRSENSE = IILIMIT* VILIMIT  28 mV * IILIMIT For example, suppose that the maximum current the battery will see is 1.8 A. Then, ILIMIT might be chosen to be 2 A. We would then select a resistor of RSENSE = 28 mV/2 A = 14 mW. The power dissipation in this resistor is PRSENSE = 28 mV * 2 A = 56 mW and so a 100mW surface mount resistor would be suitable. Another possibility is to use a thin copper trace as the sense resistor. The copper has a temperature coefficient of 0.39%/_C, but this is partially compensated for by the temperature coefficient of the current limit comparator in the Si9730, which is 0.18%/_C. A simple formula for selecting a trace to act as a current sensor is: length 1 oz. Copper width R + 0.5 mW Document Number: 70658 S-40135—Rev. F, 16-Feb-04 11 Si9730 Vishay Siliconix N-CHANNEL MOSFET SELECTION GUIDE Part Number Si4410DY Si4412DY Si6434DQ Si4936DY Si9936DY Si6954DQ rDS (on)(W) @ VGS = 10 V 0.0135 0.028 0.028 0.037 0.050 0.065 rDS(on)(W) @ VGS = 4.5 V 0.020 0.042 0.042 0.055 0.080 0.095 ID(A) 10 7 5.6 5.8 5 3.9 VGS(th) (V) 1.0 1.0 1.0 1.0 1.0 1.0 Config. Single Single Single Dual Dual Dual Package SO-8 SO-8 TSSOP-8 SO-8 SO-8 TSSOP-8 Recommended Application Current (A) @ 25_C 9 6.3 4.9 3.5 2.9 1.9 V+ 100 W Si9730 1 VM 2 NC 3 VDD 100 W 4 CD DCO 8 VSS 7 IS 6 VC 5 100 W 10 nF + 15 MW 47 kW 470 nF 100 mF Si9936 100 W 1 VM 2 NC Si9730 DCO 8 VSS 7 IS 6 VC 5 470 nF + 100 mF 3 VDD 100 W 4 CD 10 nF 100 W 47 kW 15 MW V− Si9936 FIGURE 9. www.vishay.com 4-Cell Battery Circuit Document Number: 70658 S-40135—Rev. F, 16-Feb-04 12 Si9730 Vishay Siliconix Four Cell Application Figure 9 shows a method for using the Si9730 in a 4-cell application. Basically, this is two complete 2-cell circuits stacked in series. Each half of the complete circuit monitors its own 2-cell portion of the battery, and opens its own MOSFET switch under any of the appropriate conditions. Observe that the total percent power loss in this circuit is identical to that in the 2-cell application; although there are now two sets of MOSFETs in series, there is also double the battery voltage, and so total efficiency is the same. One novel feature of this 4-cell circuit is the increase in the size of the bypass capacitors. Each half of the circuit retains its own output cap, to reduce noise seen by the circuit. Since the two halves interact with each other (when one opens its switch, the other one is also opened), there can be additional noise, which must be rejected for proper operation. The capacitors have been increased to 100 mF for this reason; remember that they must be rated to take the full maximum voltage rating of the charger, not half of it, since if one switch is closed and the other open, the charger (minus two cells’ voltage drop, which might be zero) is applied across the other capacitor. A second addition on this circuit is the (optional) two zeners, one each for each Si9730, placed from VDD to VM. These are necessary only if the charger voltage is higher than the 15-V absolute maximum of the IC plus two cells’ voltage drop. Just as with the capacitor, if one switch is open and the other closed, the IC will see this charger voltage, and must be protected. The power rating of the zener can be inferred by observing that the current through it is limited by the 100-W resistor. A tradeoff can be made here between the power rating of the zener, which can be decreased by increasing the resistor value, and the accuracy of the voltage measurement by the Si9730, which can be increased by decreasing the resistor value. Reset from Shutdown There are two specialized conditions that can place the Si9730 in shutdown mode. The first condition can occur when the circuit is first attached to a battery in the factory. When the IC comes up, it will be in the undervoltage shutdown mode. The Si9730 may also enter this mode when the ambient temperature drops and the battery is nearly in UV. When the temperature drops, the battery pack voltage will drop and the IC may enter the shutdown mode. In either case, the Si9730 must be reset by raising the VSS pin higher than the VM pin by VCPHD. Figure 10 shows a circuit that resets the circuit once it has entered the shutdown mode. The circuit works by initially connecting the 0.1-mF capacitor to the battery’s center tap and placing the switch in position #1. Although the MOSFETs are open, the 1-mW resistor is sufficient to allow the capacitor to charge up in about 300-400 msec. Once the capacitor is charged, the switch is placed in position #2, momentarily making VSS higher than VM, thus placing the Si9730 in the normal operating mode. The entire circuit provides a leakage of only a few microamps, which is much lower than the self discharge current of the LiIon battery. Si9730 1 VM 2 NC 3 VDD 4 CD DCO 8 #2 #1 SPDT VSS 7 IS 6 VC 5 15 MW 1 MW 0.1 mF FIGURE 10. Factory Startup Circuit Document Number: 70658 S-40135—Rev. F, 16-Feb-04 www.vishay.com 13