SUD15N15-95

SPICE Device Model SUD15N15-95 Vishay Siliconix N-Channel 150-V (D-S) 175° MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71756 05-Jun-04 www.vishay.com 1 SPICE Device Model SUD15N15-95 Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current b Symbol Test Conditions Simulated Data 2.6 71 0.069 0.115 0.139 0.080 0.89 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = 250 µA VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 15 A V A 0.077 Ω 0.081 0.90 V Drain-Source On-State Resistanceb rDS(on) VGS = 10 V, ID = 15 A, TJ = 125°C VGS = 10 V, ID = 15 A, TJ = 175°C VGS = 6 V, ID = 10 A Forward Voltageb VSD IS = 15 A, VGS = 0 V Dynamic a Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Chargec Gate-Drain Chargec Turn-On Delay Timec Rise Timec Turn-Off Delay Timec Fall Time c Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf trr IF = 15 A, di/dt = 100 A/µs VDD = 75 V, RL = 5 Ω ID ≅ 15 A, VGEN = 10 V, RG = 2.5 Ω VDS = 75 V, VGS = 10 V, ID = 15 A VGS = 0 V, VDS = 25 V, f = 1 MHz 897 126 73 21 5.5 7 12 19 36 41 48 900 115 70 20 5.5 7 8 35 17 30 55 ns nC pF Source-Drain Reverse Recovery Time Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. c. Independent of operating temperature. www.vishay.com 2 Document Number: 71756 05-Jun-04 SPICE Device Model SUD15N15-95 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71756 05-Jun-04 www.vishay.com 3