W3DG6430V-D2

White Electronic Designs W3DG6430V-D2 PRELIMINARY* 256MB - 32M x 64 BUFFERED SDRAM MODULE FEATURES Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply 168 pin DIMM JEDEC * This product is not fully qualified or characterized and is subject to change without notice. DESCRIPTION The W3DG6430V is a 32M x 64 synchronous DRAM module which consists of sixteen 32Mx4 SDRAM components in TSOP II package, three very high speed buffers for reduced input capacitance, and one 2K EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 168 pin DIMM multilayer FR4 Substrate. PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC NC VCC WE# DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0# DNU VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CLK0 VSS DNU CS2# DQM2 DQM3 DNU VCC NC NC NC NC VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC **SDA **SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC NC VCC CAS# DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 NC RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC VSS CKE0 NC DQM6 DQM7 NC VCC NC NC NC NC VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC PIN NAMES A0 – A11 BA0-1 DQ0-63 CLK0,CLK3 CKE0 CS0#-CS2# RAS# CAS# WE# DQM0-7 VCC VSS SDA SCL DNU NC SA0-SA2 Address input (Multiplexed) Select Bank Data Input/Output Clock input Clock Enable input Chip select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial data I/O Serial clock Do not use No Connect Address in EEPROM ** These pins should be NC in the system which does not support SPD. February 2002 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM W3DG6430V-D2 PRELIMINARY BA0, BA1, A0 - A11 CS0# CAS# RAS# WE# CKE0 A CS# DQ CAS# RAS# U1 W# CKE DQMB DQ0-3 DQMB0 A CS# A CS# DQ CAS# RAS# U9 W# CKE DQMB DQ32-35 DQMB4 A CS# DQ DQ4-7 CAS# RAS# U3 W# CKE DQMB A CS# DQMB0 A CS# DQ CAS# RAS# U11 W# CKE DQMB DQ36-39 DQMB4 DQ DQ8-11 CAS# RAS# U2 W# CKE DQMB DQMB1 DQ CAS# RAS# U10 W# CKE DQMB DQ40-43 DQMB5 A CS# DQ DQ12-15 CAS# RAS# U4 W# CKE DQMB CS2# A CS# DQ DQ16-19 DQMB1 DQ CAS# RAS# U12 W# CKE DQMB A CS# DQ CAS# RAS# U13 W# CKE DQMB A CS# DQ44-47 DQMB5 DQ48-51 CAS# RAS# U5 W# CKE DQMB DQMB2 A CS# DQMB6 A CS# DQ DQ20-23 CLOCK WIRING INPUT CK0 CK1 CK2 CK3 SDRAMS 4 SDRAMS 4 SDRAMS 4 SDRAMS 4 SDRAMS A CS# DQ CAS# RAS# U7 W# CKE DQMB DQMB2 A CS# DQ CAS# RAS# U15 W# CKE DQMB DQ52-55 DQMB6 DQ24-27 CAS# RAS# U6 W# CKE DQMB DQMB3 A CS# DQ CAS# RAS# U8 W# CKE DQMB DQ CAS# RAS# U14 W# CKE DQMB DQ56-59 DQMB7 A CS# DQ CAS# RAS# U16 W# CKE DQMB SERIAL PD SCL A0 A1 A2 SA0 SA1 SA2 SDA DQ28-31 DQ60-63 DQMB3 DQMB7 NOTE: A0-A11, BA0-BA1, WE, RAS, CAS, CS0, CS2, CKE0 are buffered, not registered. 10 ohm registors are in series with all DQ's. February 2002 Rev. 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50 W3DG6430V-D2 PRELIMINARY Units V V °C W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ 70°C Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 — -20 Typ 3.3 3.0 — — — — Max 3.6 VCC+0.3 0.8 — 0.4 20 Unit V V V V V A IOH= -2mA IOL= -2mA 1 Note Note: 1. Any input 0V ≤ VIN ≤ VCC Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE TA = 23°C, f = 1MHz, VCC = 3.3V, VREF=1.4V ± 200mV Parameter Input Capacitance (A0-A11) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CLK0,CLK2) Input Capacitance (CS0#,CS2#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 20 20 20 13 15 10 20 12 Unit pF pF pF pF pF pF pF pF February 2002 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs OPERATING CURRENT CHARACTERISTICS VCC = 3.3V, 0°C ≤ TA ≤ 70°C Parameters Symbol Conditions W3DG6430V-D2 PRELIMINARY Versions 100 Units mA Note 1 Operating Current (One bank active) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode ICC1 Burst Length = 1 tRC ≥ tRC(min) IOL = 0mA CKE ≤ VIL(max), tCC = 10ns CKE & CK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC =10ns Input signals are charged one time during 20 CKE ≥ VIH(min), CK ≤ VIL(max), tCC= ∞ Input signals are stable CKE ≥ VIL(max), tCC = 10ns CKE & CK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are charged one time during 20ns CKE ≥ VIH(min), CK ≤ VIL(max), tCC = ∞ input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CK tRC ≥ tRC(min) CKE ≤ 0.2V 1700 40 40 350 180 90 90 500 500 mA mA mA mA mA mA ICC2P ICC2PS ICC2N ICC2NS Active standby current in powerdown mode Active standby in current non powerdown mode ICC3P ICC3PS ICC3N ICC3NS Operating current (Burst mode) ICC4 mA mA 1 1700 Refresh current Self refresh current ICC5 ICC6 3300 40 mA mA 2 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VCC/VSSQ) February 2002 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS 133MHz component timing Paramater Access time from CLK Address hold time Address setup time CLK high level width CLK low level width Clock cycle time CKE hold time CKE setup time CS, RAS, CAS, WE, DQM hold time CS, RAS, CAS, WE, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) Active to Precharge command Active to Active command period Active to Read or Write delay Refresh period Auot refresh period Precharge command period Active bank a to Active bank b command Transition time Write recovery time Exit Self Refresh to Active command CL = 2 Symbol tAC tAH tAS tCH tCL tCK tCKH tCKS tCMH tCMS tDH tDS tHZ tLZ tOH tN tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR tXSR Min 0.8 1.5 2.5 2.5 7.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 1 3 1.8 37 60 15 66 15 14 0.3 1 CLK + 7ns 67 Max 5.4 W3DG6430V-D2 PRELIMINARY CL = 2 CL = 2 120,000 64 1.2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns Notes 1 2 3 4 5 6 7 Notes: 1. The clock frequency must remain constant ( stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including WR and Precharge commands). CKE may be used to reduce the data rate. 2. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 3. Paramater guaranteed by design 4. AC characteristics assume tT = 1ns 5. Auto precharge mode only) The precharge timing budget ( tRP) begins 7ns after the first clock delay, after the last Write is executed. 6. Precharge mode only. 7. CLK must be toggled a minimum of two times during this period. MODULE AC CHARACTERISTIC Address hold time Address setup time CS, RAS, CAS, WE, DQM hold time CS, RAS, CAS, WE, DQM setup time February 2002 Rev. 0 Symbol AH AS CMH CMS 5 Min 0 4.5 0 4.5 Max Units ns ns ns ns Notes White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION Part Number W3DG6430V10D2 Speed 100MHz CAS Latency CL=2 W3DG6430V-D2 PRELIMINARY PACKAGE DIMENSIONS 0.170 MAX. 5.250 0.125 (2X) 0.157 (2X) 1.500 MAX. 0.700 0.000 0.143 0.349 0.000 0.575 2.275 4.550 0.157 MIN. 0.250 2.150 0.050 ± 0.004 0.450 0.250 1.450 ALL DIMENSIONS ARE IN INCHES February 2002 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com