W19B320ATB

W19B320AT/B Data Sheet 4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 4 FEATURES ................................................................................................................................. 4 PIN CONFIGURATIONS ............................................................................................................ 5 BLOCK DIAGRAM ...................................................................................................................... 6 PIN DESCRIPTION..................................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................... 7 6.1 Device Bus Operation..................................................................................................... 7 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 Word/Byte Configuration .................................................................................................. 7 Reading Array Data .......................................................................................................... 7 Writing Commands/Command Sequences....................................................................... 7 Simultaneous Read/Write Operations with Zero Latency ................................................. 8 Standby Mode .................................................................................................................. 8 Automatic Sleep Mode ..................................................................................................... 8 #RESET: Hardware Reset Pin.......................................................................................... 9 Output Disable Mode........................................................................................................ 9 Autoselect Mode............................................................................................................... 9 Sector/Sector Block Protection and Unprotection........................................................... 9 Write Protect (#WP) ..................................................................................................... 10 Temporary Sector Unprotect ........................................................................................ 10 Security Sector Flash Memory Region ......................................................................... 10 Hardware Data Protection ............................................................................................ 11 Reading Array Data ........................................................................................................ 12 Reset Command............................................................................................................. 12 AUTOSELECT Command Sequence ............................................................................. 13 Byte/Word Program Command Sequence...................................................................... 13 Unlock Bypass Command Sequence ............................................................................. 14 Chip Erase Command Sequence ................................................................................... 14 Sector Erase Command Sequence ................................................................................ 14 Erase Suspend/Erase Resume Commands ................................................................... 15 DQ7: #Data Polling......................................................................................................... 16 RY/#BY: Ready/#Busy ................................................................................................... 16 DQ6: Toggle Bit I............................................................................................................ 16 6.2 Command Definitions ................................................................................................... 12 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.3 Write Operation Status ................................................................................................. 16 6.3.1 6.3.2 6.3.3 -1- Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 6.3.4 6.3.5 6.3.6 6.3.7 DQ2: Toggle Bit II........................................................................................................... 17 Reading Toggle Bits DQ6/DQ2 ...................................................................................... 17 DQ5: Exceeded Timing Limits ........................................................................................ 17 DQ3: Sector Erase Timer ............................................................................................... 18 7. TABLE OF OPERATION MODES ............................................................................................ 19 7.1 7.2 7.3 7.4 7.5 Device Bus Operations ................................................................................................. 19 AUTOSELECT Codes (High Voltage Method) ............................................................. 19 Sector Address Table (Top Boot Block) ....................................................................... 20 Sector Address Table (Bottom Boot Block) .................................................................. 22 CFI Query Identification String...................................................................................... 26 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 System Interface String .................................................................................................. 26 Device Geometry Definition ............................................................................................ 27 Primary Vendor-Specific Extended Query ...................................................................... 28 Command Definitions ..................................................................................................... 29 Write Operation Status ................................................................................................... 30 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8. 8.1 8.2 8.3 8.4 Temporary Sector Unprotect Algorithm ........................................................................ 31 In-System Sector Protect/Unprotect Algorithms........................................................... 32 Security Sector Protect Verify....................................................................................... 33 Program Algorithm........................................................................................................ 33 Erase Algorithm ............................................................................................................ 34 Data Polling Algorithm .................................................................................................. 34 Toggle Bit Algorithm ..................................................................................................... 35 Absolute Maximum Ratings .......................................................................................... 36 Operating Ranges......................................................................................................... 36 DC Characteristics........................................................................................................ 37 8.3.1 8.4.1 8.4.2 CMOS Compatible.......................................................................................................... 37 Test Condition ................................................................................................................ 38 AC Test Load and Waveforms ....................................................................................... 38 ELECTRICAL CHARACTERISTICS......................................................................................... 36 AC Characteristics ........................................................................................................ 38 8.5 8.6 8.7 8.8 8.9 8.10 9. 9.1 Read-Only Operations .................................................................................................. 39 Hardware Reset (#RESET) .......................................................................................... 39 Word/Byte Configuration (#BYTE)................................................................................ 39 Erase and Program Operation...................................................................................... 40 Temporary Sector Unprotect ........................................................................................ 40 Alternate #CE Controlled Erase and Program Operations........................................... 41 AC Read Waveform...................................................................................................... 42 -2- TIMING WAVEFORMS ............................................................................................................. 42 W19B320AT/B 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 10. 11. 12. 13. Reset Waveform ........................................................................................................... 42 #BYTE Waveform for Read Operation ......................................................................... 43 #BYTE Waveform for Write Operation ......................................................................... 43 Programming Waveform............................................................................................... 44 Accelerated Programming Waveform........................................................................... 44 Chip/Sector Erase Waveform ....................................................................................... 45 Back-to back Read/Write Cycle Waveform .................................................................. 45 #Data Polling Waveform (During Embedded Algorithms) ............................................ 46 Toggle Bit Waveform (During Embedded Algorithms) ................................................. 46 DQ 2 vs. DQ6 Waveform .............................................................................................. 47 Temporary Sector Unprotect Timing Diagram.............................................................. 47 Sector/Sector Block Protect and Unprotect Timing Diagram ....................................... 47 Alternate #CE Controlled Write (Erase/Program) Operation Timing............................ 48 LATCHUP CHARACTERISTICS .............................................................................................. 49 CAPACITANCE......................................................................................................................... 49 ORDERING INFORMATION .................................................................................................... 50 PACKAGE DIMENSIONS ......................................................................................................... 51 13.1 13.2 TFBGA48ball (6X8 mm^2, Ø=0.40mm)........................................................................ 51 48-Pin Standard Thin Small Outline Package .............................................................. 52 14. VERSION HISTORY ................................................................................................................. 53 -3- Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 1. GENERAL DESCRIPTION The W19B320AT/B is a 32Mbit, 2.7~3.6-volt flexible bank CMOS flash memory organized as 4M x 8 or 2M × 16 bits. The word-wide (× 16) data appears on DQ15-DQ0, and byte-wide (x 8) data appears on DQ7-DQ0. The device can be programmed and erased in-system with a standard 3.0-volt power supply. A 12-volt VPP is not required. The unique cell architecture of the W19B320AT/B results in fast program/erase operations with extremely low current consumption (compared to other comparable 3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers. 2. FEATURES Performance • 2.7~3.6-volt write (program and erase) operations • Fast write operation − Sector erases time: 0.4 Sec (typical) − Chip erases time: 49 Sec (typical) − Byte programming time: 5 μs (typical) • Read access time: 70 ns • Typical program/erase cycles: − 100K • Twenty-year data retention • Ultra low power consumption − Active current (Read): 10 mA (typical) − Active current (Read while Erase/Program): 21 mA (typical) − Standby current: 0.2 μA (typical) Architecture • Flexible Bank architectures − Consist of four banks that customer can group the bank size as they needed − Bank 1: 4M; Bank 2: 12M; Bank 3: 12M; Bank 4: 4M • Security Sector Size: 256 Bytes − The Security Sector is an OTP; once the sector is programmed, it cannot be erased • Simultaneous Read/write operation − Data can be continuously read from one bank while processing erase/program functions in other bank with zero latency • JEDEC standard byte-wide and word-wide pinouts • Manufactured on WinStack 0.18μm process technology • Available packages: 48-pin TSOP and 48-ball TFBGA (6x8mm) Software Features • Compatible with common Flash Memory Interface (CFI) specification − Flash device parameters stored directly on the device − Allows software driver to identify and use a variety of different current and future Flash products • Erase Suspend/Erase Resume − Suspends erase operations to allow programming in same bank • End of program detection − Software method: Toggle bit/Data polling • Unlock Bypass Program command − Reduces overall programming time when issuing multiple program command sequences Hardware Features • Ready/#Busy output (RY/#BY) − Detect program or erase cycle completion • Hardware reset pin (#RESET) − Reset the internal state machine to the read mode -4- W19B320AT/B • #WP/ACC input pin − Write protect (#WP) function allows protection of two outermost boot sectors, regardless of sector protection status − Acceleration (ACC) function accelerates program timing • Sector Protection − Sectors can be locked in-system or via programmer − Temporary Sector Unprotect allows changing data in protected sectors in-system 3. PIN CONFIGURATIONS (Top View, Balls Face Down) A6 A13 48-Ball TFBGA C6 A14 B6 A12 D6 A15 E6 A16 F6 #BYTE G6 DQ15/A-1 H6 Vss A5 A9 B5 A8 C5 A10 D5 A11 E5 DQ7 F5 DQ14 G5 DQ13 H5 DQ6 A4 #WE B4 #RESET C4 NC D4 A19 E4 DQ5 F4 DQ12 G4 V DD H4 DQ4 A3 RY/#BY B3 #WP/ACC C3 A18 D3 A20 E3 DQ2 F3 DQ10 G3 DQ11 H3 DQ3 A2 A7 B2 A17 C2 A6 D2 A5 E2 DQ0 F2 DQ8 G2 DQ9 H2 DQ1 A1 A3 B1 A4 C1 A2 D1 A1 E1 A0 F1 #CE G1 #OE H1 Vss A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 #WE #RESET NC #WP/ACC RY/#BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 48-pin TSOP 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 #BYTE Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V DD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 #OE Vss #CE A0 -5- Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 4. BLOCK DIAGRAM VDD VSS #CE #OE #WE #WP/ACC #BYTE #RESET DQ15/A-1 A0 . . . A20 DECODER CONTROL OUTPUT BUFFER DQ0 . . DQ15/A-1 4 12 12 4 5. PIN DESCRIPTION SYMBOL PIN NAME A0−A20 DQ0−DQ14 DQ15/A-1 #CE #OE #WE #WP/ACC #BYTE #RESET RY/#BY VDD VSS NC Address Inputs Data Inputs/Outputs Word mode Byte mode Chip Enable Output Enable Write Enable Hardware Write Protect/ Acceleration Pin Byte Enable Input Hardware Reset Ready/Busy Status Power Supply Ground No Connection DQ15 is Data Inputs/Outputs A-1 is Address input -6- W19B320AT/B 6. FUNCTIONAL DESCRIPTION 6.1 Device Bus Operation 6.1.1 Word/Byte Configuration The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration. When the #BYTE pin is ‘1’, the device is in word configuration; DQ0 -DQ15 are active and controlled by #CE and #OE. When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. 6.1.2 Reading Array Data To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power control and used to select the device. #OE is the output control and gates array data to the output pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in words or bytes. The internal state machine is set for reading array data when device power-up, or after hardware reset. This ensures that no excess modification of the memory content occurs during the power transition. In this mode there is no command necessary to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are changed. 6.1.3 Writing Commands/Command Sequences In writhing a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH. For program operations, the #BYTE pin determines the device accepts program data whether in bytes or in words. Refer to “Word/Byte Configuration” for more information. The Unlock Bypass mode of device is to facilitate a faster programming. When a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to "Word/Byte Configuration” section for details on programming data to the device using both standard and Unlock Bypass command sequences. The erase operation can erase a sector, multiple sectors, even the entire device. The device address space is divided into four banks: Bank 1and Bank 4 contains the boot/parameter sectors; while Bank 2 and Bank 3 contain the larger sectors of uniform size. The “bank address” is the address bits required to solely select a bank; while the “sector address” is the address bits required to solely select a sector. -7- Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B Accelerated Program Operation The device provides accelerated program operations through the ACC function. This is one of two functions provided by the #WP/ACC pin. This function is primarily intended to allow a faster manufacturing throughput in the factory. If #WP/ACC pin is set at VHH, the device automatically enters into the Unlock Bypass mode. Then the device will temporarily unprotect any protected sectors, and uses the higher voltage on this pin to reduce the time required for program operations. The system would use a two-cycle program command sequence required by the Unlock Bypass mode. When VHH is removed from the #WP/ACC pin, the device is back to a normal operation. Please note that the #WP/ACC pin can not be at VHH for operations except accelerated programming; otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left floating; otherwise, an unconnected inconsistent behavior will occur. AUTOSELECT Functions When the system writes the AUTOSELECT command sequence, the device enters the AUTOSELECT mode. The system can then read AUTOSELECT codes from the internal register (which is separate from the memory array) on DQ0 –DQ7. The standard read cycle timings are applied in this mode. Please refer to the AUTOSELECT Mode and AUTOSELECT Command Sequence sections for more information. 6.1.4 Simultaneous Read/Write Operations with Zero Latency This device is capable of simultaneously reading data from one bank of memory and programming/ erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). 6.1.5 Standby Mode When the system is not reading or writing to the device, the device will be in a standby mode. In this mode, current consumption is greatly reduced, and the outputs are in the high impedance state, independent from the #OE input. When the #CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS standby mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are held at VIH, but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. When the device is deselected during erasing or programming, the device initiates active current until the operation is completed. 6.1.6 Automatic Sleep Mode The automatic sleep mode minimizes device's energy consumption. When addresses remain stable for tACC + 30ns, the device will enable this mode automatically. The automatic sleep mode is independent from the #CE, #WE, and #OE control signals. Standard address access timings provide new data when addresses are changed. In sleep mode, output data is latched and always available to the system. -8- W19B320AT/B 6.1.7 #RESET: Hardware Reset Pin The #RESET pin provides a hardware method to reset the device to reading array data. When the #RESET pin is set to low for at least a period of tRP, the device will immediately terminate every operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data mode. To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to accept another command sequence. Current is reduced for the duration of the #RESET pulse. When #RESET is held at VSS ± 0.3V, the device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within VSS ± 0.3V, the standby current will be greater. The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the device, enabling the system to read the boot-up firmware from the device. If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until the internal reset operation is complete. If #RESET is asserted when a program or erase operation is not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH. 6.1.8 Output Disable Mode When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high impedance state. 6.1.9 Autoselect Mode The AUTOSELECT mode offers manufacturer and device identification, as well as sector protection verification, through identifier codes output on DQ0-DQ7. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the AUTOSELECT codes can also be accessed in-system through the command register. When using programming equipment, the AUTOSELECT mode requires VID (8.5V to 12.5V) on address pins A9. Address pins A6, A1, and A0 must be as shown in table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ0-DQ7. 6.1.10 Sector/Sector Block Protection and Unprotection The hardware sector protection feature disables both program and erasure operations in any sectors. The hardware sector Unprotection feature re-enables both program and erasure operations in previously protected sectors. Sector Protection/Unprotection can be implemented through two methods. The primary method requires VID on the #RESET pin, and can be implemented either in-system or through programming equipment. This method uses standard microprocessor bus cycle timing. The alternate method intended only for programming equipment requires VID on address pin A9 and #OE. It is possible to determine whether a sector is protected or unprotected. See the Application Note for detail information. -9- Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 6.1.11 Write Protect (#WP) The Write Protect function provides a hardware method to protect the certain boot sectors without using VID. This function is one of two features provided by the #WP/ACC pin. When the #WP/ACC pin is set at VIL, the device disables program and erase functions in the two outermost 8 Kbytes boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection.” The two outermost 8 Kbytes boot sectors are the two sectors containing either the lowest addresses in a bottom-boot-configured device or the highest addresses in a top-boot-configured device. When the #WP/ACC pin is set at VIH, the device reverts to the two outermost 8 Kbytes boot sectors were last set either to be protected or unprotected. That is, sector Protection or Unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Please note that the #WP/ACC pin must not be left floating or unconnected; otherwise, the inconsistent behavior of the device may occur. 6.1.12 Temporary Sector Unprotect This feature allows temporary Unprotection of previously protected sectors to change data in-system. When the #RESET pin is set to VID, the Sector Unprotect mode is activated. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. What if VID is removed from the #RESET pin, all the previously protected sectors are protected again. 6.1.13 Security Sector Flash Memory Region The Security Sector feature provides an OTP memory region that enables permanent device identification through an Electronic Serial Number (ESN). The Security Sector uses a Security Sector Indicator Bit (DQ7) to indicate whether the Security Sector is locked or not when shipped from the factory. The DQ7 is permanently set when it is in the factory and cannot be changed, which prevents copying of a factory locked part. This ensures the security of the ESN when the product is shipped to the field. This issue should be considered during system design. Winbond offers the device with the Security Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Security Sector Indicator Bit permanently set to “1” The customer-lockable version is shipped with the Security Sector unprotected, which allowing customers to utilize the sector in any ways they choose. The customer-lockable version has the Security Sector Indicator Bit permanently set to “0.” Thus, the Security Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the Security Sector through a command sequence (see “Enter Security Sector/Exit Security Sector Command Sequence”). After the system has written the Enter Security Sector command sequence, it may read the Security Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Security Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. Factory Locked: Security Sector Programmed and Protected At the Factory The device Security Sector is protected when it is shipped from the factory, and it cannot be modified in any way. The device is available to be preprogrammed by one of the following: • • • A random, secure ESN only Customer code through the supplier's service Both a random, secure ESN and customer code through supplier's service. - 10 - W19B320AT/B In devices with an ESN, the Bottom Boot device will be with the 16-byte ESN in the lowest addressable memory area at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the highest 8 Kbytes boot sector at addresses 1FF000h–1FF007h in word mode (or addresses 3FE000h– 3FE00Fh in byte mode). Customers may choose have their code programmed by Winbond. Winbond can program the customer’s code, with or without the random ESN. The devices are then shipped with the Security Sector permanently locked. Customer Lockable: Security Sector NOT Programmed or Protected At the Factory If the security feature is not necessary, the Security Sector can be seen as an additional OTP memory space. When in system design, this issue should be considered. The Security Sector can be read, programmed; but cannot be erased. Please note that when programming the Security Sector, the accelerated programming (ACC) and unlock bypass functions are not available. The Security Sector area can be protected using one of the following procedures: • • Write the three-cycle Enter Security Sector Region command sequence, and then follow the in-system sector protect algorithm, except that #RESET may be at either V IH or VID. This allows in-system protection of the Security Sector without raising any device pin to a high voltage. Please note that this method is only suitable for the Security Sector. To verify the protect/unprotect status of the Security Sector; follow the algorithm show in Security Sector Protect Verify. The Security Sector protection must be used with caution, since there is no procedure available for unprotect the Security Sector area and none of the bits in the Security Sector memory space can be modified in any ways. 6.1.14 Hardware Data Protection The command sequence requirements of unlock cycles for programming or erasing provides data protection against negligent writes. In addition, the following hardware data protection measures prevent inadvertent erasure or programming, which might be caused by spurious system level signals during VDD power-up and power-down transitions, or from system noise. Write Pulse “Glitch” Protection Noise pulses, which is less than 5 ns (typical) on #OE, #CE or #WE, do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE must be a logical zero while #OE is a logical one to initiate a write cycle. Power-Up Write Inhibit During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up. - 11 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 6.2 Command Definitions The device operation can be initiated by writing specific address and data commands or sequences into the command register. The device will be reset to reading array data when writing incorrect address and data values or writing them in the improper sequence. The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing waveforms. 6.2.1 Reading Array Data After device power-up, it is automatically set to reading array data. There is no commands are required to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, each bank is ready to read array data. After the device accepts an Erase Suspend command, the corresponding bank enters the erasesuspend-read mode. After it the system can read data from any non-erase-suspended sector within the same bank. And then, after completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. Please refer to Erase Suspend/Erase Resume Commands section for detail information. The system must initiate the reset command to return a bank to read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or the bank is in the AUTOSELECT mode. See Reset Command section and Requirements for Reading Array Data in the Device Bus Operations section for more information. 6.2.2 Reset Command The banks will be to the read or erase-suspend-read mode when writing the reset command. For this command, the address bits are Don’t Care. The reset command may be written between the sequential cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank, to which the system was writing to the read mode. If the program command sequence is written to a bank, in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. When programming begins, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an AUTOSELECT command sequence. When in the AUTOSELECT mode, the reset command must be written to return to the read mode. If a bank entered into the AUTOSELECT mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). - 12 - W19B320AT/B 6.2.3 AUTOSELECT Command Sequence The AUTOSELECT command sequence provides the host system to access the manufacturer and device codes, and determine whether a sector is protected or not. This is an alternative method, which is intended for PROM programmers and requires VID on address pin A9. The AUTOSELECT command sequence may be written to an address within a bank that is either in the read or erasesuspend-read mode. When the device is actively programming or erasing in the other bank, the AUTOSELECT command may not be written. The first writing two unlock cycles initiate the AUTOSELECT command sequence. This is followed by a third write cycle that contains the bank address and the AUTOSELECT command. The bank then enters into the AUTOSELECT mode. The system may read at any address within the same bank without initiating another AUTOSELECT command sequence: • • • A read cycle at address (BA) XX00h (where BA is the bank address) returns the manufacturer code. A read cycle at address (BA) XX01h in word mode (or (BA) XX02h in byte mode) returns the device code. A read cycle to an address containing a sector address (SA) within the same bank, and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected or 00h if it is unprotected. To return to read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend), the system must write the reset command. Enter Security Sector/Exit Security Sector Command Sequence The Security Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Security Sector region by issuing the three-cycle Enter Security Sector command sequence. The device continues to access the Security Sector region until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security Sector command sequence returns the device to normal operation. See “Security Sector Flash Memory Region” for further information. 6.2.4 Byte/Word Program Command Sequence The device can be programmed either by word or byte, which depending on the state of the #BYTE pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program setup command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Once the Embedded Program algorithm is complete, the bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information. Any commands written to the device during the Embedded Program Algorithm are ignored. Please note that a hardware reset will immediately stop the program operation. The program command sequence should be reinitiated when the bank has returned to the read mode, in order to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to “1.” If trying to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate that the operation is successful. However, a succeeding read will show that the data is still “0.” Only erase operations can change “0” to “1.” - 13 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 6.2.5 Unlock Bypass Command Sequence The unlock bypass feature provides the system to program bytes or words to a bank which is faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass command, 20h, is followed. Then, the bank enters into the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. In the same manner, additional data is programmed. This mode dispenses with the initial two unlock cycles which required in the standard program command sequence, resulting in faster total programming time. All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The system must issue the two-cycle unlock bypass reset command sequence to exit the unlock bypass mode. The first cycle must contain the bank address and the data 90h. The second cycle needs to contain the data 00h. Then, the bank returns to the read mode. The device offers accelerated program operations by the #WP/ACC pin. When the VHH is set at the #WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle Unlock Bypass program command sequence may be written. To accelerate the operation, the device must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at VHH in any operation other than accelerated programming; otherwise the device may be damaged. In addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent behavior may occur. 6.2.6 Chip Erase Command Sequence Chip erase is a six-bus cycle operation. Writing two unlock cycles initiate the chip erase command sequence, which is followed by a set-up command. After chip erase command, two additional unlock write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations is not required in system. As the Embedded Erase algorithm is complete, the bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation will be ignored. However, a hardware reset shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip erase command sequence should be reinitiated when that bank has returned to reading array data. 6.2.7 Sector Erase Command Sequence Sector erase is a six-bus cycle operation. Writing two unlock cycles initiate the sector erase command sequence, which is followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. The device does not require the system to preprogram before erase. Before electrical erase, the Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern. Any controls or timings during these operations are not required in system. A sector erase time-out of 50 μs occurs after the command sequence is written. Additional sector addresses and sector erase commands may be written during the time-out period. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all - 14 - W19B320AT/B sectors. The time between these additional cycles must be less than 50 μs; otherwise, erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final #WE pulse in the command sequence. As the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Please note that when the Embedded Erase operation is in progress, the system can read data from the non-erasing bank at the same time. By reading DQ7, DQ6, DQ2, or RY/#BY in the erasing bank, the system can determine the status of the erase operation. Please refer to the Write Operation Status section for information on these status bits. When the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. However, a hardware reset shall terminate the erase operation immediately. If this occurs, to ensure data integrity, the sector erase command sequence should be reinitiated once the bank has returned to reading array data. 6.2.8 Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. When writing this command, the bank address is required. This command is valid only during the sector erase operation, which includes the 50 μs time-out period during the sector erase command sequence. If written during the chip erase operation or Embedded Program algorithm, the Erase Suspend command is ignored. As the Erase Suspend command is written during the sector erase operation, a maximum of 20 μs is required to suspend the erase operation. However, while the Erase Suspend command is written during the sector erase time-out, the device shall terminate the time-out period and suspends the erase operation immediately. The bank enters into an erase-suspend-read mode after the erase operation has been suspended. The system can read data from, or program data to, any sector not selected for erasure. (In device “erase suspends” all sectors are selected for erasure.) The “reading at any address within erasesuspended sectors produces status” information is on DQ0-DQ7. The system can use DQ7, or DQ6 and DQ2 together, to determine whether a sector is actively erasing or is erase-suspended. Please refer to the Write Operation Status section for detail information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. Using the DQ7 or DQ6 status bits, the system can determine the status of the program operation, just as in the standard Byte Program operation. Please refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the AUTOSELECT command sequence also can be issued. Please refer to the AUTOSELECT Mode and AUTOSELECT Command Sequence sections for details. The Erase Resume command must be written to resume the sector erase operation. When writing this command, the bank address of the erase-suspended bank is required. Further writes of the Resume command are ignored. After the chip has resumed erasing, another Erase Suspend command can be written. - 15 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 6.3 Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been completed. 6.3.1 DQ7: #Data Polling The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed, or whether or not a bank is in Erase Suspend. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. Once the Embedded Program algorithm has completed that the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1μs, and then that bank returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase algorithm has completed, or when the bank enters the Erase Suspend mode, #Data Polling produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, #Data Polling on DQ7 is active for about 100 μs, and then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will appear on successive read cycles. 6.3.2 RY/#BY: Ready/#Busy The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) When the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. 6.3.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. - 16 - W19B320AT/B During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the operation has completed, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for about 100 μs, and then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors which are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. While if the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see DQ7: #Data Polling). If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program command sequence is written, and then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling when the Embedded Program algorithm is complete. Please also refer to DQ2: Toggle Bit II. 6.3.4 DQ2: Toggle Bit II When used with DQ6, the “Toggle Bit II” on DQ2 indicates whether a particular sector is actively erasing (i.e., the Embedded Erase algorithm is in progress), or the sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final #WE pulse in the command sequence. DQ2 toggles as the system reads at addresses within those sectors that have been selected for erasure. (The system may use either #OE or #CE to control the read cycles.) But DQ2 cannot distinguish that whether the sector is actively erasing or is erase-suspended. By comparison, DQ6 indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Therefore, both status bits are required for sector and mode information. 6.3.5 Reading Toggle Bits DQ6/DQ2 Whenever the system initially starts to read toggle bit status, it must read DQ0-DQ7 at least twice in a row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the toggle bit after the first read. While after the second read, the system would compare the new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erasure operation. The system can read array data on DQ0-DQ7 on the following read cycle. However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erasure operation. If it is still toggling, the device did not complete the operation, and the system must write the reset command to return to reading array data. Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation. 6.3.6 DQ5: Exceeded Timing Limits Publication Release Date: December 27, 2005 Revision A4 - 17 - W19B320AT/B DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed. The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). 6.3.7 DQ3: Sector Erase Timer After writing a sector erasure command sequence, the system may read DQ3 to determine whether erasure has begun or not. (The sector erase timer does not apply to the chip erase command.) The entire time-out applies after each additional sector erasure command if additional sectors are selected for erasure. Once the timeout period has completed, DQ3 switches from “0” to “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 μs, the system need not monitor, DQ3 does not need to be monitored. Please also refer to Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (#Data Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. The system software should check the status of DQ3 before and following each subsequent sector erase command to ensure the command has been accepted. If DQ3 is high on the second status check, the last command might not have been accepted. - 18 - W19B320AT/B 7. TABLE OF OPERATION MODES 7.1 Device Bus Operations MODE Read Write Standby Output Disable Reset Sector Protect Sector Unprotect Temporary Sector Unprotect #CE L L VDD ±0.3V L X L L X #OE L H X H X H H X #WE H L X H X L L X #RESET H H VDD ±0.3V H L VID VID VID #WP/ACC ADDRESSES DQ0-DQ7 L/H (Note2) H L/H L/H L/H (Note2) (Note2) AIN AIN X X X SA, A6=L, A1=H, A0=L SA, A6=H, A1=H, A0=L AIN DOUT DIN High-Z High-Z High-Z DIN DIN DIN DQ8-DQ15 #BYTE=VIH DOUT DIN High-Z High-Z High-Z X X DIN #BYTE =VIL DQ8-DQ14 =High-Z, DQ15=A-1 High-Z High-Z High-Z X X High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 ~ 12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out. Notes: 1. 2. Addresses are A20:A0 in word mode (#BYTE = VIH), A20: A-1 in byte mode (#BYTE = VIL). If #WP/ACC = VIL, the two outermost boot sectors remain protected. If #WP/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotect ion”. If #WP/ACC = VHH, all sectors will be unprotected. 7.2 AUTOSELECT Codes (High Voltage Method) DESCRIPTION A20 A11 #CE #OE #WE TO TO A12 A10 A9 A8 TO A7 A6 A5 TO A4 A3 A2 A1 A0 DQ8 TO DQ15 #BYTE #BYTE = VIH = VIL DDh 22h 22h 22h X X X X X X DQ7 TO DQ0 Manufacturer ID: Winbond Device ID: VIL VIL VIL VIL VIL VIL VIH VIH VIH VIH VIH BA BA BA BA SA X X X X X VID VID VID VID VID X X X X X VIL VIL VIL VIL VIL X X X X X X VIL VIH VIH X X VIL VIH VIH VIL VIL VIL VIH VIH VIH VIL VIH VIL VIH VIL DAh 7Eh 0Ah 01h(Top) 00h(Bottom) 01h (protected) 00h (unprotected) 82h (factory locked) 02h (not factory locked) Read Cycle1 VIL Read Cycle2 VIL Read Cycle3 VIL Sector Protection Verification VIL Security Indicator Bit (DQ7) VIL VIL VIH BA X VID X VIL X X VIL VIH VIH X X Legend: BA= Bank Address, SA= Sector Address, X= Don't Care. - 19 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 7.3 Sector Address Table (Top Boot Block) BANK SECTOR SA0 SA1 SA2 Bank 4 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank 3 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Bank 2 SA35 SA36 SA37 SA38 SA39 SA40 SECTOR ADDRESS A20-A12 000000XXX 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX 100000XXX 100001XXX 100010XXX 100011XXX 100100XXX 100101XXX 100110XXX 100111XXX 101000XXX SECTOR SIZE (Kbytes/Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) ADDRESS RANGE 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh (x16) ADDRESS RANGE 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh - 20 - W19B320AT/B Sector Address Table (Top Boot Block), continued. BANK SECTOR SA41 SA42 SA43 SA44 SA45 SA46 Bank 2 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 Bank 1 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SECTOR ADDRESS A20-A12 101001XXX 101010XXX 101011XXX 101100XXX 101101XXX 101110XXX 101111XXX 110000XXX 110001XXX 110010XXX 110011XXX 110100XXX 110101XXX 110110XXX 110111XXX 111000XXX 111001XXX 111010XXX 111011XXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 SECTOR SIZE (KBYTES/KWORDS) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (X8) ADDRESS RANGE 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh (X16) ADDRESS RANGE 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE =VIH). Security Sector Addresses for Top Boot Devices DEVICE SECTOR ADDRESS A20-A12 SECTOR SIZE (KBYTES/KWORDS) (X8) ADDRESS RANGE (X16) ADDRESS RANGE W19B320ATT 111111XXX 256/128 3FE000h-3FE0FFh 1FF000h-1FF07Fh - 21 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 7.4 Sector Address Table (Bottom Boot Block) BANK SECTOR SA0 SA1 SA2 SA3 SA4 SA5 Bank 1 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank 2 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SECTOR ADDRESS A20-A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX SECTOR SIZE (Kbytes/Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) ADDRESS RANGE 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh (x16) ADDRESS RANGE 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh - 22 - W19B320AT/B Sector Address Table (Bottom Boot Block), continued. BANK SECTOR SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 Bank 3 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 Bank 4 SA65 SA67 SA68 SA69 SA70 SECTOR ADDRESS A20-A12 100000XXX 100001XXX 100010XXX 100011XXX 100100XXX 100101XXX 100110XXX 100111XXX 101000XXX 101001XXX 101010XXX 101011XXX 101100XXX 101101XXX 101110XXX 101111XXX 110000XXX 110001XXX 110010XXX 110011XXX 110100XXX 110101XXX 110110XXX 110111XXX 111000XXX 111001XXX 111010XXX 111011XXX 111100XXX 111101XXX 111110XXX 111111XXX SECTOR SIZE (KBYTES/KWORDS) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (X8) ADDRESS RANGE 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh (X16) ADDRESS RANGE 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Note: The address range is [A20:A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE =VIH). Security Sector Addresses for Bottom Boot Devices DEVICE SECTOR ADDRESS A20-A12 SECTOR SIZE (BYTES/WORDS) (X8) ADDRESS RANGE (X16) ADDRESS RANGE W19B320ATB 000000XXX 256/128 000000h-0000FFh 000000h-00007Fh - 23 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B Top Boot Sector/Sector Block Address for Protection/Unprotection SECTOR A20-A12 SECTOR/SECTOR BLOCK SIZE SA0 SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 000000XXX 000001XXX 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 64 K bytes 192 (3x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 192(3x64) K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes - 24 - W19B320AT/B Bottom Boot Sector/Sector Block Address for Protection/Unprotection SECTOR A20-A12 SECTOR/SECTOR BLOCK SIZE SA70 SA69-SA67 SA66-SA63 SA62-SA59 SA58-SA55 SA54-SA51 SA50-SA47 SA46-SA43 SA42-SA39 SA38-SA35 SA34-SA31 SA30-SA27 SA26-SA23 SA22-SA19 SA18-SA15 SA14-SA11 SA10-SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 111111XXX 111110XXX 111101XXX 111100XXX 1110XXXXX 1101XXXXX 1100XXXXX 1011XXXXX 1010XXXXX 1001XXXXX 1000XXXXX 0111XXXXX 0110XXXXX 0101XXXXX 0100XXXXX 0011XXXXX 0010XXXXX 0001XXXXX 000011XXX 000010XXX 000001XXX 000000111 000000110 000000101 000000100 000000011 000000010 000000001 000000000 64 K bytes 192 (3x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 256(4x64) K bytes 192(3x64) K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes 8 K bytes - 25 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 7.5 CFI Query Identification String DESCRIPTION ADDRESS (WORD MODE) DATA ADDRESS (BYTE MODE) Query-unique ASCII string "QRY" 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Primary OEM Command Set Address for primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternative OEM Extended table (00h = none exists) 7.5.1 System Interface String DESCRIPTION ADDRESS (WORD MODE) DATA ADDRESS (BYTE MODE) VDD Min. (write/erase) D7-D4: volt , D3-D0: 100 mV VDD Max. (write/erase) D7-D4: volt , D3-D0: 100 mV VPP Min. voltage (00h=no VPP pin present) VPP Max. voltage (00h=no VPP pin present) Typical timeout per single byte/word write 2N μs Typical timeout for Min. size buffer write 2N μs (00h=not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h=not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical ( 00h = not supported) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch - 26 - W19B320AT/B 7.5.2 Device Geometry Definition DESCRIPTION ADDRESS (WORD MODE) DATA ADDRESS (BYTE MODE) Device size =2N bytes Flash device interface description (refer to CFI publication 100) Max. number of bytes in multi-byte write=2N (00h=not supported) Number of Erase Block Regions within devices Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100 ) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information - 27 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 7.5.3 Primary Vendor-Specific Extended Query DESCRIPTION ADDRESS (WORD MODE) DATA ADDRESS ( BYTE MODE) 40h Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Silicon Revision Number 01h = 0.18 μm Erase suspend 0 = Not supported, 1= To read only; 2 = To read & write Sector protect 00 = Not supported, 01=Supported Sector Temporary Unprotect 00 = Not supported, 01=Supported Sector protect/unprotect scheme Simultaneous operation Number of Sectors (except for Bank 1) Burst mode type 00 = Not supported, 01=Supported Page mode type 00 = Not Supported, 01=4 Word Page, 02=8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 02h=Bottom Boot Device, 03h=Top Boot Device 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 0050h 0052h 0049h 0031h 0033h 0001h 0002h 0001h 0001h 0004h 0038h 0000h 0000h 0085h 0095h 000Xh 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh - 28 - W19B320AT/B 7.5.4 Command Definitions COMMAND SEQUENCE (note 1 ) Read (note 6) Reset (note 7) Normal Program Unlock Bypass Unlock Bypass Program (note 11) Unlock Bypass Reset (note12) Chip Erase Sector Erase Erase Suspend (note 13) Erase Resume (note 14) Manufacturer Word Code Byte AUTOSELECT(note8) Device Code Word Byte 4 Word Byte Word Byte Word Byte Word Byte BUS CYCLES (note 2-5) CYCLE 1 1 4 3 2 2 6 6 1 1 4 6 FIRST ADDR RA XXX 555 AAA 555 AAA XXX BA 555 AAA 555 AAA BA BA 555 AAA 555 AAA 555 AAA AA DATA RD F0 AA AA A0 90 AA AA B0 30 AA 2AA 555 2AA 555 2AA 555 55 55 (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA 90 90 (BA)X00 (BA)X01 (BA)x02 (BA)X03 (BA)X06 82/02 DA (BA)X0E (BA)X1C (BA)X0 F 00/01 (BA)x1E 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 555 AAA 555 AAA A0 20 PA PD SECOND ADDR DATA THIRD ADDR DATA FOURTH ADDR DATA FIFTH ADDR SIXTH DATA ADDR DATA AA 55 90 7E 0A Security Word Sector Factory Protect (note Byte 9) Sector/ Sector Block Protect Verify (note 10) Word 555 2AA AA 55 555 2AA 555 2AA 555 (BA)555 90 (BA)AAA 555 AAA 555 AAA (SA)X02 00/01 (SA)X04 4 Byte Word Byte Word Byte Word Byte AAA 555 AAA 555 AAA 55 Enter Security Sector Region Exit Security Sector Region Common Flash Interface (CFI) Query (note 15) 3 4 1 AA AA 55 55 88 90 XXX 00 AA 98 Legend: X = Don’t Care RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first. RD = Data read from location RA during read operation. - 29 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B SA = Address of the sector to be verified (in AUTOSELECT mode) or erased. Address bits A20-A12 uniquely select any sector. BA = Address of the bank that is being switched to AUTOSELECT mode, is in bypass mode, or is being erased Notes: 1. See Bus Operations Table for details. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the AUTOSELECT command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20-A11 are “don’t care”. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the AUTOSELECT mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the AUTOSELECT command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or Security Sector factory protect information. Data bits DQ15-DQ8 are don’t care. See the AUTOSELECT Command Sequence section for more information. 9. The data is 82h for factory locked and 02h for not factory locked. 10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the AUTOSELECT mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in AUTOSELECT mode. 7.5.5 Write Operation Status STATUS DQ7 (NOTE 2) #DQ7 0 1 DQ6 Toggle Toggle No toggle DQ5 (NOTE1) 0 0 0 DQ3 N/A 1 N/A DQ2 (NOTE 2) No toggle Toggle Toggle RY/#BY 0 0 1 Standard Mode Embedded Program Algorithm Embedded Erase Algorithm EraseSuspend Read Erase Suspended Sector Non-Erase Suspended Sector Erase Suspend Mode Data #DQ7 Data Toggle Data 0 Data N/A Data N/A 1 0 Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to DQ5 description section for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. - 30 - W19B320AT/B 7.6 Temporary Sector Unprotect Algorithm START #RESET = VID (Note 1) Perform Erase or Program Operations #RESET = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If #WP/ACC = VIL, outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. - 31 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 7.7 In-System Sector Protect/Unprotect Algorithms START PLSCNT=1 #RESET=VID Wait 1 μ s Protect all sectors The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT=1 #RESET=VID Wait 1 μ s No Temporary Sector Unprotect Mode No First Write Cycle=60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6=0,A1=1,A0=0 Wait 150 μ s No First Write Cycle=60h? Yes Temporary Sector Unprotect Mode All sectors protected ? Yes Set up first sector address Sector Unprotect: Write 60h to any address with A6=1,A1=1,A0=0 Reset PLSCNT=1 Increment PLSCNT Wait 15 mS Verity Sector Unprotect:Write 40h to sector address with A6=1, A1=1,A0=0 Read from sector address with A6=1, A1=1,A0=0 No PLSCNT =1000? Yes No Set up next sector address Data=00h? Yes No Device failed Last sector verified Yes Remove V ID from #RESET Write reset command Increment PLSCNT Verity Sector Protect:Write 40h to sector address with A6=0, A1=1,A0=0 Read from sector address with A6=0, A1=1,A0=0 No No PLSCNT =25? Yes Data=01h? Yes Yes Device failed Protect another sector? No Remove V ID from #RESET Write reset command Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Sector Unprotect complete - 32 - W19B320AT/B 7.8 Security Sector Protect Verify START Enter Security Sector #RESET = V IH or Wait 1 Write 60h to any address Write 40h to Security V ID μ s If data = 00h, Security Sector is unprotected. If data = 01h, Security Sector is producted. V IH or Remove from #RESET Write reset command Exit Security Sector Security Sector Protect Verify complete V ID Sector Address with A6 = 0 A1 = 1, A0 = 0 Read from Security Sector address with A6 = 0 A1 = 1, A0 = 0 7.9 Program Algorithm START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? Yes Increment Address No No Last Address? Yes Programming Completed - 33 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 7.10 Erase Algorithm START Write Program Command Sequence (Note1,2) Data Poll to Erasing Bank from System No Data=FFh? Yes Erase Completed Embedded Erase algorithm in progress Notes: 1. See Command Definitions Table for erase command sequence details. 2. See DQ3 section for the sector erase timer details. 7.11 Data Polling Algorithm START Read DQ7-DQ0 Addr=VA Yes DQ7=Data? No No DQ5=1? Yes Read DQ7-DQ0 Addr=VA DQ7=Data? No FAIL Yes PASS Notes: 1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. - 34 - W19B320AT/B 7.12 Toggle Bit Algorithm START Read DQ7-DQ0 Read DQ7-DQ0 Toggle Bit =Toggle? No Yes No DQ5=1? Yes Read DQ7-DQ0 Twice Toggle Bit =Toggle? No Yes Program/Erase Operation Not Complete,Write Reset Command Program/Erase Complete Note: The system should recheck the toggle bit even if DQ5 =”1” because the toggle bit may stop toggling as DQ5 changes to “1”. See DQ6 and DQ2 section for more information - 35 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings PARAMETER RATING UNIT Storage Temperature Plastic Packages Ambient Temperature with Power Applied VDD (Note 1) Voltage with Respect to Ground A9, #OE, and #RESET (Note 2) #WP/ACC All other pins (Note 1) Output Short Circuit Current (Note 3) Notes: -65 to +150 -65 to +125 -0.5 to +4.0 -0.5 to +12.5 -0.5 to +10.5 -0.5 to VDD +0.5 200 °C °C V V V V mA - 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions, input or I/O pins may overshoot to VDD +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, #OE, #RESET, and #WP/ACC is -0.5 V. During voltage transitions, A9, #OE, #WP/ACC, and #RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on #WP/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 Operating Ranges PARAMETER RATING UNIT Ambient Temperature (TA ) VDD Supply Voltages VDD for standard voltage range Industrial Grade Extended Grade -40 to +85 -20 to +85 2.7 to 3.6 °C V Operating ranges define those limits between which the functionality of the device is guaranteed. - 36 - W19B320AT/B 8.3 DC Characteristics 8.3.1 CMOS Compatible PARAMETER Input Load Current A9 Input Load Current Output Leakage Current VDD Active Read Current (Note 1, 2) SYM. ILI ILIT ILO TEST CONDITIONS MIN. VIN =VSS to VDD, VDD = VDD (Max.) VDD = VDD (Max.), A9 = 12.5V VOUT =VSS to VDD, VDD =VDD (Max.) - LIMITS TYP. 10 2 10 2 15 0.2 0.2 0.2 21 21 21 21 17 5 15 - UNIT MAX. ±1.0 35 ±1.0 16 4 16 4 30 5 5 5 45 45 45 45 35 10 30 0.8 VDD +0.3 9.5 μA μA μA mA mA mA mA mA μA μA μA mA mA mA mA mA V V V #CE = VIL, #OE = VIH ICC1 Byte Mode #CE = VIL, #OE = VIH Word Mode 5 MHz 1 MHz 5 MHz 1 MHz VDD Active Write Current (Note 2, 3) ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 IAcc VIL VIH VHH #CE = VIL, #OE = VIH, #WE = VIL #CE = VDD ±0.3V, #RESET = VDD ±0.3V - VDD Standby Current (Note2) VDD Reset Current (Note2) #RESET = VSS ±0.3V VIH = VDD ±0.3V, VIL = VSS ±0.3V Automatic Sleep Mode Current (note 2, 4) VDD Active Read-WhileProgram Current (note 1, 2) VDD Active Read-WhileErase Current (note 1, 2) VDD Active Program-WhileErase-Suspended Current (note 2, 5) #CE = VIL, #OE = VIH #CE = VIL, #OE = VIH #CE = VIL, #OE = VIH #CE = VIL, #OE = VIH VDD =3.0V ±10% Byte Word Byte Word ACC Accelerated Program Current, Word or Byte Input Low Voltage Input High Voltage Voltage for #WP/ACC Sector Protect/ Unprotect and Program Acceleration Voltage for AUTOSELECT and Temporary Sector Unprotected Output Low Voltage Output High Voltage Low VDD Lock-Out Voltage Notes: 1. 2. 3. 4. ACC Pin VDD Pin -0.5 0.7x VDD 8.5 VID VOL VOH1 VOH2 VLKO VDD =3.0V ±10% IOL = 4.0 mA, VDD = VDD (Min.) IOH = -2.0 mA, VDD = VDD (Min.) IOH = -100 μA, VDD = VDD (Min.) 8.5 0.85 VDD VDD -0.4 2.3 - 12.5 0.45 2.5 V V V V The ICC current listed is typically less than 2 mA/ MHz, with #OE at VIH. Maximum ICC specifications are tested with VDD = VDD max. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is200 nA. - 37 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 8.4 AC Characteristics 8.4.1 Test Condition TEST CONDITION 70ns UNIT Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 5 1 TTL gate 30 0-3.0 1.5 1.5 pF ns V V V 8.4.2 AC Test Load and Waveforms +3.3V 2.7K Ω D OUT 30 pF (Including Jig and Scope) 6.2K Ω Input 3V 1.5V 0V Test Point Output 1.5V Test Point - 38 - W19B320AT/B 8.5 Read-Only Operations PARAMETER SYM. TEST SETUP 70NS MIN. MAX. UNIT Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Hold Time From Address, #OE or #CE, Whichever Occurs First Read Output Enable Hold Time Toggle and #Data polling Note: Not 100 % tested TRC TACC TCE TOE TDF TDF TOH TOEH #OE, #CE =VIL #OE, = VIL 70 0 0 10 70 70 30 16 16 - ns ns ns ns ns ns ns ns ns 8.6 Hardware Reset (#RESET) PARAMETER SYM. MIN. MAX. UNIT #RESET PIN Low (During Algorithms) to Read Mode Embedded TReady TReady TRP TRH TRPD TRB 500 50 20 0 20 500 - μs #RESET Pin Low (Not During Embedded Algorithms) to Read Mode #RESET Pulse Width Reset High Time Before Read #RESET Low to Standby Mode RY/#BY Recovery Time Note: Not 100 % tested ns ns ns μs ns 8.7 Word/Byte Configuration (#BYTE) PARAMETER SYM. MIN. 70NS MAX. UNIT #CE to #BYTE Switching Low or High #BYTE Switching Low to Output High Z #BYTE Switching High to Output Active TELFL/TELFH TFLQZ TFHQV 70 5 16 - ns ns ns - 39 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 8.8 Erase and Program Operation PARAMETER Write Cycle Timing (Note 1) Address setup Time Address Setup Timing to #OE low during toggle bit polling Address Hold Time Address Hold Time From #CE or #OE high during toggle bit polling Data Setup Time Data Hold Time Output Enable High During toggle bit polling Read Recovery Time Before Write (#OE High to #WE Low) SYM. MIN. TWC TAS TASO TAH TAHT TDS TDH TOEPH TGHWL TCS TCH TWP TWPH TSR/W Byte Word Byte Word TPB TPW TACCP TSE TVCS TRB TBUSY 70 0 15 45 0 35 0 20 0 0 0 30 30 0 5 7 4 50 0 90 0.4 70ns TYP. MAX. ns ns ns ns ns ns ns ns ns ns ns ns ns ns μs μs μs sec μs ns ns UNIT #CE Setup Time #CE HOLD Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operation Programming Time (Note 2) Accelerated Programming Time (Noe2) Sector Erase Time (Note 2) VDD Setup Time (Note 1) Write Recovery Time from RY/#BY Program/Erase Valid to RY/#BY Delay Notes: 1. 2. Not 100 % tested See the “Alternate #CE Controlled Erase and Program Operations“ section for more information 8.9 Temporary Sector Unprotect PARAMETER VID Rise and Fall Time VHH Rise and Fall Time #RESET Setup Time for Temporary Sector Unprotect #RESET Hold Time from RY/#BY High for Temporary Sector Unprotect Note: Not 100 % tested SYM. TVIDR TVHH TRSP TRRB MIN. 500 250 4 4 MAX. - UNIT ns ns μs μs - 40 - W19B320AT/B 8.10 Alternate #CE Controlled Erase and Program Operations 70 NS PARAMETER SYM. MIN. TYPICAL (NOTE3) MAX. (NOTE4) UNIT Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover Time Before Write (#OE High to #WE Low) #WE Setup Time #WE Hold Time #CE Pulse Width #CE Pulse Width High Programming Time (Note 6) Accelerated Programming Time (Note 6) Sector Erase Time (Note 2) Chip Erase Time (Note 2) Chip Program Time (Note 5) Notes: 1. Not 100 % tested. TWC TAS TAH TDS TDH TGHEL TWS TWH TCP TCPH Byte Word Byte Word TPB TPW TACCP TSE TCE Byte Word 70 0 45 35 0 0 0 0 30 30 - 5 7 4 0.4 49 21 14 150 210 120 15 63 42 ns ns ns ns ns ns ns ns ns ns μs μs sec sec sec TCPB TCPW 2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 3. Typical program and erase time assume the following conditions :25℃,3.0 V VDD, 100,000 cycles .Additionally, programming typicals assume checkerboard pattern. 4. Under worst case conditions of 90℃, VDD =2.7V, 100,000 cycles. 5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most bytes program faster than maximun program times listed. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. 7. The device has a minimum erase and program cycle endurance of 100,000 cycles. - 41 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 9. TIMING WAVEFORMS 9.1 AC Read Waveform TRC Address #CE T ACC Addresses Stable T RH #OE TRH T OE T DF TOEH #WE T CE High-Z Outputs T OH High-Z Output Valid #RESET RY/#BY 0V 9.2 Reset Waveform RY/#BY #OE,#CE TRH #RESET TP R TReady Reset Timing NOT during Embedded Algorithms TReady RY/#BY #OE,#CE TRB #RESET TRP Reset Timings during Embedded Algorithms - 42 - W19B320AT/B 9.3 #BYTE Waveform for Read Operation #CE #OE #BYTE #BYTE Switching from word to byte mode TELFL DQ0-DQ14 Data Output (DQ0-DQ14) DQ15 Output Data Output (DQ0-DQ7) Address Input DQ15/A-1 TELFH #BYTE #BYTE Switching from byte to word mode DQ0-DQ14 TFLQZ Data Output (DQ0-DQ7) Data Output (DQ0-DQ14) DQ15/A-1 Address Input DQ15 Output T FHQV 9.4 #BYTE Waveform for Write Operation #CE #WE The falling edge of the last #WE sign #BYTE TSET (T ) AS T HOLD (T ) AH Note: Refer to the Erase /Program Operations table for TAS and TAH Specifica - 43 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 9.5 Programming Waveform Program Command Sequence (last two cycles) WC T AS T Read Status Data (last two cycles Address #CE #OE #WE Data RY/#BY VDD 555h PA AH T PA PA CH T WP T CS T PW T TDS A0h TWPH DH T PD BUSY T Status DOUT RB T VCS T Notes: 1. 2. PA = program address, PD = program data,DOUT is the true data at the program address Illustration shows device in word mode 9.6 Accelerated Programming Waveform VHH VIL or VIH T VHH TVHH VIL or VIH #WP/ACC - 44 - W19B320AT/B 9.7 Chip/Sector Erase Waveform Erase Command Sequence (last two cycl TWC Address #CE T CH #OE #WE Data RY/#BY VDD Read Status Data T AS SA 555h for chip erase 2AAh VA TAH VA TWP TCS TWPH TDS TSE 30h In Progress T DH 10 for Chip Erase 55h Complete T BUSY TRB TVCS Notes : 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write operation Status”). 2. These waveforms are for the word mode 9.8 Back-to back Read/Write Cycle Waveform TWC Addresses Valid PA TRC Valid RA T WC Valid PA T WC Valid PA TAH #CE #OE T WP #WE TWPH T OEH TACC T CE T OE TGHWL T CPH T CP TDF TDS Valid In TDH TOH Valid Out Valid In Valid In Data TSR/W #WE Controlled Write Cycle Read Cycle #CE Controlled Write Cycle - 45 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 9.9 #Data Polling Waveform (During Embedded Algorithms) T RC Addresses VA ACC T VA VA #CE TCH #OE T OEH #WE DQ7 DQ0-DQ6 RY/#BY T BUSY T CE T OE TDF TOH Complement Complement High Z True True Valid Data Valid Data High Z Status Data Status Data Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 9.10 Toggle Bit Waveform (During Embedded Algorithms) T AHT Addresses TAHT #CE TOEH TAS TASO TCEPH TOEPH TDH Valid Data Valid Status #WE #OE DQ6/DQ2 RY/#BY TOE Valid Status Valid Status Valid Data (first read) (second read) (stop toggling) Note: VA= Valid address;not requires for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. - 46 - W19B320AT/B 9.11 DQ 2 vs. DQ6 Waveform Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Read Erase Erase Complete #WE Erase Erase Suspend Program DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The sysytem may use #OE or #CE to toggle DQ2 and DQ6. 9.12 Temporary Sector Unprotect Timing Diagram V ID #RESET #CE #WE T RSP RY/#BY T RRB V SS ,V IL , or V IH V ID V SS ,V IL, or V IH T VIDR Program or Erase Command Sequence TVIDR 9.13 Sector/Sector Block Protect and Unprotect Timing Diagram V ID #RESET SA,A6, A1,A0 DATA #CE #WE #OE *For sector protect,A6=0,A1=1,A0=0.For sector unprotect ,A6=1,A1=1,A0=0 1 μs VIH Valid* Sector/sector Block Protect or Unprotect Valid* Verify Valid* 60h 60h Sector/Sector Block Protect:150 Sector/Sector Block Unprotect:15ms 40h μs, Status - 47 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 9.14 Alternate #CE Controlled Write (Erase/Program) Operation Timing #Data Polling Address 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase PA #WE #OE #CE TWC TWH t GHEL TCP TWS TAS TAH T PW, T ACCP, or T SE TCPH TDS DATA TRH #RESET RY/#BY . A0 for program 55 for erase TDH TBUSY . PD for program 30 for sector erase 10 for chip erase #DQ7 D OUT Notes: 1. Firgure indicates last two bus cycles of a program or erase operation. 2. PA= program address, SA= sector address, PD= program data. 3. #DQ7 is the complement of the data written to the device. Dout is the data written to the device. 4. Waveforms are for the word mode. - 48 - W19B320AT/B 10. LATCHUP CHARACTERISTICS PARAMETER MIN. MAX. Input voltage with respect to VSS on all pins except I/O pins (including A9, #OE, and #RESET) Input voltage with respect to VSS on all I/O pins VDD Current Note: Includes all pins except VDD. Test conditions: VDD = 3.0 V, one pin at a time. -1.0V -1.0V -100mA 12.5 V VDD +1.0V +100mA 11. CAPACITANCE PARAMETER SYM. TEST SETUP TSOP TFBGA MAX. UNIT TYPICAL MAX. TYPICAL Input Capacitance Output Capacitance Control Pin Capacitance CIN COUT CIN2 VIN = 0 VOUT = 0 VIN = 0 6 8.5 7.5 7.5 12 9 4.2 5.4 3.9 5.0 6.5 4.7 pF pF pF Notes: 1. Sampled, not 100 % tested. 2. Test condition TA = 25 °C, f = 1.0 MHz. - 49 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 12. ORDERING INFORMATION Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 50 - W19B320AT/B 13. PACKAGE DIMENSIONS 13.1 TFBGA48ball (6X8 mm^2, Ø=0.40mm) - 51 - Publication Release Date: December 27, 2005 Revision A4 W19B320AT/B 13.2 48-Pin Standard Thin Small Outline Package 1 48 e MILLIMETER INCH Sym. MIN. NOM. MAX. MIN. NOM. MAX. A A1 0.05 0.95 18.3 1.00 18.4 18.5 20.2 12.1 A2 1.20 0.002 1.05 0.037 0.039 0.041 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.047 E b D HD E 19.8 20.0 11.9 12.0 0.17 0.10 0.50 0.50 0.60 0.80 0.22 c D HD A2 θL L1 b c e L L1 0.27 0.007 0.009 0.011 0.21 0.004 0.020 0.008 0.70 0.020 0.024 0.028 0.031 0.10 0.004 0 5 A A1 Y Y θ 0 5 - 52 - W19B320AT/B 14. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A1 A2 A3 A4 March 1, 2005 April 14, 2005 May 16, 2005 December 27, 2005 50 Initial Issued Adding important notice 1. Updating ESN address, 2. Updating AUTOSELECT 8,17,48,49 codes table, 3.Updating ordering information, 4.Updating 48Ball TFBGA dimension. All Removing “Preliminary” characters. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 53 - Publication Release Date: December 27, 2005 Revision A4