W24257AJ-8N

W24257AJ-8N 32K × 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W24257AJ-8N is a high speed, low power CMOS static RAM organized as 32768 × 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • • High speed access time: 8 nS (max.) Single +5V power supply Fully static operation • • • All inputs and outputs directly TTL compatible Three-state outputs Available packages: 28-pin 300 mil SOJ PIN CONFIGURATIONS BLOCK DIAGRAM VDD VSS A0 . . DECODER CORE ARRAY A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin SOJ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 A14 CS OE WE CONTROL DATA I/O I/O1 . . I/O8 PIN DESCRIPTION SYMBOL A0−A14 I/O1−I/O8 CS WE OE VDD VSS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground -1- Publication Release Date: February 1998 Revision A2 W24257AJ-8N DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 0 to +55 UNIT V V W °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. TRUTH TABLE CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1−I/O8 High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 IDD IDD IDD OPERATING CHARACTERISTICS (VDD = 5V ±5%, VSS = 0V, TA = 0 to 55° C) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. VIL VIH ILI ILO VOL VOH IDD ISB ISB1 TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS = VIH or OE = VIH or WE = VIL IOL = +8.0 mA IOH = -4.0 mA CS = VIL, I/O = 0 mA, Cycle = Min., Duty = 100% CS = VIH Cycle = Min., Duty = 100% CS ≥ VDD -0.2V MIN. -0.5 +2.2 -10 -10 2.4 TYP. - MAX. +0.8 VDD +0.5 +10 +10 0.4 180 UNIT V V µA µA V V mA mA mA - - 30 10 Note: Typical characteristics are at VDD = 5V, TA = 25° C. -2- W24257AJ-8N CAPACITANCE (VDD = 5V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Input/Output Capacitance SYM. CIN CI/O CONDITIONS VIN = 0V VOUT = 0V MAX. 8 10 UNIT pF pF Note: These parameters are sampled but not 100% tested. THERMAL RESISTANCE PARAMETER Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance SYM. CONDITIONS A. F. R. = 1m/sec, TA = 25° C A. F. R. = 1m/sec, TA = 25° C MAX. 20 60 UNIT °C/W °C/W θJC θJA Note: These parameters are only applied to "TSOP" and "SOJ" package types. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 5 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS AC TEST LOADS AND WAVEFORM R1 480 ohm R1 480 ohm 5V OUTPUT 30 pF Including Jig and Scope R2 255 ohm 5V OUTPUT 5 pF Including Jig and Scope R2 255 ohm (For TCLZ , TOLZ , TCHZ, TOHZ , TWHZ , TOW ) 3.0V 90% 10% 5 nS 90% 10% 5 nS 0V -3- Publication Release Date: February 1998 Revision A2 W24257AJ-8N AC CHARACTERISTICS (VDD = 5V ±5%, VSS = 0V, TA = 0 to 55° C) Read Cycle PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change ∗ These parameters are sampled but not 100% tested. SYM. TRC TAA TACS TAOE TCLZ∗ TOLZ∗ TCHZ∗ TOHZ∗ TOH W24257AJ-8N MIN. 8 3 0 3 MAX. 8 8 4 4 4 nS nS nS nS nS nS nS nS nS UNIT Write Cycle PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write ∗ These parameters are sampled but not 100% tested. CS , WE SYM. TWC TCW TAW TAS TWP TWR TDW TDH TWHZ∗ TOHZ∗ TOW W24257AJ-8N MIN. 8 7 7 0 7 0 6 0 0 MAX. 5 5 nS nS nS nS nS nS nS nS nS nS nS UNIT -4- W24257AJ-8N TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH DOUT TAA TOH Read Cycle 2 (Chip Select Controlled) CS TACS DOUT TCLZ TCHZ Read Cycle 3 (Output Enable Controlled) T RC Address T AA OE T AOE T OLZ CS T ACS DOUT TCLZ T CHZ T OHZ T OH -5- Publication Release Date: February 1998 Revision A2 W24257AJ-8N Timing Waveforms, continued Write Cycle 1 (OE Clock) TWC T OE TCW CS T AW TAS T D OUT T D IN TDH (1, 4) TWP Write Cycle 2 (OE = VIL Fixed) T WC Address TCW CS TAW WE TAS T WP TWHZ (1, 4) TOH (2) TOW (3) TWR DOUT TDW DIN TDH Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24257AJ-8N ORDERING INFORMATION PART NO. ACCESS TIME (nS) 8 OPERATING CURRENT MAX. (mA) 180 STANDBY CURRENT MAX. (mA) 10 PACKAGE W24257AJ-8N Notes: 300 mil SOJ 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. PACKAGE DIMENSIONS 28-pin Small Outline J Band Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. 0.140 0.027 0.095 0.026 0.016 0.008 0.100 0.028 0.018 0.010 0.710 0.295 0.044 0.245 0.327 0.077 0.300 0.050 0.265 0.337 0.087 0.105 0.032 0.022 0.014 0.730 0.305 0.056 0.285 0.347 0.097 0.045 0.004 0 10 0 7.49 1.12 6.22 8.31 1.96 0.69 2.41 0.66 0.41 0.20 2.54 0.71 0.46 0.25 18.03 7.62 1.27 6.73 8.56 2.21 2.67 0.81 0.56 0.36 18.54 7.75 1.42 7.24 8.81 2.46 1.14 0.10 10 3.56 28 15 E HE 1 14 A A1 A2 b1 b c D E e e1 HE L S y θ Notes: D c A2 A L £c A1 y e1 s Seating Plane b b1 e 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec. should be based on final visual inspection spec. -7- Publication Release Date: February 1998 Revision A2 W24257AJ-8N VERSION HISTORY VERSION A1 A2 DATE Nov. 1997 Feb. 1998 4 PAGE Initial Issued Modify TDW(Data Valid to End of Write) from 5 nS to 6 nS DESCRIPTION Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5796096 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice & Fax-on-demand: 886-2-27197006 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. -8-