NJ88C30KADP

THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS NJ88C30 IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS NJ88C30 DS3281-1.1 NJ88C30 VHF SYNTHESISER The NJ88C30 contains all the logic needed for a VHF PLL synthesiser and is fabricated on the GPS high performance, small geometry CMOS process. The circuit contains a reference oscillator and divider, a two-modulus prescaler and 4-bit control register, a 12-bit programmable divider, a phase comparator and the necessary data input and control logic. GROUND DATA TRANSFER CLOCK DATA CRYSTAL MON CRYSTAL IN CRYSTAL OUT 1 2 3 4 5 6 7 14 13 12 COMP FREQ f UP f DN LD VCO P DIV OUT VDD FEATURES s Low Power CMOS NJ88C30 11 10 s s s s Easy to Use Low Cost Single Chip Synthesiser to VHF Lock Detect Output 9 8 DP14, MP14 APPLICATIONS s Mobile Radios s Hand Held Portable Radios s Sonobuoys ORDERING INFORMATION NJ88C30 KA DP Plastic DIL Package NJ88C30 KA MP Miniature Plastic DIL Package Fig.1 Pin connections - top view ABSOLUTE MAXIMUM RATINGS Supply voltage, VDD Voltage on any pin Operating temperature Storage temperature CRYSTAL MON VDD 8 14 0V REFERENCE DIVIDER 4 1, 5, 10, 20, 2, 4, 8 OR 16 VDD 13 COMP FREQ 20·3V to 6V 20·3V to VDD10·3V 230°C to 170°C 255°C to 1125°C CRYSTAL OUT 7 5 0V 6 CRYSTAL IN 10 4 100 VCO 4 15/16 REF SELECT (DR2-DR0) 12 PHASE COMP 0V 11 f UP f DN LOCK DETECT (LD) 4-BIT COUNTER 12-BIT PROG DIVIDER 0V 9 0V P DIV OUT 4-BIT REGISTER DATA TRANSFER DATA CLOCK 2 4 3 12-BIT REGISTER 3-BIT REGISTER 19-BIT SHIFT REGISTER 1 GROUND Fig.2 Block diagram NJ88C30 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated): TAMB = –30°C to +70°C, VDD = 5V ± 0·5V Characteristic Supply current Crystal Oscillator Frequency External input level High level Low level VCO Input Input sensitivity Slew rate Input impedance DATA, DATA TRANSFER and CLOCK Inputs High level Low level Rise, fall time Data set-up time Clock frequency Transfer pulse width CRYSTAL MONITOR Output Current sink COMP FREQ, LD, P DIV Current sink f UP / f DN Current sink Current source Pin Min. 8 Value Typ. 4 Max. 7 mA Units Conditions 1VRMS VCO input at 200MHz and fXTAL = 10MHz Parallel resonant, fundamental crystal AC coupled DC coupled DC coupled At 200MHz, see Fig. 3 6, 7 6 6 6 10 10 10 1 VDD21 10 15 MHz Vrms V V Vrms V/µs 1 1 4 5pF// 10k 2, 3, 4 2. 3, 4 2, 3 3, 4 3 2 5 9, 11, 14 12 13 VDD21 1 200 200 2 500 0·8 1·6 0·8 0·8 V V ns ns MHz ns mA mA mA mA See Fig. 4 VOUT = 0·5V VOUT = 0·5V VOUT = 0·5V VOUT = VDD20·5V 1·6 VCO INPUT AMPLITUDE (V RMS) 1·4 1·2 1·0 0·8 0·6 0·4 0·2 0 TYPICAL GUARANTEED OPERATING AREA * * Tested as specified in Table of Electrical Characteristics 0 50 100 150 FREQUENCY (MHz) 200 Fig. 3 Input sensitivity 2 NJ88C30 CLOCK DATA DR2 DR1 DR0 DF15 DF1 DF0 DATA SET-UP TIME DATA TRANSFER TRANSFER PULSE WIDTH Fig. 4 Input data timing diagram 180 20 PHASE (DEGREES) 1M FREQUENCY (Hz) 10M 10 GAIN (dB) 120 0 60 210 0 100k 100k 1M FREQUENCY (Hz) 10M Fig. 5 Gain and phase characteristics of reference oscillator inverter CIRCUIT DESCRIPTION Crystal Oscillator and Reference Divider The Reference oscillator consists of a Pierce type oscillator intended for use with a parallel resonant fundamental crystal. Typical gain and phase characteristics for the oscillator inverter are shown in Fig 5. An external reference oscillator may be used by either capacitively coupling a 1V RMS sinewave into CRYSTAL IN (pin 6) or, if CMOS levels are available, by direct connection to CRYSTAL IN. The reference oscillator drives a 4100 prescaler followed by a reference divider to provide a range of comparison frequencies which are selected by decoding the first three bits (DR2, DR1, DR0) of the input data. The possible division ratios and the comparison frequencies (channel spacing) if a 10MHz crystal is used are shown in Table 1. DR2 DR1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 DR0 0 1 0 1 0 1 0 1 Total division ratio 1600 800 400 200 2000 1000 500 100 Comparison frequency for 10MHz Ref. Osc. 6·25kHz 12·5kHz 25kHz 50kHz 5kHz 10kHz 20kHz 100kHz To assist in trimming the crystal, an open drain output at one hundredth of the reference oscillator frequency is provided on CRYSTAL MONITOR pin 5 Programmable Divider The programmable divider consists of a 415/16 two modulus prescaler with a 4-bit control register, followed by a 12-bit programmable divider. A 1V RMS sinewave should be capacitively coupled from the VCO to the divider input VCO pin (pin 10). The overall division ratio is selected by a single 16-bit word (DF15 to DF0), loaded through the serial data bus. A lower limit of 240 ensures correct prescaler operation; the upper limit is 65535. The VCO frequency in a locked system will be this division ratio multiplied by the comparison frequency. Phase Comparator The phase comparator consists of a digital type phase comparator with open drain f UP and f DN outputs and an open drain LOCK DETECT (LD) output. Open drain outputs from the reference divider and programmable divider are provided for monitoring purposes or for use with an external phase comparator. Waveforms for all these outputs are shown in Fig.6. The duty cycle of f UP and f DN versus phase difference are shown in Fig. 7. The phase comparator is linear over a ± 2π range and if the phase gains or slips by more than 2π, the phase comparator outputs repeat with a 2π period. Table 1 Reference divider division ratios 3 NJ88C30 (a) Phase P DIV output leads phase COMP FREQ output COMP FREQ P DIV f UP f DN LD (b) Phase P DIV output lags phase COMP FREQ output COMP FREQ P DIV f UP f DN LD Fig. 6 Phase comparator waveforms DUTY CYCLE f UP 100% 0% 22π 0 DUTY CYCLE f DN 100% 2π PHASE DIFFERENCE 0% 22π 0 2π PHASE DIFFERENCE Fig. 7 Phase comparator output characteristics 4 NJ88C30 Once the phase difference exceeds 2π, the comparator will gain or slip one cycle and then try to lock on to the new zero phase difference. Note that very narrow pulses may be seen on the inactive phase comparator output at the end of the pulse on the active output, as shown in Fig. 6. Data Input and Control Register To control the synthesiser a simple three-line serial input is used with DATA, CLOCK and DATA TRANSFER signals. The data consists of 19 bits; the first three, DR2, DR1 and DR0, control the reference divider while the following sixteen, DF15 LOCK DETECT (LD) to DF0, control the prescaler and programmable divider. Until the synthesiser receives the DATA TRANSFER pulse, it will use the previously loaded data; on receiving the pulse it will switch rapidly to the new data. APPLICATIONS A simplified circuit for a synthesiser intended for VHF broadcast receiver applications is shown in Fig. 8. When the varicap line drive voltage necessary to tune the required band is greater than 5V, some form of level shifter such as the operational amplifier shown in Fig. 8 is required. 1 DATA TRANSFER CLOCK DATA 2 3 14 13 12 R1' 18k R2 10k 22k C1 47n VCO 112V 22k 10n R1 18k 1 112V 10k 10n 22k VARICAP DRIVE 1 -10V 4 NJ88C30 11 5 6 10 9 8 SL562 2 4·5MHz 7 5 - 65p 15V Fig.8. Typical application PROGRAMMING EXAMPLE 1.Maximum Frequency For a channel spacing (comparison frequency, fcomp) of 5kHz when using a 10MHz crystal oscillator, the reference divider ratio will need to be 2000 (seeTable 1) This is programmed as binary 100 (= 4HEX) in the most significant three of the 19 bits (MSB programmed first). DR 2 Binary Hex 1 1 0 0 0 15 14 13 12 11 10 1 0 0 1 1 1 9 0 8 0 To obtain the maximum VCO frequency of 200MHz the programmable divider ratio would be: 2003106 = 403103 which is 9C40 HEX 53103 The program word would then be as shown in Table 2. DF 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 0 4 9 C 4 0 Table 2 Maximum VCO frequency programming (fXTAL = 10MHz, fcomp = 5kHz) 240 = F0HEX gives a minimum programmable VCO frequency of 240353103 = 1·2MHz. The program word for this frequency is therefore as shown in Table 3. DF 0 0 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 1 6 1 5 1 4 1 3 0 2 0 1 0 0 0 2. Minimum Frequency Using the same crystal frequency and channel spacing (10MHz, 5kHz), the lower limit of programmable divider ratio of DR 2 Binary Hex 1 1 0 4 0 0 F 0 Table 3 MinimumVCO frequency programming (fXTAL = 10MHz, fcomp = 5kHz) 5 NJ88C30 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. 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