P10C68-35

P10C68/P11C68 PRELIMINARY INFORMATION DS3600-1.2 September 1992 P10C68/P11C68 (Previously PNC10C68 and PNC11C68 ) CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM (Supersedes DS3159-1.3, DS3160-1.3, DS3234-1.1, DS3235-1.1) The P10C68 and P11C68 are fast static RAMs (35 and 45 ns) with a non-volatile electically-erasable PROM (EEPROM) cell incorporating in each static memory cell. The SRAM can be read and written an unlimited number of times while independent non-volatile data resides in PROM. On the P10C68 data may easily be transferred from the SRAM to the EEPROM (STORE) and from the EEPROM back to the SRAM ( RECALL) using the NE (bar) pin. The Store and Recall cycles are initiated through software sequences on the P11C68. These devices combine the high performance and ease of use of a fast SRAM with the data integrity of nonvolatility. The P10C68 and P11C68 feature the industry standard pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and ceramic dual-in-line packages. NE A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W NC A8 A9 A 11 G A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 FEATURES I Non-Volatile Data Integrity I 10 year Data Retention in EEPROM I 35ns and 45ns Address and Chip Enable Access Times I 20ns and 25ns Output Enable Access I Unlimited Read and Write to SRAM I Unlimited Recall Cycles from EEPROM I 104 Store Cycles to EEPROM I Automatic Recall on Power up I Automatic Store Timing I Hardware Store Protection I Single 5V ± 10% Operation I Available in Standard Package 28-pin 0.3-inch DIL plastic and ceramic I Commercial and Industrial temperature ranges ORDERING INFORMATION (See back page) Figure 1. Pin connections - top view. Pin Name A0 - A12 W DQ0 - DQ7 E G VCC VSS Pin 1 NE Pin 1 N/C Function Address inputs Write enable Data in/out Chip enable Output enable Power (+5V) Ground Non volatile enable P10C68 No connection P11C68 1 P10C68/P11C68 EEPROM ARRAY 256 x 256 A3 A4 A5 A6 A7 A8 A9 A12 R O W D E C O D E R STATIC RAM ARRAY 256 x 256 STORE RECALL STORE/ RECALL CONTROL DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I N P U T B U F F E R S COLUMN I/O COLUMN DECODER A0 A1 A2 A10 A11 G NE (P10C68 only) E W Figure 2. Logic block diagram. 2 P10C68/P11C68 ABSOLUTE MAXIMUM RATINGS Voltage on typical input relative to VSS Voltage on DQ0-7 and G(bar) Temperature under Bias Storage temperature Power dissipation DC output current -0.6V to 7.0V -0.5V to (Vcc + 0.5V) -55°C to + 125°C -65°C to + 150°C 1W 15mA NOTE Stresses greater than those listed in the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at any other conditions than those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect reliability. (one output at a time, one second duration) DC OPERATING CONDITIONS Parameter Symbol Min. Supply voltage Input logic '1' voltage Input logic '0' voltage Ambient operating temperature commercial industrial VCC VIH VIL Tamb Tamb Value Typ. 5.0 2.2 VSS -0.5 0 -40 VCC +0.5 0.8 +70 +85 Max. V V V o o Units Conditions All inputs All inputs C C DC ELECTRICAL CHARACTERISTICS Commercial temperature range Test conditions (unless otherwise stated): Tamb = 0°C to 70°C, Vcc = +5V (See notes 1, 2 and 3) Characteristic Symbol Min. Average power supply current Average power supply current during STORE cycle Average power supply current (standby, cycling TTL input levels) ICC1 ICC2 ISB1 Value Max. 75 65 50 mA mA mA tAVAV = 35ns tAVAV = 45ns All inputs at VIN ≤ 0.2V tAVAV = 35ns tAVAV = 45ns E(bar) ≥VIH, all other inputs cycling E (bar)≥(VCC -0.2V), all other inputs at VIN≤0.2V or ≥(VCC 0.2V) VCC = max, VIN = VSS to VCC VCC = max, VIN = VSS to VCC IOUT = 4mA IOUT = 8mA Units Conditions 23 20 mA mA Average power supply current (standby, stable CMOS input levels) ISB2 1 mA Input leakage current (any input) Off state output leakage current Output logic '1' voltage Output voltage '0' voltage IILK IOLK VOH VOL ±1 ±5 2.4 0.4 µA µA V V NOTES 1. ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 2. Bringing E (bar) ≥ VIH will not produce standby currents levels until any non-volatile cycle in progress has timed out. See Mode Selection table. 3. ICC2 is the average current required for the duration of the STORE cycle (tSTORE) after the sequence that initiates the cycle. 3 P10C68/P11C68 Industrial temperature range Test conditions (unless otherwise stated): Tamb = -40˚C to 70˚C, Vcc = +5V ± 10% (See notes 4, 5 and 6) Characteristic Symbol Min. Average power supply current Average power supply current during STORE cycle Average power supply current (standby, cycling TTL input levels) ICC1 ICC2 ISB1 Value Max. 80 75 50 mA mA mA tAVAV = 35ns tAVAV = 45ns All inputs at VIN ≤ 0.2V tAVAV = 35ns tAVAV = 45ns E(bar) ≥VIH, all other inputs cycling E (bar)≥(VCC -0.2V), all other inputs at VIN≤0.2V or ≥(VCC 0.2V) VCC = max, VIN = VSS to VCC VCC = max, VIN = VSS to VCC IOUT = 4mA IOUT = 8mA Units Conditions 27 23 mA mA Average power supply current (standby, stable CMOS input levels) ISB2 1 mA Input leakage current (any input) Off state output leakage current Output logic '1' voltage Output voltage '0' voltage IILK IOLK VOH VOL ±1 ±5 2.4 0.4 µA µA V V NOTES 4. ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 5. Bringing E (bar) ≥ VIH will not produce standby currents levels until any non-volatile cycle in progress has timed out. See Mode Selection table. 6. ICC2 is the average current required for the duration of the STORE cycle (tSTORE) after the sequence that initiates the cycle. AC TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing reference levels Output load VSS to 3V ≤5ns 1.5V See Figure 3 5.0V 480 Ohms CAPACITANCE Tamb = 25°C, f = 1.0MHz (see note 7) Parameter Input capacitance Output capacitance Symbol CIN COUT Max. Units 5 7 pF pF Conditions ∆V=0 to 3V ∆V=0 to 3V OUTPUT 255 Ohms 30p INCLUDING SCOPE AND FIXTURE NOTE 7. These parameters are characterised but not 100% tested. Figure 3. AC output loading. 4 P10C68/P11C68 SRAM MEMORY OPERATION Test conditions (unless otherwise stated): Commercial and Industrial Temperature Range Tamb = -40°C to + 85°C, Vcc = + 5V ± 10% READ CYCLES 1 AND 2 (See note 8) Symbol Standard tELQV tAVAV tAVQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL tWHQV Alternative tACS tRC tAA tOE tOH tLZ tOHZ tOLZ tHZ tPA tPS tWR Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Outout disable to output inactive Chip enable to power active Chip disable to power standby Write recovery time P10C68-35 P11C68-35 Min. Max. 35 35 35 20 5 5 20 0 15 0 25 45 0 25 55 0 20 5 5 25 45 45 25 P10C68-45 P11C68-45 Max. Min. 45 Parameter Units Notes ns ns ns ns ns ns ns ns ns ns ns ns 9 10 11 11 12 12 NOTES 8. E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a monotonic fashion. NE (bar) must be ≥ VIH during entire cycle. 9. For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle. 10. Device is continuously selected with E (bar) low, and G (bar) low. 11. Measured ±200mV from steady state output voltage. Load capacitance is 5pF. 12. Parameter guaranteed but not tested. tAVAV ADDRESS tAVQV tAXQX DQ (DATA OUT) DATA VALID W tWHQV Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10). 5 P10C68/P11C68 tAVAV ADDRESS tELQV E tELQX tEHQZ G DQ (DATA OUT) ACTIVE ICC STANDBY tELICCH tGLQV tGHQZ DATA VALID tEHICCL tGLQX W tWHQV Figure 5. READ CYCLE 2 timing diagram (see note 9). WRITE CYCLE 1 : W (BAR) CONTROLLED (See notes 8 and 13) Commercial and Industrial Temperature Range Symbol Standard tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ tWHQZ Alternative tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write cycle time Write pulse width Chip enable to end of write Data set-up to end of write Data hold after end of write Address set-up to end of write Address set-up to start of write Address hold after end of write Write enable to output disable Output active after end of write Parameter P10C68-35 P11C68-35 Max. Min. 45 35 35 30 0 35 0 0 35 5 5 P10C68-45 P11C68-45 Max. Min. 45 35 35 30 0 35 0 0 35 Units Notes ns ns ns ns ns ns ns ns ns ns 11, 14 NOTES 13. E (bar) or W (bar) must be ≥ VIH during address transitions. 14. If W (bar) is low when E (bar) goes low, the outputs remain in the high impedance state. 6 P10C68/P11C68 tAVAV ADDRESS tELWH E tAVWL W tDVWH DATA IN DATA VALID tWLQZ DATA OUT PREVIOUS DATA HIGH IMPEDANCE tWHQX tWHDX tAVWH tWLWH tWHAX Figure 6. WRITE CYCLE 1: W (bar) controlled timing diagram (see notes 8 and 13). WRITE CYCLE 2 : E (BAR) CONTROLLED (See notes 8 and 13) Symbol Standard tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tEHAX tAVWL Alternative tWC tWP tCW tDW tDH tAW tWR tAS Write cycle time Write pulse width Chip enable to end of write Data set-up to end of write Data hold after end of write Address set-up to end of write Address hold after end of write Address set-up to start of write P10C68-35 P11C68-35 Max. Min. 45 35 35 30 0 35 0 0 P10C68-45 P11C68-45 Max. Min. 45 35 35 30 0 35 0 0 Parameter Units Notes ns ns ns ns ns ns ns ns tAVAV ADDRESS tAVEL E tAVEH W tWLEH tDVEH DATA IN DATA VALID tEHDX tELEH tEHAX DATA OUT HIGH IMPEDANCE Figure 7. WRITE CYCLE 2: E (bar) controlled timing diagram (see notes 8 and 13). 7 P10C68/P11C68 VCC 5.0V 3.3V t AUTO RECALL STORE INHIBIT Figure 8. Automatic RECALL and STORE inhibit. NON-VOLATILE MEMORY OPERATION OF P10C68 MODE SELECTION E H L L L L L L W X H L H L L H G X L X L H L H NE X H H L L L X Not selected Read RAM Write RAM Non-volatile recall (Note 15) Non-volatile store No operation Mode Power Standby Active Active Active ICC2 Active NOTE 15. An automatic RECALL also takes place on chip power-up, starting when Vcc exceeds 3.3V, and taking tRECALL from the time at which Vcc exceeds 3.3V. Vcc must not drop below 3.3V once it has exceeded it for the RECALL to function properly. STORE CYCLE 1 : W (BAR) CONTROLLED (See note 16) Symbol Standard tWLQX tGHNL tNLWL tWLNH tELWL Alternative tSTORE tWC Store cycle time Output disable set-up to NE (bar) fall Non-volatile set-up to write low Write low to NE (bar) rise Chip enable SET-UP Parameter P10C68-35 Min. Max. 10 0 0 45 0 0 0 45 0 P10C68-45 Min. Max. 10 ms ns ns ns ns 17 Units Notes 18 8 P10C68/P11C68 STORE CYCLE 2 : E (BAR) CONTROLLED (See note 13) Symbol Standard tELQX1 tNLEL tWLEL tELNH tGHEL Alternative tSTORE tWC Store cycle time NE (bar) set-up to chip enable Write enable wet-up to chip enable Chip enable to NE (bar) rise Output disable set-up to E (bar) fall Parameter P10C68-35 Min. Max. 10 0 0 45 0 0 0 45 0 P10C68-45 Min. Max. 10 ms ns ns ns ns 17 Units Notes 18 NOTES 16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a monotonic fashion. 17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted by Vcc