UN-2864KSWXG22

Product Specification Part Name: OLED Display Module Customer Part ID: Limito Part ID: UN-2864KSWXG22 Ver: B Customer: Approved by From: Unvision technology Inc. Approved by Unvision technology Inc. Http://www.Unvision.com.cn Notes: 1. Please contact Unvision technology Inc. before assigning your product based on this module specification 2. The information contained herein is presented merely to indicate the characteristics and performance of our products. No responsibility is assumed by Unvision technology Inc. for any intellectual property claims or other problems that may result from application based on the module described herein. Ver:B Revised History Part Number Revision Revision Content Revised on UN-2864KSWXG22 A New 20190726 B 修改包装数量 20191222 i Ver:B Contents Revision History Contents 1. Basic Specifications 1.1 1.2 1.3 1.4 1.5 Display Specifications Mechanical Specifications Active Area / Memory Mapping & Pixel Construction Mechanical Drawing Pin Definition 2. Absolute Maximum Ratings 3. Optics & Electrical Characteristics 3.1 Optics Characteristics 3.2 DC Characteristics 3.3 AC Characteristics 3.3.1 Serial Interface Characteristics (4-wire SPI) 4. Functional Specification 4.1 Commands 4.2 Power down and Power up Sequence 4.2.1 Power up Sequence 4.2.2 Power down Sequence 4.3 Reset Circuit 4.4 Actual Application Example 4.4.1 VCC Supplied Externally 4.4.2 VCC Generated by Internal DC/DC Circuit 5. Reliability 5.1 Contents of Reliability Tests 5.2 Failure Check Standard 6. Outgoing Quality Control Specifications 6.1 Environment Required 6.2 Sampling Plan 6.3 Criteria & Acceptable Quality Level 6.3.1 Cosmetic Check (Display Off) in Non-Active Area 6.3.2 Cosmetic Check (Display Off) in Active Area 6.3.3 Pattern Check (Display On) in Active Area 7. Package Specifications 8. Precautions When Using These OEL Display Modules 8.1 8.2 8.3 8.4 8.5 Handling Precautions Storage Precautions Designing Precautions Precautions when disposing of the OEL display modules Other Precautions Warranty Notice ii Ver:B 1. Basic Specifications 1.1 Display Specifications 1) 2) 3) Display Mode: Display Color: Drive Duty: Passive Matrix Monochrome (White) 1/64 Duty 1.2 Mechanical Specifications 1) 2) 3) 4) 5) 6) 7) Outline Drawing: Number of Pixels: Panel Size: Active Area: Pixel Pitch: Pixel Size: Weight: According to the annexed outline drawing 128 × 64 34.5 × 23.0 × 1.4 (mm) 29.42 × 14.7 (mm) 0.23 × 0.23(mm) 0.21 × 0.21(mm) 2.18 (g) 1.3 Active Area / Memory Mapping & Pixel Construction P0.23x128-0.02=29.42 "A" 0.23 0.21 P0.23x64-0.02=14.7 0.23 0.21 Segment 129 ( Column 1 ) Common 1 ( Row 63 ) Common 63 ( Row 1 ) Detail "A" Scale (10:1) Segment 2 ( Column 128 ) Common 0 ( Row 64 ) Common 62 ( Row 2 ) 1 Ver:B Item A 34.5±0.2 (Panel Size) 0.5±0.5 (1.1) (2.1) 31.42±0.2 (V/A) Active Area 1.3" 128 x 64 Pixels 29.42±0.2 (A/A) 5 10 Segment 129 ( Column 1 ) Segment 2 ( Column 128 ) 1 Common 0 ( Row 64 ) Common 1 ( Row 63 ) Contact Side 16 Common 62 ( Row 2 ) Common 63 ( Row 1 ) Symbol 1 2 3 C2P C2N C1P 4 5 C1N VBAT VSS VDD CS# RES# 8 9 10 D/C# SCLK SDIN 11 12 W=0.3±0.03 13 14 15 IREF VCOMH VCC VSS 0.3±0.03 8.5±0.1 0.21 0.23 16 Notes: Customer Approval Signature 0.23 0.21 1. Color: White 2. Driver IC: CH1116 3. FPC Number: LT1116P08 4. Interface: 4-wire SPI 5. General Tolerance: ±0.30 Pin 6 7 3±0.2 6.5±0.2 4.5±0.2 P0.23x64-0.02=14.7 Protective Tape 15x8(6.8)x0.06mm 25±0.2 05 ±0. 0.8 "A" P0.5*(16-1)=7.5±0.05 Mechanical Drawing 1 6.5±0.1 1.4 2-? P0.23x128-0.02=29.42 (48) Glue Polarizer t=0.2mm 6 Remove Tape t=0.15mm Max 1.4±0.1 23±0.2 (Panel Size) 19.2±0.2 (Cap Size) 18.2±0.2 (Polarizer) 16.7±0.2 (V/A) 14.7±0.2 (A/A) Remark Original Drawing 2 (2.54) (1.54) 0.5±0.5 33.5±0.2 (Polarizer) 34.5±0.2 (Cap Size) Active Area 1.3" 128 x 64 Pixels Date 20190704 Drawing Number Unvision technology Inc. UN-2864KSWXG22 Material Unless Otherwise Specified Unit mm Title UN-2864KSWXG22 Folding Type OEL Display Module Pixel Number: 128 x 64, Monochrome, COG Package Soda Lime / Polyimide General Roughness Detail "A" Scale (10:1) Tolerance Dimension ±0.3 Angle ±1 By Date Drawn HONG 20190704 E.E. Panel / E. Rev. A P.M. Scale 1:1 Sheet 1 of 1 Size A3 Ver:B 1.5 Pin Definition Pin Number Symbol I/O Function 7 VDD P 6,16 VSS P Power Supply for Logic This is a voltage supply pin. It must be connected to external source. Ground of Logic Circuit This is a ground pin. It acts as a reference for the logic pins. It must be connected to external ground. Power Supply 15 VCC P 13 IREF I 14 VCOMH O Power Supply for OEL Panel This is the most positive voltage supply pin of the chip. A stabilization capacitor should be connected between this pin and VSS when the converter is used. It must be connected to external source when the converter is not used. Driver Current Reference for Brightness Adjustment This pin is segment current reference pin. A resistor should be connected between this pin and VSS. Set the current at 12.5μA maximum. Voltage Output High Level for COM Signal This pin is the input pin for the voltage output high level for COM signals. A capacitor should be connected between this pin and VSS. DC/DC Converter 5 VBAT P 3/4 1/2 C1P / C1N C2P / C2N I 9 RES# I 8 CS# I 10 D/C# I Power Supply for DC/DC Converter Circuit This is the power supply pin for the internal buffer of the DC/DC voltage converter. It must be connected to external source when the converter is used. It should be connected to VDD when the converter is not used. P o s i t i v e T e r m i n a l o f t h e F l y i n g I n v e r ti n g C a p a c i t o r Negative Terminal of the Flying Boost Capacitor The charge-pump capacitors are required between the terminals. They must be floated when the converter is not used. Interface Power Reset for Controller and Driver This pin is reset signal input. When the pin is low, initialization of the chip is executed. Keep this pin pull high during normal operation. Chip Select This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. Data/Command Control This pin is Data/Command control pin. When the pin is pulled high, the input at D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0 will be transferred to the command register. When the pin is pulled high and serial interface mode is selected, the data at SDIN will be interpreted as data. When it is pulled low, the data at SDIN will be transferred to the command register. In I2C mode, this pin acts as SA0 for slave address selection. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. 1.5 Pin Definition (Continued) Pin Number Symbol I/O Function Interface (Continued) 11 SCLK I 12 SDIN I/O Serial Clock Input Singal The transmission if information in the bus is following a clock signal. Each transmission of data bit is taken place during a single clock period of this pin. Serial Data Input Signal This pins acts as a communication channel. The input data through SDIN are latch at the rising edge of SCLK in fhe sequence of MSB first and converted to 8-bit parallel data and handled at the rising edge of last serial clock. SDIN is identified to display data or command by D/C bit data at the rising of first SCLK. 3 Ver:B 2. Absolute Maximum Ratings Parameter Symbol Min Max Unit Notes Supply Voltage for Logic VDD -0.3 4 V 1, 2 Supply Voltage for Display VCC 0 14 V 1, 2 Supply Voltage for DC/DC VBAT -0.3 5 V 1, 2 Operating Temperature TOP -40 85 °C Storage Temperature TSTG -40 85 °C 3 10,000 - hour 4 Life Time (80 cd/m ) 30,000 - hour 4 Life Time (60 cd/m2) 50,000 - hour 4 Life Time (120 cd/m2) 2 Note 1: All the above voltages are on the basis of “VSS = 0V”. Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur. Also, for normal operations, it is desirable to use this module under the conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate. Note 3: The defined temperature ranges do not include the polarizer. The maximum withstood temperature of the polarizer should be 80°C. Note 4: VCC = 9.0V, Ta = 25°C, 50% Checkerboard. Software configuration follows Section 4.4 Initialization. End of lifetime is specified as 50% of initial brightness reached. The average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions. 4 Ver:B 3. Optics & Electrical Characteristics 3.1 Optics Characteristics Characteristics Symbol Conditions Min Typ Max Unit Brightness (VCC Supplied Externally) Lbr Note 5 90 - - cd/m2 Lbr Note 6 90 110 - cd/m2 C.I.E. (White) (x) (y) C.I.E. 1931 0.24 0.27 0.27 0.30 0.30 0.33 Dark Room Contrast CR - 2000:1 - - Free - degree Min Typ Max Unit 1.65 3 3.3 V 8.5 9.0 9.5 V Brightness (VCC Generated by Internal DC/DC) Viewing Angle * Optical measurement taken at VDD = 3V, VCC = 9V&3.5V Software configuration follows Section 4.4 Initialization. 3.2 DC Characteristics Characteristics Symbol Supply Voltage for Logic VDD Supply Voltage for Display (Supplied Externally) VCC Supply Voltage for DC/DC Supply Voltage for Display (Generated by Internal DC/DC) VBAT Conditions Note 5 (Internal DC/DC Disable) High Level Input VIH Internal DC/DC Enable 3.5 Note 6 (Internal DC/DC Enable) IOUT = 100μA, 3.3MHz 0.8×VDD Low Level Input VIL IOUT = 100μA, 3.3MHz High Level Output VOH IOUT = 100μA, 3.3MHz 0.9×VDD - VDD V Low Level Output VOL IOUT = 100μA, 3.3MHz 0 - 0.1×VDD V Operating Current for VDD IDD - 180 300 μA Operating Current for VCC (VCC Supplied Externally) ICC Note 7 - 20.3 26 mA Operating Current for VBAT (VCC Generated by Internal DC/DC) IBAT Note 8 - 36.3 45.4 mA Sleep Mode Current for VDD IDD, SLEEP - 1 5 μA Sleep Mode Current for VCC ICC, SLEEP - 2 10 μA VCC 0 - 4.2 V 9 - V - VDD V - 0.2×VDD V Note 5 & 6: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer’s request. Note 7: VDD = 3V, VCC = 9V, IREF=390K 100% Display Area Turn on. Note 8: VDD = 3V, VBAT = 3.5V, IREF=390K 100% Display Area Turn on. * Software configuration follows Section 4.4 Initialization. 5 Ver:B 3.3 AC Characteristics 3.3.1.1 Serial Interface Timing Characteristics: (4-wire SPI) Symbol Description Min Max Unit Clock Cycle Time 100 - ns tAS Address Setup Time 15 - ns tAH Address Hold Time 15 - ns tCSS Chip Select Setup Time 20 - ns tCSH Chip Select Hold Time 10 - ns tDSW Write Data Setup Time 15 - ns tDHW Write Data Hold Time 15 - ns tCLKL Clock Low Time 20 - ns tCLKH Clock High Time 20 - ns tcycle tR Rise Time - 40 ns tF Fall Time - 40 ns * (VDD - VSS = 1.65V to 3.3V, Ta = 25°C) 6 Ver:B 3.3.1.2 4-wire Serial Interface with Internal Charge Pump 特别提醒(Special Tips):主板设计务必加电子开关, 否则, 可能引起漏电流现象 (When design main board, Please add Electronic Switch circuit, otherwise, will be caused leak current) C2N C1N C6 C7 C2P C1P 4-SPI R1 VBAT_IN Q1 Q2 GPIO VBAT VDD R2 C1 C2 IREF VCOMH VCC R3 C3 C4 C2P C2N C1P C1N VBAT VSS VDD CS RES DC SCLK SDIN IREF VCOMH VCC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C2P C2N C1P C1N VBAT VSS VDD CS RES D/C DCLK SDIN IREF VCOMH VCC VSS C5 Component_1 Recommended Components: C1 1μF / 6.3V, X7R C2: 2.2μF / 6.3V, X7R C3: 4.7μF / 25V, X7R C4: 2.2μF / 25V, X7R C5: 1μF / 25V, X7R C6, C7: 1μF / 16V, X5R R3: 390kΩ, R3 = (Voltage at IREF - VSS) / IREF R2, R1: 47kΩ Q1: FDN338P Q2: FDN335N Notes: VDD: 1.65~3.3V, it should be equal to MPU I/O voltage. VBAT_in: 3.5~4.2V 7 Ver:B 4. Functional Specification 4.1 Commands Refer to the Technical Manual for the CH1116 4.2 Power down and Power up Sequence To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation. 4.2.1 Power up Sequence: 1. 2. 3. 4. 5. 6. Power up VDD Send Display off command Initialization Clear Screen Power up VCC/ VBAT Delay 100ms (When VCC is stable) 7. Send Display on command VDD on B B VCC /VBAT on B B Display on VCC B VDD B VSS/Ground B B Display off 4.2.2 Power down Sequence: 1. Send Display off command 2. Power down VCC / VBAT 3. Delay 100ms (When VCC / VBAT is reach 0 and panel is completely discharges) 4. Power down VDD VCC / VBAT off B B B VDD off B B VCC/VBAT B B VDD B VSS/Ground B B Note 13: 1) Since an ESD protection circuit is connected between VDD and VCC inside the driver IC, VCC becomes lower than VDD whenever VDD is ON and VCC is OFF. 2) VCC / VBAT should be kept float (disable) when it is OFF. 3) Power Pins (VDD, VCC, VBAT) can never be pulled to ground under any circumstance. 4) VDD should not be power down before VCC / VBAT power down. 4.3 Reset Circuit When RES# input is low, the chip is initialized with the following status: 1. Display is OFF 2. 128×64 Display Mode 3. Normal segment and display data column and row address mapping (SEG0 mapped to column address 00h and COM0 mapped to row address 00h) 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 0 6. Column address counter is set at 0 7. Normal scan direction of the COM outputs 8. Contrast control register is set at 7Fh 9. Normal display mode (Equivalent to A4h command) 8 Ver:B 4.4 Actual Application Example Command usage and explanation of an actual example 4.4.1 VCC Supplied Externally VDD/VCC off State Set Display Offset 0xD3, 0x00 set VPP 0x33 Power up VDD (RES# as Low State) Set Display Start Line 0x40 Set Normal/Inverse Display 0xA6 Power Stabilized (Delay Recommended) Set Charge Pump 0xad, 0x8b Clear Screen Set RES# as High (3μs Delay Minimum) Set Segment Re-Map 0xA1 Power up VCC & Stabilized (Delay Recommended) Initialized State (Parameters as Default) Set COM Output Scan Direction 0xC8 Set Display On 0xAF Set Display Off 0xAE Set COM Pins Hardware Configuration 0xDA, 0x12 (100ms Delay Recommended) Initial Settings Configuration Set Contrast Control 0x81, 0XBF Display Data Sent Set Display Clock Divide Ratio/Oscillator Frequency 0xD5, 0x80 Set Pre-Charge Period 0xD9, 0X22 Set Multiplex Ratio 0xA8, 0x3F Set VCOMH Deselect Level 0xDB, 0x30 If the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function. 20 Ver:B Normal Operation Power down VCC (100ms Delay Recommended) Set Display Off 0xAE Power down VDD B VDD/VCC off State B Normal Operation Power down VCC Set Display Off 0xAE Sleep Mode Sleep Mode Set Display On 0xAF Power up VCC & Stabilized (Delay Recommended) (100ms Delay Recommended) Normal Operation External setting void Ch1116() { RES=1; delay(1000); RES=0; delay(1000); RES=1; delay(1000); write_i(0xAE); /*display off*/ write_i(0x02); write_i(0x10); /*set lower column address*/ /*set higher column address*/ write_i(0x40); /*set display start line*/ write_i(0xB0); /*set page address*/ 21 Ver:B write_i(0x81); write_i(0xBF); /*contract control*/ /*128*/ write_i(0xA1); /*set segment remap*/ write_i(0xA6); /*normal / reverse*/ write_i(0xA8); write_i(0x3F); /*multiplex ratio*/ /*duty = 1/64*/ write_i(0xad); write_i(0x8a); /*set charge pump enable*/ /* 0x8a 外供 VCC */ write_i(0x33); /*0X30---0X33 write_i(0xC8); set VPP 9V */ /*Com scan direction*/ write_i(0xD3); write_i(0x00); /*set display offset*/ /* 0x20 */ write_i(0xD5); write_i(0x80); /*set osc division*/ write_i(0xD9); write_i(0x22); /*set pre-charge period*/ /*0x22*/ write_i(0xDA); write_i(0x12); /*set COM pins*/ write_i(0xdb); write_i(0x30); /*set vcomh*/ clear(); write_i(0xAF); /*display ON*/ } void write_i(unsigned char { unsigned char m,da; unsigned int j; DC=0; CS=0; da=ins; for(j=0;j