NE555N

NE555 NE555Precision Timers 1 Features 3 Description • • • • These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. 1 • Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source Up to 200 mA On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. The threshold and trigger levels normally are twothirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flipflop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. 2 Applications • • • Fingerprint Biometrics Iris Biometrics RFID Reader The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs. 4 Simplified Schematic VCC 8 6 THRES 2 TRIG CONT 5 Î Î Î RESET 4 ÎÎ Î Î ÎÎ Î R1 R S Î Î Î Î Î Î 3 OUT 1 7 DISCH 1 GND http://www.hgsemi.com.cn 1 2014 OCT NE555 6 Pin Configuration and Functions NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) 1 8 2 7 3 6 4 5 NC GND NC VCC NC VCC DISCH THRES CONT NC TRIG NC OUT NC 4 3 2 1 20 19 18 5 17 6 16 7 15 14 9 10 11 12 13 8 NC DISCH NC THRES NC NC RESET NC CONT NC GND TRIG OUT RESET SE555...FK PACKAGE (TOP VIEW) NC – No internal connection Pin Functions PIN NAME D, P, PS, PW, JG FK I/O DESCRIPTION NO. CONT 5 12 I/O Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitor connection DISCH 7 17 O Open collector output to discharge timing capacitor GND 1 2 – Ground 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 – No internal connection NC OUT 3 7 O High current timer output signal RESET 4 10 I Active low reset input forces output and discharge low. THRES 6 15 I End of timing input. THRES > CONT sets output low and discharge low TRIG 2 5 I Start of timing input. TRIG < ½ CONT sets output high and discharge open VCC 8 20 – Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V) http://www.hgsemi.com.cn 2 2014 OCT NE555 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage (2) VI Input voltage IO Output current θJA CONT, RESET, THRES, TRIG Package thermal impedance (3) (4) θJC Package thermal impedance (5) (6) TJ Operating virtual junction temperature (1) (2) (3) (4) (5) (6) MAX UNIT 18 V VCC V ±225 mA D package 97 P package 85 PS package 95 PW package 149 FK package 5.61 JG package 14.5 °C/W °C/W 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1,6 mm (1/16 in) from case for 60 s JG package 300 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC) / θJC. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with MIL-STD-883. 7.2 Handling Ratings PARAMETER Tstg DEFINITION Storage temperature range MIN MAX UNIT –65 150 °C UNIT 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VI Input voltage IO Output current MIN MAX NA555, NE555, SA555 4.5 16 SE555 4.5 18 CONT, RESET, THRES, and TRIG NA555 TA Operating free-air temperature http://www.hgsemi.com.cn 3 –40 V VCC V ±200 mA 105 NE555 0 70 SA555 –40 85 SE555 –55 125 °C 2014 OCT NE555 7.4 Electrical Characteristics VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) PARAMETER THRES voltage level TEST CONDITIONS MIN TYP MAX MIN TYP MAX 9.4 10 10.6 8.8 10 11.2 VCC = 5 V 2.7 3.3 4 2.4 3.3 4.2 30 250 5 5.2 1.67 1.9 VCC = 15 V TRIG voltage level VCC = 5 V RESET voltage level RESET current 4.8 TA = –55°C to 125°C 3 1.45 5.6 1.1 1.67 2.2 0.5 2 0.3 0.7 1 nA V 0.9 0.7 1 1.1 μA V RESET at VCC 0.1 0.4 0.1 0.4 RESET at 0 V –0.4 –1 –0.4 –1.5 20 100 20 100 nA 0.15 0.4 V 9 10 11 2.6 3.3 4 0.1 0.25 0.4 0.75 2 2.5 VCC = 5 V, IO = 8 mA VCC = 5 V VCC = 15 V, IOL = 10 mA VCC = 15 V, IOL = 50 mA VCC = 15 V, IOL = 100 mA 9.6 TA = –55°C to 125°C 2.9 TA = –55°C to 125°C VCC = 5 V, IOL = 3.5 mA VCC = 5 V, IOL = 5 mA Output low, No load Supply current Output high, No load 3.3 3.8 0.1 0.15 0.4 0.5 2 2.2 1 TA = –55°C to 125°C 2.7 V 2.5 TA = –55°C to 125°C 2.5 0.35 0.1 0.2 0.15 0.25 TA = –55°C to 125°C 0.1 0.35 0.15 0.4 0.8 13 13.3 12.75 13.3 12 12.5 3 TA = –55°C to 125°C V 0.2 TA = –55°C to 125°C TA = –55°C to 125°C mA 3.8 TA = –55°C to 125°C VCC = 15 V, IOH = –200 mA VCC = 5 V, IOH = –100 mA 10.4 10.4 2.9 VCC = 5 V, IOL = 8 mA VCC = 15 V, IOH = –100 mA 10 9.6 VCC = 15 V, IOL = 200 mA (1) 0.5 TA = –55°C to 125°C VCC = 15 V High-level output voltage 250 5 V 1.9 0.3 CONT voltage (open circuit) Low-level output voltage 30 4.5 6 TA = –55°C to 125°C TRIG at 0 V DISCH switch off-state current DISCH switch on-state voltage UNIT VCC = 15 V THRES current (1) TRIG current NA555 NE555 SA555 SE555 12.5 3.3 2.75 V 3.3 2 VCC = 15 V 10 12 10 VCC = 5 V 3 5 3 15 6 VCC = 15 V 9 10 9 13 VCC = 5 V 2 4 2 5 mA This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB ≉ 3.4 MΩ, and for VCC = 15 V, the maximum value is 10 MΩ. http://www.hgsemi.com.cn 4 2014 OCT NE555 7.5 Operating Characteristics VCC = 5 V to 15 V, TA = 25°C (unless otherwise noted) PARAMETER MIN Initial error of timing interval (2) Temperature coefficient of timing interval Each timer, monostable (3) Each timer, astable TA = 25°C (5) Each timer, monostable (3) TYP MAX 0.5 1.5 (4) 1.5 TA = MIN to MAX Each timer, astable (5) (3) Supply-voltage sensitivity of Each timer, monostable (5) timing interval Each timer, astable NA555 NE555 SA555 SE555 TEST CONDITIONS (1) 30 0.05 TYP MAX 1 3 2.25 100 (4) 90 TA = 25°C MIN UNIT 50 ppm/ °C 150 0.2 (4) 0.15 0.1 % 0.5 0.3 %/V Output-pulse rise time CL = 15 pF, TA = 25°C 100 200 (4) 100 300 ns Output-pulse fall time CL = 15 pF, TA = 25°C 100 200 (4) 100 300 ns (1) (2) (3) (4) (5) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 kΩ to 100 kΩ, C = 0.1 μF. On products compliant to MIL-PRF-38535, this parameter is not production tested. Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 kΩ to 100 kΩ, C = 0.1 μF. http://www.hgsemi.com.cn 5 2014 OCT NE555 7.6 Typical Characteristics Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. 10 7 VCC = 5 V 4 2 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V 10 7 TA = −55°C 1 0.7 TA = 25°C 0.4 TA = 125°C 0.2 0.1 0.07 0.04 VCC = 10 V 4 2 TA = 25°C 1 0.7 TA= −55°C 0.4 TA = 125°C 0.2 0.1 0.07 0.04 0.02 0.02 0.01 0.01 1 2 4 7 10 20 40 1 70 100 Figure 1. Low-Level Output Voltage vs Low-Level Output Current 7 10 20 40 70 100 Figure 2. Low-Level Output Voltage vs Low-Level Output Current TA = −55°C VCC = 15 V 1.8 4 TA = −55°C ( VCC − VOH) − Voltage Drop − V VOL − Low-Level Output Voltage − V 4 2.0 10 7 2 1 0.7 0.4 TA = 25°C 0.2 TA = 125°C 0.1 0.07 0.04 0.02 1.6 TA = 25°C 1.4 1.2 TA = 125°C 1 0.8 0.6 0.4 0.2 0.01 1 2 4 7 10 20 40 0 70 100 VCC = 5 V to 15 V 1 2 4 7 10 20 40 70 100 IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 3. Low-Level Output Voltage vs Low-Level Output Current Figure 4. Drop Between Supply Voltage and Output vs High-Level Output Current Pulse Duration Relative to Value at VCC = 10 V 10 Output Low, No Load 9 8 I CC − Supply Current − mA 2 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA TA = 25°C 7 6 5 TA = −55°C 4 TA = 125°C 3 2 1 1.015 1.010 1.005 1 0.995 0.990 8 0.985 0 5 6 7 8 9 10 11 12 13 14 0 15 5 10 15 20 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 5. Supply Current vs Supply Voltage Figure 6. Normalized Output Pulse Duration (Monostable Operation) vs Supply Voltage http://www.hgsemi.com.cn 6 2014 OCT NE555 Typical Characteristics (continued) Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. 1000 VCC = 10 V 900 TA = 125°C 1.010 t PD – Propagation Delay Time – ns Pulse Duration Relative to Value at TA = 25 C 1.015 1.005 1 0.995 0.990 8 800 700 TA = 70°C 600 500 TA = 25°C 400 300 T A = 0° C 200 TA = –55°C 100 0.985 −75 8 −50 −25 0 25 50 75 0 100 125 0 TA − Free-Air Temperature − °C Figure 7. Normalized Output Pulse Duration (Monostable Operation) vs Free-Air Temperature http://www.hgsemi.com.cn 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Lowest Level of Trigger Pulse – ×VCC 0.4 Figure 8. Propagation Delay Time vs Lowest Voltage Level of Trigger Pulse 7 2014 OCT NE555 8 Detailed Description 8.1 Overview The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from < 1mHz to 100 kHz. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. Maximum output sink and discharge sink current is greater for higher VCC and less for lower VCC. 8.2 Functional Block Diagram VCC 8 6 THRES 2 TRIG CONT 5 Î Î Î Î Î Î Î Î Î RESET 4 Î Î Î Î Î Î Î R1 R 3 OUT 1 S 7 DISCH 1 GND A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES. 8.3 Feature Description 8.3.1 Mono-stable Operation For mono-stable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1. http://www.hgsemi.com.cn 8 2014 OCT NE555 Feature Description (continued) VCC (5 V to 15 V) RA Î Î Î 4 7 6 Input 2 5 8 CONT VCC RL RESET DISCH OUT 3 Output THRES TRIG GND 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 9. Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC. 10 RA = 10 MΩ 1 tw − Output Pulse Duration − s Voltage − 2 V/div RA = 9.1 kΩ CL = 0.01 µF RL = 1 kΩ See Figure 9 Input Voltage ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Output Voltage 10−1 10−2 10−3 RA = 100 kΩ RA = 10 kΩ 10−4 RA = 1 kΩ 10−5 0.001 Capacitor Voltage 0.01 0.1 1 10 100 C − Capacitance − µF Time − 0.1 ms/div Figure 10. Typical Monostable Waveforms http://www.hgsemi.com.cn RA = 1 MΩ Figure 11. Output Pulse Duration vs Capacitance 9 2014 OCT NE555 Feature Description (continued) 8.3.2 A-stable Operation As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB. ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈ 0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the mono-stable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. VCC (5 V to 15 V) Î Î Î 0.01 µF Open (see Note A) 5 8 VCC CONT 4 7 RB 6 2 RL RESET DISCH 3 OUT Output THRES t H TRIG tL GND C RL = 1 kW See Figure 12 Voltage − 1 V/div RA RA = 5 kW RB = 3 kW C = 0.15 µF Output Voltage 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Figure 12. Circuit for Astable Operation Capacitor Voltage Time − 0.5 ms/div Figure 13. Typical Astable Waveforms Figure 12 shows typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL can be calculated as follows: tH = 0.693 (R A + RB )C (1) tL = 0.693 (RB )C (2) Other useful relationships are shown below: period = tH + tL = 0.693 (R A + 2RB )C (3) 1.44 frequency » (R A +2RB )C (4) tL RB Output driver duty cycle = = tH + tL R A + 2RB (5) Output waveform duty cycle = Low-to-high ratio = http://www.hgsemi.com.cn tH RB = 1tH + tL R A + 2RB (6) tL RB = tH R A + RB (7) 10 2014 OCT NE555 Feature Description (continued) 100 k RA + 2 RB = 1 kΩ f − Free-Running Frequency − Hz RA + 2 RB = 10 kΩ 10 k RA + 2 RB = 100 kΩ 1k 100 10 1 RA + 2 RB = 1 MΩ RA + 2 RB = 10 MΩ 0.1 0.001 0.01 0.1 1 10 100 C − Capacitance − µF Figure 14. Free-Running Frequency 8.3.3 Frequency Divider By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure 15 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during the timing cycle. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Voltage − 2 V/div VCC = 5 V RA = 1250 Ω C = 0.02 µF See Figure 9 Input Voltage Output Voltage Capacitor Voltage Time − 0.1 ms/div Figure 15. Divide-by-Three Circuit Waveforms 8.4 Device Functional Modes Table 1. Function Table (1) RESET TRIGGER VOLTAGE (1) THRESHOLD VOLTAGE (1) OUTPUT DISCHARGE SWITCH Low Irrelevant Irrelevant Low On High 1/3 VCC >2/3 VCC Low On High >1/3 VCC [maximum normal input high time]. RL improves VOH, but it is not required for TTL compatibility. http://www.hgsemi.com.cn 12 2014 OCT NE555 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Typical Applications (continued) 9.2.1.3 Application Curves Voltage − 2 V/div VCC = 5 V RA = 1 kΩ C = 0.1 µF See Figure 15 Input Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage Capacitor Voltage Time − 0.1 ms/div Figure 17. Completed Timing Waveforms for Missing-Pulse Detector 9.2.2 Pulse-Width Modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used. VCC (5 V to 15 V) 4 RESET Clock Input 2 RL 8 VCC OUT TRIG RA 3 Output 7 DISCH Modulation 5 Input (see Note A) CONT THRES 6 GND C 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 18. Circuit for Pulse-Width Modulation http://www.hgsemi.com.cn 13 2014 OCT NE555 Typical Applications (continued) 9.2.2.1 Design Requirements Clock input must have VOL and VOH levels that are less than and greater than 1/3 VCC. Modulation input can vary from ground to VCC. The application must be tolerant of a nonlinear transfer function; the relationship between modulation input and pulse width is not linear because the capacitor charge is based RC on an negative exponential curve. 9.2.2.2 Detailed Design Procedure Choose RA and C so that RA × C = 1/4 [clock input period]. RL improves VOH, but it is not required for TTL compatibility. 9.2.2.3 Application Curves ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ RA = 3 kΩ C = 0.02 µF RL = 1 kΩ See Figure 18 Voltage − 2 V/div Modulation Input Voltage Clock Input Voltage Output Voltage Capacitor Voltage Time − 0.5 ms/div Figure 19. Pulse-Width-Modulation Waveforms 9.2.3 Pulse-Position Modulation As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. http://www.hgsemi.com.cn 14 2014 OCT NE555 Typical Applications (continued) VCC (5 V to 15 V) 4 8 RESET 2 VCC OUT RA 3 Output TRIG DISCH Modulation Input 5 (see Note A) RL CONT THRES 7 6 RB GND C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 20. Circuit for Pulse-Position Modulation 9.2.3.1 Design Requirements Both DC and AC coupled modulation input will change the upper and lower voltage thresholds for the timing capacitor. Both frequency and duty cycle will vary with the modulation voltage. 9.2.3.2 Detailed Design Procedure The nominal output frequency and duty cycle can be determined using formulas in A-stable Operation section. RL improves VOH, but it is not required for TTL compatibility. http://www.hgsemi.com.cn 15 2014 OCT NE555 Typical Applications (continued) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 9.2.3.3 Application Curves Voltage − 2 V/div RA = 3 kΩ RB = 500 Ω RL = 1 kΩ See Figure 20 Modulation Input Voltage Output Voltage Capacitor Voltage Time − 0.1 ms/div Figure 21. Pulse-Position-Modulation Waveforms 9.2.4 Sequential Timer Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22 shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output waveforms. VCC 4 RESET 2 TRIG S 8 VCC 3 OUT DISCH 5 0.01 µF CONT 7 4 RESET RA 33 kΩ 2 0.001 µF CA = 10 µF RA = 100 kΩ RB CONT 0.01 µF Output A THRES GND 1 CB CB = 4.7 µF RB = 100 kΩ 4 RESET 33 kΩ 2 0.001 µF DISCH 7 5 6 THRES GND 1 CA TRIG 8 VCC 3 OUT DISCH 5 6 0.01 µF Output B TRIG 8 VCC 3 OUT CONT THRES GND 1 CC CC = 14.7 µF RC = 100 kΩ RC 7 6 Output C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. Figure 22. Sequential Timer Circuit http://www.hgsemi.com.cn 16 2014 OCT NE555 Typical Applications (continued) 9.2.4.1 Design Requirements The sequential timer application chains together multiple mono-stable timers. The joining components are the 33kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next monostable. 9.2.4.2 Detailed Design Procedure The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ 9.2.4.3 Application Curves See Figure 22 Voltage − 5 V/div Output A twA twA = 1.1 RACA twB Output B twB = 1.1 RBCB Output C twC twC = 1.1 RCCC t=0 t − Time − 1 s/div Figure 23. Sequential Timer Waveforms 10 Power Supply Recommendations The devices are designed to operate from an input voltage supply range between 4.5 V and 16 V. (18 V for SE555). A bypass capacitor is highly recommended from VCC to ground pin; ceramic 0.1 µF capacitor is sufficient. http://www.hgsemi.com.cn 17 2014 OCT