74ALVCH16952DGGS

74ALVCH16952 16-bit registered transceiver; 3-state Rev. 3 — 9 January 2018 1 Product data sheet General description The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. 2 Features and benefits • CMOS low-power consumption • Multibyte flow-through pinout architecture • Low inductance, multiple center power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • Output drive capability 50 Ω transmission lines at 85 °C • Complies with JEDEC standard JESD8-B 3 Ordering information Table 1. Ordering information Type number 74ALVCH16952DGG Package Temperature range Name Description Version -40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 4 Functional diagram 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 56 1 1OEBA 1OEAB 1CEAB 3 54 2 1CEBA 1CPAB 1CPBA 55 1B0 2A0 1B1 2A1 1B2 2A2 1B3 2A3 1B4 2A4 1B5 2A5 1B6 2A6 1B7 2A7 15 42 16 41 17 40 19 38 20 37 22 36 23 34 24 33 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 29 28 26 31 27 30 2OEBA 2OEAB 2CEAB 2CEBA 2CPAB 2CPBA 001aae552 Figure 1. Logic symbol 1OEBA 1CEBA 1CPBA 1OEAB 1CEAB 1CPAB 56 54 55 1 3 2 29 2OEBA 31 2CEBA 30 2CPBA 28 2OEAB 26 2CEAB 27 2CPAB 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 5 6 1EN3 G1 1C5 EN4 G2 2C6 EN9 G7 7C11 EN10 G8 8C12 3 6D 5D 4 52 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 9 12D 11D 10 41 17 40 19 38 20 37 21 36 23 34 24 33 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 VCC 2B0 2B1 2B2 2B3 data input 2B5 2B6 2B7 001aad245 001aae550 Figure 2. IEC logic symbol 74ALVCH16952 Product data sheet to internal circuit 2B4 Figure 3. Bus hold circuit All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state CEAB CPAB OEAB CEBA CPBA OEBA A0 Q D CP Q D B0 CP 8 IDENTICAL CHANNELS TO 7 OTHER CHANNELS 001aae549 Figure 4. Schematic diagram (one section) 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 5 Pinning information 5.1 Pinning 74ALVCH16952 1OEAB 1 56 1OEBA 1CPAB 2 55 1CPBA 1CEAB 3 54 1CEBA GND 4 53 GND 1A0 5 52 1B0 1A1 6 51 1B1 VCC 7 50 VCC 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 GND 11 46 GND 1A5 12 45 1B5 1A6 13 44 1B6 1A7 14 43 1B7 2A0 15 42 2B0 2A1 16 41 2B1 2A2 17 40 2B2 GND 18 39 GND 2A3 19 38 2B3 2A4 20 37 2B4 2A5 21 36 2B5 VCC 22 2A6 23 35 VCC 2A7 24 33 2B7 GND 25 32 GND 34 2B6 2CEAB 26 31 2CEBA 2CPAB 27 30 2CPBA 2OEAB 28 29 2OEBA 001aae551 Figure 5. Pin configuration 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 4 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7 5, 6, 8, 9, 10, 12, 13, 14 data inputs or outputs 1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7 52, 51, 49, 48, 47, 45, 44, 43 data inputs or outputs 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7 15, 16, 17, 19, 20, 21, 23, 24 data inputs or outputs 2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7 42, 41, 40, 38, 37, 36, 34, 33 data inputs or outputs 1OEAB, 1OEBA, 2OEAB, 2OEBA 1, 56, 28, 29 output enable input (active LOW) 1CEAB, 1CEBA, 2CEAB, 2CEBA 3, 54, 26, 31 clock enable input (active LOW) 1CPAB, 1CPBA, 2CPAB, 2CPBA 2, 55, 27, 30 clock pulse input (LOW-to-HIGH, edge-triggered) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6 Functional description Table 3. Function table [1] Operating mode Control A to B, B to A nOEAB, nOEBA nCEAB, nCEBA Hold L Load and output enable L Load and output disable H Input Internal Output nCPAB, nCPBA nAn, nBn nQn nBn, nAn H X X NC NC L ↑ L L L H H H L L Z H H Z L ↑ [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH clock transition; X = don’t care; Z = high impedance OFF-state; NC = no change. 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 5 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC Conditions supply voltage VI input voltage Min Max Unit -0.5 +4.6 V control pins [1] -0.5 +4.6 V data inputs [1] -0.5 VCC + 0.5 V [1] -0.5 VCC + 0.5 V VO output voltage IIK input clamping current VI < 0 V - -50 mA IOK output clamping current VO > VCC or VO < 0 V - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C - 600 mW Min Typ Max Unit CL = 30 pF 2.3 - 2.7 V CL = 50 pF 3.0 - 3.6 V Ptot total power dissipation [2] Tamb = -40 °C to +125 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP56 package: Ptot derates linearly with 8 mW/K above 55 °C. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC maximum speed performance supply voltage VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature operating in free-air -40 - +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 6 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 9 Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = -40 °C to +85 °C Min VIH VIL VOH VOL Typ [1] Unit Max HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL VCC = 2.3 V to 3.6 V; IO = -100 μA VCC - 0.2 VCC - V VCC = 2.3 V; IO = -6 mA VCC - 0.3 VCC - 0.08 - V VCC = 2.3 V; IO = -12 mA VCC - 0.6 VCC - 0.26 - V VCC = 2.7 V; IO = -12 mA VCC - 0.5 VCC - 0.14 - V VCC = 3.0 V; IO = -12 mA VCC - 0.6 VCC - 0.09 - V VCC = 3.0 V; IO = -24 mA VCC - 1.0 VCC - 0.28 - V LOW-level output voltage VI = VIH or VIL VCC = 2.3 V to 3.6 V; IO = 100 μA - GND 0.20 V VCC = 2.3 V; IO = 6 mA - 0.07 0.40 V VCC = 2.3 V; IO = 12 mA - 0.15 0.70 V VCC = 2.7 V; IO = 12 mA - 0.14 0.40 V VCC = 3.0 V; IO = 24 mA - 0.27 0.55 V II input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 μA IOZ OFF-state output current VCC = 2.7 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW sustaining current VCC = 2.3 V; VI = 0.7 V 45 - - μA VCC = 3.0 V; VI = 0.8 V 75 150 - μA bus hold HIGH sustaining current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V -500 - - μA Ci input capacitance - 3.0 - pF IBHH [1] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 7 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 10 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C; For test circuit, see Figure 9. Symbol Parameter tpd propagation delay Conditions Min nCPBA to nAn; nCPAB to nBn; see Figure 6 enable time tw tsu disable time pulse width set-up time Max Unit VCC = 2.3 V to 2.7 V 1.0 3.2 4.1 ns VCC = 2.7 V 1.0 - 4.6 ns 1.0 3.2 3.9 ns VCC = 2.3 V to 2.7 V 1.0 - 5.4 ns VCC = 2.7 V 1.0 - 5.3 ns 1.0 - 4.4 ns VCC = 2.3 V to 2.7 V 1.0 - 5.3 ns VCC = 2.7 V 1.4 - 4.4 ns VCC = 3.0 V to 3.6 V 1.1 - 4.0 ns VCC = 2.3 V to 2.7 V 3.3 - - ns VCC = 2.7 V 3.3 - - ns VCC = 3.0 V to 3.6 V 3.3 - - ns VCC = 2.3 V to 2.7 V 1.7 - - ns VCC = 2.7 V 1.9 - - ns VCC = 3.0 V to 3.6 V 1.5 - - ns VCC = 2.3 V to 2.7 V 1.2 - - ns VCC = 2.7 V 1.0 - - ns VCC = 3.0 V to 3.6 V 1.0 - - ns VCC = 2.3 V to 2.7 V 0.6 - - ns VCC = 2.7 V 0.6 - - ns VCC = 3.0 V to 3.6 V 0.8 - - ns VCC = 2.3 V to 2.7 V 1.1 - - ns VCC = 2.7 V 0.9 - - ns VCC = 3.0 V to 3.6 V 1.1 - - ns nOEBA to nAn; nOEAB to nBn; see Figure 8 [3] VCC = 3.0 V to 3.6 V tdis [1] [2] VCC = 3.0 V to 3.6 V ten Typ nOEBA to nAn; nOEAB to nBn; see Figure 8 [4] nCPAB; nCPBA; HIGH or LOW; see Figure 6 nAn to nCPAB or nBn to nCPBA; see Figure 7 nCEAB to nCPAB or nCEBA to nCPBA; see Figure 7 th hold time nAn to nCPAB or nBn to nCPBA; see Figure 7 nCEAB to nCPAB or nCEBA to nCPBA; see Figure 7 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 8 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state Symbol Parameter Conditions fmax CP; see Figure 6 maximum frequency Min power dissipation capacitance [1] Max Unit VCC = 2.3 V to 2.7 V 150 350 - MHz VCC = 2.7 V 150 350 - MHz 150 350 - MHz - 30 - pF VCC = 3.0 V to 3.6 V CPD Typ [5] per driver; VI = GND to VCC [1] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V [2] tpd is the same as tPHL and tPLH. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N +∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 10.1 Waveforms and test circuit 1/f max VI input nCPBA or nCPAB VM VM VM 0V tW tW t PHL t PLH VOH output nAn or nBn VM VOL VM 001aae95 6 Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 6. Propagation delay clock input (nCPAB, nCPBA) to output (nBn, nAn), clock pulse width and maximum clock pulse frequency 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 9 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state VI input nAn or nBn nCEAB nCEBA VM 0V th th t su t su VI input nCPAB or nCPBA VM 0V 001aae547 Measurements points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 7. Setup and hold times VI input nOEAB nOEBA VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled 001aae548 Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 8. 3-state enable and disable time Table 8. Measurement points Supply voltage Input VCC VI VM VM VX VY 2.3 V to 2.7 V VCC 0.5 V 0.5 V VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVCH16952 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 10 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr VI tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Figure 9. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH16952 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 11 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 11 Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 10. Package outline SOT364-1 (TSSOP56) 74ALVCH16952 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 © Nexperia B.V. 2018. All rights reserved. 12 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state 12 Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16952 v.3 20180109 Product data sheet - 74ALVCH16952 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74ALVCH16952 v.2 20060427 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors • The symbol of pin numbers 15, 16, 17, 19, 20, 21, 23 and 24 is rectified 74ALVCH16952 v.1 19980901 74ALVCH16952 Product data sheet Product data sheet Preliminary specification - - All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 January 2018 74ALVCH16952 v.1 - © Nexperia B.V. 2018. All rights reserved. 13 / 14 74ALVCH16952 Nexperia 16-bit registered transceiver; 3-state Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 5 Functional description ........................................5 Limiting values .................................................... 6 Recommended operating conditions ................ 6 Static characteristics .......................................... 7 Dynamic characteristics .....................................8 Waveforms and test circuit ................................ 9 Package outline .................................................12 Abbreviations .................................................... 13 Revision history ................................................ 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 January 2018 Document identifier: 74ALVCH16952