LM555M/TR

LM555 LM555 General-purpose single bipolar timers Features ■ Low turn-off time ■ Maximum operating frequency greater than 500 kHz ■ Timing from microseconds to hours ■ Operates in both astable and monostable modes ■ Output can source or sink up to 200 mA ■ Adjustable duty cycle ■ TTL compatible ■ Temperature stability of 0.005% per °C N DIP8 (Plastic package) D SO8 (Plastic micropackage) Description The LM555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA. Pin connections (top view) 1 8 2 7 3 6 4 5 1 - GND 2 - Trigger 3 - Output 4 - Reset http://www.hgsemi.com.cn 1 5 - Control voltage 6 - Threshold 7 - Discharge 8 - VCC 2018 JUN LM555 1 Schematic diagrams Figure 1. Block diagram VCC+ 5kΩ COMP THRESHOLD CONTROL VOLTAGE DISCHARGE R FLIP-FLOP 5kΩ Q COMP OUT TRIGGER S INHIBIT/ RESET 5kΩ S RESET S - 8086 Figure 2. Schematic diagram CONTROL VOLTAGE OUTPUT THRESHOLD COMPARATOR 5 VCC R2 830W R1 4.7kW R4 R8 1kW 5kW R3 4.7kW R12 6.8kW Q21 Q5 Q6 Q7 Q8 Q19 Q9 Q22 Q20 R13 3.9kW R11 5kW THRESHOLD Q1 Q2 Q3 Q11 Q12 TRIGGER 2 Q23 R9 5kW D2 RESET 4 Q24 Q18 R16 100W R15 4.7kW Q17 R5 10kW R6 100kW R7 100kW R10 5kW 1 TRIGGER COMPARATOR http://www.hgsemi.com.cn R14 220W Q15 7 Q14 GND 3 Q13 Q10 Q16 DISCHARGE D1 R17 4.7kW Q4 2 FLIP FLOP 2018 JUN LM555 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Parameter Value Unit 18 V ±225 mA VCC Supply voltage IOUT Output current (sink & source) Rthja Thermal resistance junction to ambient(1) DIP8 SO-8 85 125 °C/W Rthjc Thermal resistance junction to case (1) DIP8 SO-8 41 40 °C/W Human body model (HBM)(2) (3) ESD TLEAD Tj Tstg 1000 Machine model (MM) 100 Charged device model (CDM)(4) 1500 Latch-up immunity 200 mA Lead temperature (soldering 10 seconds) 260 °C Junction temperature 150 °C -65 to 150 °C Storage temperature range V 1. Short-circuits can cause excessive heating. These values are typical. 2. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 3. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of connected pin combinations while the other pins are floating. 4. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. Table 2. Operating conditions Symbol VCC Vth, Vtrig, Vcl, Vreset IOUT Parameter Value Unit 4.5 to 16 V Maximum input voltage VCC V Output current (sink and source) ±200 mA 0 to 70 °C Supply voltage LM555 Operating free air temperature range Toper http://www.hgsemi.com.cn LM555 3 2018 JUN LM555 3 Electrical characteristics Table 3. Tamb = +25° C, VCC = +5 V to +15 V (unless otherwise specified) LM555 Symbol Parameter Unit Min. ICC Typ. Max. 3 10 2 Timing error (monostable) (RA = 2kΩ to 100kΩ, C = 0.1μF) Initial accuracy (1) Drift with temperature Drift with supply voltage 0.5 30 0.05 Timing error (astable) (RA, RB = 1kΩ to 100kΩ, C = 0.1μF, VCC = +15V) Initial accuracy (1) Drift with temperature Drift with supply voltage 1.5 90 0.15 Supply current (RL = ∝) Low state VCC = +5V VCC = +15V High state VCC = +5V Min. Typ. Max. 5 12 3 10 2 6 15 2 100 0.2 1 50 0.1 3 0.5 2.25 150 0.3 mA % ppm/°C %/V % ppm/°C %/V VCL Control voltage level VCC = +15V VCC = +5V 9.6 2.9 10 3.33 10.4 3.8 9 2.6 10 3.33 11 4 V Vth Threshold voltage VCC = +15V VCC = +5V 9.4 2.7 10 3.33 10.6 4 8.8 2.4 10 3.33 11.2 4.2 V Ith Threshold current (2) 0.1 0.25 0.1 0.25 µA 5 1.67 5.2 1.9 5 1.67 5.6 2.2 V 0.5 0.9 0.5 2.0 µA 0.7 1 0.7 1 V mA Vtrig Trigger voltage VCC = +15V VCC = +5V Itrig Trigger current (Vtrig = 0V) 4.8 1.45 4.5 1.1 Vreset Reset voltage (3) Ireset Reset current Vreset = +0.4V Vreset = 0V 0.1 0.4 0.4 1 0.1 0.4 0.4 1.5 VOL Low level output voltage VCC = +15V IO(sink) = 10mA IO(sink) = 50mA IO(sink) = 100mA IO(sink) = 200mA VCC = +5V IO(sink) = 8mA IO(sink) = 5mA 0.1 0.4 2 2.5 0.1 0.05 0.15 0.5 2.2 0.1 0.4 2 2.5 0.3 0.25 0.25 0.75 2.5 VOH 0.4 High level output voltage VCC = +15V IO(sink) = 200mA IO(sink) = 100mA VCC = +5V IO(sink) = 100mA http://www.hgsemi.com.cn 13 3 4 12.5 13.3 3.3 0.4 0.25 0.2 12.75 2.75 12.5 13.3 3.3 V 0.4 0.35 V 2018 JUN LM555 Table 3. Tamb = +25° C, VCC = +5 V to +15 V (unless otherwise specified) (continued) LM555 Symbol Parameter Unit Min. Typ. Max. 20 Min. Typ. Max. 100 20 100 Idis(off) Discharge pin leakage current (output high) Vdis = 10V Vdis(sat) Discharge pin saturation voltage (output low) (4) VCC = +15V, Idis = 15mA VCC = +5V, Idis = 4.5mA 180 80 480 200 180 80 480 200 Output rise time Output fall time 100 100 200 200 100 100 300 300 Turn off time (5) (Vreset = VCC) 0.5 tr tf toff nA mV ns 0.5 µs 1. Tested at VCC = +5 V and VCC = +15 V. 2. This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 MΩ for +15 V operation and 3.5 MΩ for +5 V operation. 3. Specified with trigger input high. 4. No protection against excessive pin 7 current is necessary, providing the package dissipation rating is not exceeded. 5. Time measured from a positive pulse (from 0 V to 0.8 x VCC) on the Threshold pin to the transition from high to low on the output pin. Trigger is tied to threshold. http://www.hgsemi.com.cn 5 2018 JUN LM555 Figure 3. Minimum pulse width required for triggering Figure 4. Supply current versus supply voltage Figure 5. Delay time versus temperature Figure 6. Low output voltage versus output sink current Figure 7. Low output voltage versus output sink current Figure 8. Low output voltage versus output sink current http://www.hgsemi.com.cn 6 2018 JUN LM555 Figure 9. High output voltage drop versus output Figure 10. Delay time versus supply voltage Figure 11. Propagation delay versus voltage level of trigger value http://www.hgsemi.com.cn 7 2018 JUN LM555 4 Application information 4.1 Monostable operation In the monostable mode, the timer generates a single pulse. As shown in Figure 12, the external capacitor is initially held discharged by a transistor inside the timer. Figure 12. Typical schematics in monostable operation VCC = 5 to 15V Reset R1 8 4 Trigger 7 2 LM555 Output 6 5 3 1 C1 Control Voltage 0.01μF The circuit triggers on a negative-going input signal when the level reaches 1/3 VCC. Once triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered again during this interval. The duration of the output HIGH state is given by t = 1.1 R1C1 and is easily determined by Figure 14. Note that because the charge rate and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. Applying a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2) during the timing cycle discharges the external capacitor and causes the cycle to start over. The timing cycle now starts on the positive edge of the reset pulse. During the time the reset pulse is applied, the output is driven to its LOW state. When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the shortcircuit across the external capacitor and driving the output HIGH. The voltage across the capacitor increases exponentially with the time constant t = R1C1. When the voltage across the capacitor equals 2/3 VCC, the comparator resets the flip-flop which then discharges the capacitor rapidly and drives the output to its LOW state. Figure 13 shows the actual waveforms generated in this mode of operation. When Reset is not used, it should be tied high to avoid any possibility of unwanted triggering. http://www.hgsemi.com.cn 8 2018 JUN LM555 Figure 13. Waveforms in monostable operation t = 0.1 ms / div INPUT = 2.0V/div OUTPUT VOLTAGE = 5.0V/div CAPACITOR VOLTAGE = 2.0V/div R1 = 9.1kΩ, C1 = 0.01μF, RL = 1kΩ Figure 14. Pulse duration versus R1C1 0.01 0.001 10 μs 4.2 Ω 10 M 0.1 10 k R 1= 1.0 Ω 10 0k Ω 1M Ω 1k Ω C (μF) 10 100 μs 1.0 ms 10 ms 100 ms 10 s (t d ) Astable operation When the circuit is connected as shown in Figure 15 (pins 2 and 6 connected) it triggers itself and free runs as a multi-vibrator. The external capacitor charges through R1 and R2 and discharges through R2 only. Thus the duty cycle can be set accurately by adjusting the ratio of these two resistors. In the astable mode of operation, C1 charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times and, therefore, frequency are independent of the supply voltage. http://www.hgsemi.com.cn 9 2018 JUN LM555 Figure 15. Typical schematics in astable operation VCC = 5 to 15V R1 8 4 Output 3 7 LM555 Control Voltage R2 6 5 0.01μF 1 2 C1 Figure 16 shows the actual waveforms generated in this mode of operation. The charge time (output HIGH) is given by: t1 = 0.693 (R1 + R2) C1 and the discharge time (output LOW) by: t2 = 0.693 (R2) C1 Thus the total period T is given by: T = t1 + t2 = 0.693 (R1 + 2R2) C1 The frequency of oscillation is then: 1 1.44 f = --- = --------------------------------------T ( R1 + 2R2 )C1 It can easily be found from Figure 17. The duty cycle is given by: R2 D = ------------------------R1 + 2R2 http://www.hgsemi.com.cn 10 2018 JUN LM555 Figure 16. Waveforms in astable operation t = 0.5 ms / div OUTPUT VOLTAGE = 5.0V/div CAPACITOR VOLTAGE = 1.0V/div R1 = R2 = 4.8kΩ, C1= 0.1μF, RL = 1kΩ Figure 17. Free running frequency versus R1, R2 and C1 C (μF) 10 1.0 R 1 1k Ω 10 kΩ + 0.1 0.01 0.001 0.1 http://www.hgsemi.com.cn 1 R2 1M = 10 M 10 11 10 0k Ω Ω Ω 100 1k 10k f o (Hz) 2018 JUN LM555 4.3 Pulse width modulator When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to pin 5. Figure 18 shows the circuit. Figure 18. Pulse width modulator VCC RA 8 4 Trigger 7 2 LM555 6 Modulation Input 5 3 Output C 1 4.4 Linear ramp When the pull-up resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is generated. Figure 19 shows a circuit configuration that will perform this function. Figure 19. Linear ramp VCC RE 8 4 Trigger R1 7 2 LM555 2N4250 or equiv. 6 C Output 5 3 0.01μF R2 1 http://www.hgsemi.com.cn 12 2018 JUN LM555 Figure 20 shows the waveforms generator by the linear ramp. The time interval is given by: (2/3 Vcc RE (R1+R2) C T = ---------------------------------------------------------------- VBE = 0.6V R1 Vcc - VBE (R1+R2) Figure 20. Linear ramp VCC = 5 V Time: 20 µs/DIV R1 + 47 kΩ R2 = 100 kΩ RE = 2.7 kΩ C = 0.01 µF 4.5 Top trace: input 3 V/DIV Middle trace: output 5 V/DIV Bottom trace: output 5 V/DIV Bottom trace: capacitor voltage 1 V/DIV 50% duty cycle oscillator For a 50% duty cycle, the resistors RA and RB can be connected as in Figure 21. The time period for the output high is the same as for astable operation (see Section 4.2 on page 9): t1 = 0.693 RA C For the output low it is RB – 2RA t 2 = [(R. RB)/(RA+RB)].C.Ln --------------------------2RB – RA Thus the frequency of oscillation is: 1 f = ---------------t1 + t2 http://www.hgsemi.com.cn 13 2018 JUN LM555 Figure 21. 50% duty cycle oscillator VCC VCC RA 51kΩ 4 8 RB 7 2 22kΩ LM555 Out 6 5 3 1 0.01μF C 0.01μF Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator. 4.6 Additional information Adequate power supply bypassing is necessary to protect associated circuitry. The minimum recommended is 0.1 µF in parallel with 1 µF electrolytic. http://www.hgsemi.com.cn 14 2018 JUN