XD74LS74

XD74LS74 DIP-14 Pin Arrangement 1CLR 1 1D 2 1CK 3 1PR 4 1Q 5 D 1Q 6 CLR Q GND 7 CK D PR CLR Q Q CK PR Q 14 VCC 13 2CLR 12 2D 11 2CK 10 2PR 9 2Q 8 2Q (Top view) Function Table Input Output Preset L Clear H Clock X D X Q H Q L H L L L X X X X L H* H H* H H H H ↑ ↑ H L H L L H H H L X Q0 Q0 H; high level, L; low level, X; irrelevant, ↑; transition from low to high level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. *;This configuration is nonstable, that is, it will not persist when preset and clear inputs return to their inactive (high) level. 1 XD74LS74 DIP-14 Absolute Maximum Ratings Item Supply voltage Symbol VCC Ratings 7 Unit V VIN PT 7 400 V mW Tstg –65 to +150 °C Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Symbol VCC Min 4.75 Typ 5.00 Max 5.25 Unit V IOH IOL — — — — –400 8 µA mA Topr fclock –20 0 25 — 75 25 °C MHz Pulse width Clock High Clear Preset tw tw 25 25 — — — — ns Setup time “H” Data “L” Data tsu tsu 20↑ 20↑ — — — — ns th 5↑ — — ns Hold time Note: ↑; The arrow indicates the rising edge. 2 XD74LS74 DIP-14 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH min. 2.0 typ.* — max. — Unit V VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA VOL — — — — 0.5 0.4 V IOL = 8 mA IOL = 4 mA — — — — 20 40 — — — — 40 20 µA VCC = 5.25 V, VI = 2.7 V — — — — –0.4 –0.8 — — — — –0.8 –0.4 mA VCC = 5.25 V, VI = 0.4 V — — — — 0.1 0.2 — — — — 0.2 0.1 mA VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC** — 4 8 mA VCC = 5.25 V Output voltage D Clear Preset Clock Input current D Clear Preset Clock D Clear Preset Clock Short-circuit output current Supply current IIH IIL II Condition VCC = 4.75 V, VIL = 0.8 V, VIH = 2 V Input clamp voltage VIR — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** With all output open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol fmax Inputs Outputs min. 25 typ. 33 max. Unit MHz tPLH tPHL Clear, Clock or Preset Q, Q — — 13 25 25 40 ns ns Condition CL = 15 pF, RL = 2 kΩ Timing Definition tw 3V 1.3 V 1.3 V 1.3 V Clock tsu th tsu 0V th 3V 1.3 V 1.3 V 1.3 V Data 0V "H" Data "L" Data 3 XD74LS74 DIP-14 Testing Method Test Circuit 1. ƒmax, tPLH, tPHL (Clock→Q, Q) 4.5V VCC Output Q Input RL PR P.G. Zout = 50Ω D Q Input CL Output Q P.G. Zout = 50Ω Notes: Load circuit 1 CK CLR Q Same as Load Circuit 1. 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 2. tPHL, tPLH (Clear or Preset→ Q, Q) VCC Input Output Q P.G. Zout = 50Ω RL Load circuit 1 PR D Q CL Output Q Input CK CLR Q P.G. Zout = 50Ω Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 4 Same as Load Circuit 1. XD74LS74 DIP-14 Waveforms 1 tTLH tTHL tw(L) 90% 90% 1.3 V 1.3 V Clock 3V 1.3 V 10% 10% 0V tw(H) 3V D 0V tPLH tPHL VOH 1.3 V Q 1.3 V tPHL VOL tPLH Q VOH 1.3 V 1.3 V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax, tTLH = tTHL ≤ 2.5 ns Waveforms 2 tTHL Clear tTLH 90% 1.3V 10% 3V 90% 1.3V 10% tw (clear) 0V tTHL ≥ 25ns tTLH 90% 1.3V 10% Preset 90% 1.3V 10% tw (preset) ≥ 25ns tPLH tPHL 1.3V Q 3V 0V VOH 1.3V tPLH VOL VOH Q Note: 1.3V 1.3V tPHL Crear and presel input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, 5 VOL XD74LS74 DIP-14 DIP14 65