5003DAA70M65600BBI

AS5003 Arcadium™ I2C Programmable Oscillator, 10 kHz to 350 MHz The AS5003 Arcadium™ all-silicon oscillator utilizes proprietary frequency synthesis and sensor technologies to provide a quartz-free, MEMS-free, low jitter clock at any output frequency. The device is fully programmable to any frequency from 10 kHz to 350 MHz with < 0.026 ppb resolution and maintains low jitter across its operating range. The AS5003 uses on-chip temperature and strain sensors, and an advanced LC tank architecture to achieve excellent reliabilities even in high impact shock scenarios. AS5003’s on-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low jitter clocks in noisy systems that use switched-mode power supplies. Offered in a variety of industrystandard packages, the AS5003 has a dramatically simplified supply chain that enables Aeonsemi to ship samples shortly after receipt of order. The AS5003 is user-configurable with an I2C interface for a wide variety of user specifications, including frequency, output format, and DCO mode. Default configuration is factory programmed at time of shipment. It also guarantees 100% electrical testing of every device before shipment. KEY FEATURES • Quartz-free and MEMS-free without mechanical moving parts • I2C programmable to any frequency • Differential: 10 kHz to 350 MHz • LVCMOS: 10 kHz to 212.5 MHz • Up to 0.026 ppb frequency tuning resolution • I2C interface supports 100 kbps, 400 kbps and 1 Mbps (Fast Mode Plus) • Low jitter: 350 fs Typ RMS (12 kHz – 20 MHz) • Compliant to PCIe Gen 1/2/3/4/5 jitter requirements • 50 ppm stability (-40 to 105ºC) • Integrated LDO for on-chip power supply All Silicon Oscillator Flexible Output Frequency noise filtering Flexible Output Format • Support continuous 1.8V to 3.3V VDD supply operation • LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output options • Industrial standard 3.2 x 5, 2.5 x 3.2 mm Freq / Temp Comp package footprints APPLICATIONS Control • 1G/10G/40G/100G Ethernet • Servers, switches, storage, NICs, search acceleration • Test and measurement I2C • Clock and data recovery • FPGA/ASIC clocking Pin Assignments Pin # Descriptions 2 1 SDA = I C Serial Data 2 SCL = I2C Serial Clock 3 GND = Ground 4 CLK+ = Clock output 5 CLK- = Complementary clock output 6 VDD = Power supply 3.2 x 5 mm and 2.5 x 3.2 mm aeonsemi.com | Enabling Edge Computing Network This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Rev. 0.9 AS5003 Datasheet 1. Ordering Guide The AS5003 Oscillator supports a variety of initial options including frequency, output format, as shown in the chart below. Configurations are changeable by users via I2C interface upon startup. Samples are available in 2 weeks. XO Series Description 5003 I2C Programmable 5003 Total Stability A A A 1 Package + 50 ppm A - - - - - A 3.2 x 5 mm I -40 to 85 °C B 2.5 x 3.2 mm E -40 to 105 °C - Signal Format VDD Range Coupling Order Option LVPECL 2.5, 3.3 V DC A LVPECL 2.5, 3.3 V AC B LVDS 1.8 V DC C LVDS 2.5, 3.3 V DC D CML 1.8, 2.5, 3.3 V AC E 1.8, 2.5, 3.3 V DC F Frequency Code 1.8, 2.5, 3.3 V DC G Mxxxxxxx 1.8, 2.5, 3.3 V DC H 1.8, 2.5, 3.3 V DC I 1.8, 2.5, 3.3 V DC J HCSL 50 Termination) HCSL 5 Termination) CMOS Dual CMOS (In-Phase) Dual CMOS (Complementary) Temperature Grade - - A Output B I 2 R Device Revision A Low Power State B Default Freq, Output Disabled Tape and Reel Package Qty C Default Freq, Output Enabled T 250 R 2500 Bulk 3 Description FCLK < 1 MHz xMxxxxxx 1 MHz xxMxxxxx 10 MHz xxxMxxxx 100 MHz FCLK < 10 MHz FCLK < 100 MHz FCLK MHz An unique startup frequencies can be specified within the supported range of the selected signal format. Notes: 1. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 10 years aging at 40 °C. 2. Device supports extended industrial temperature range of -40 to 105°C only with VDD = 1.8V (+/- 5%). 3. For example: 156.25 MHz = 156M2500; 25 MHz = 25M00000. aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 2 AS5003 Datasheet 2. Electrical Specifications Table 2.1 Electrical Specifications VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC; VDD = 1.8 V ± 5%, TA = –40 to 105 ºC Parameter Symbol Temperature Range TA Frequency Range FCLK Supply Voltage VDD Supply Current (FCLK = 50 MHz) IDD Test Condition/Comment Min Typ Max Unit –40 — 105 ºC LVPECL, LVDS, CML, HCSL 0.01 — 350 MHz CMOS, Dual CMOS 0.01 — 212.5 MHz 3.47 V 1.71 — 40 50 mA Ready State — 1 2 mA LVPECL (DC-Coupled) — 70 80 mA LVPECL (AC-Coupled) — 60 70 mA LVDS — 45 55 mA HCSL — 60 70 mA CML — 60 70 mA CMOS — 40 55 mA — 50 60 mA –50 — 50 ppm Tristate Hi-Z (output disabled) Dual CMOS Total Stability1 FSTAB Frequency stability Rise/Fall Time (20% to 80% VPP) TR/TF LVPECL/LVDS/CML — — 350 ps CMOS / Dual CMOS (CL = 5 pF) — 0.5 1.5 ns HCSL, FCLK >50 MHz — — 550 ps All formats 45 — 55 % Duty Cycle DC Output Enable (OE)2 VIH 0.7 × VDD — — V VIL — — 0.3 × VDD V TD Output Disable Time, FCLK >10 MHz — — 0.5 µs TE Output Enable Time, FCLK >10 MHz — — 0.5 µs — — 4 ms tOSC Powerup Time Time from 0.9 × VDD until output frequency (FCLK) within spec VOC Mid-level VDD – 1.55 — VDD – 1.25 V (DC-Coupled) VO Swing (diff) 1.4 — 1.85 VPP LVPECL Output Option3 VO Swing (diff) 1.4 1.85 VPP VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V Mid-level (1.8 V VDD) 0.795 0.85 0.905 V Swing (diff) 0.5 0.82 0.96 VPP LVPECL Output Option3 (AC-Coupled) LVDS Output Option4 (DC-Coupled) VO aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 3 AS5003 Datasheet Parameter Symbol Test Condition/Comment Min Typ Max Unit VOH Output voltage high 695 815 935 mV VOL Output voltage low 0 5 10 mV VOH Output voltage high 695 820 945 mV VOL Output voltage low 0 5 10 mV CML Output Option4 (AC-Coupled) VO Swing (diff) 0.725 0.8 0.89 VPP CMOS Output Option VOH IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.83 × VDD — — V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD — 0.17 × VDD V HCSL Output Option4 (Rterm = 50 Ω; DC-Coupled) HCSL Output Option5 (Rterm = 5 Ω; DC-Coupled) — Notes: 1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 10 years at 40 ºC. 2. The TD and TE < 10 ns + 3 * 1/FCLK for all frequencies measured from the end of the I 2C byte write to OE control registers. 3. Rterm = 50 Ω to VDD – 2.0 V (see Figure 4.1). 4. Rterm = 100 Ω differential) see Figure 4.2). 5. Rterm = 5 Ω or 50 Ω to GND see Figure 4.3). Table 2.2: I2C Characteristics VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC; VDD = 1.8 V ± 5%, TA = –40 to 105 ºC Parameter Frequency Reprogramming Resolution Frequency Range for Small Frequency Change (Continuous Glitchless Output) Settling Time for Small Frequency Change (DCXO Feature) Settling Time for Frequency Change (fUSER_FREQ Register) aeonsemi.com | Enabling Edge Computing Network Symbol Test Condition/Comment VRES From center frequency < ± 970 ppm from center frequency Min Typ Max Unit — 0.026 — ppb +970 ppm 8 us 200 us -970 Rev. 0.9 | 4 AS5003 Datasheet Table 2.3: Clock Output Phase Jitter and PSRR VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC; VDD = 1.8 V ± 5%, TA = –40 to 105 ºC Parameter Symbol Test Condition/Comment Min Typ Max Unit Phase Jitter (RMS, 12 kHz - 20 MHz)1,2 FCLK ≥ 10 MHz ϕJ Differential Formats — 350 750 fs CMOS, Dual CMOS — 350 — fs Phase Jitter (RMS, 50 kHz - 20 MHz) ϕJ Differential Formats — 150 250 fs CMOS, Dual CMOS — 100 — fs 100 kHz sine wave — -76 — 200 kHz sine wave — -75 — 500 kHz sine wave — -75 — 1 MHz sine wave — -75 — 100 kHz sine wave — -83 — 200 kHz sine wave — -83 — 500 kHz sine wave — -83 — 1 MHz sine wave — -82 — FCLK ≥ 156.25 MHz Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. PSRR LVDS 156.25 MHz Output VDD = 1.8 V Spurs Induced by External Power Supply Noise, 50 mVpp Ripple. PSRR LVDS 156.25 MHz Output VDD = 2.5 or 3.3 V dBc dBc Note: 1. Applies to output frequency: 50, 100, 156.25, 212.5, 350 MHz 2. Guaranteed by characterization. Jitter inclusive of any spurs Figure 2.1: Phase Noise at 156.25 MHz aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 5 AS5003 Datasheet Table 2.4: Environmental Compliance and Package Information Parameter Test Condition Moisture Sensitivity Level 1 Note: For additional product information not listed in the data sheet (e.g. RoHS Certifications, MSDS data, qualification data, REACH Declarations, ECCN codes, etc.), contact aeonsemi.com/contact-us/ Table 2.5: Thermal Conditions Package Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient ΘJA Still Air 105 ºC/W Thermal Resistance Junction to Board ΘJB Still Air 81 ºC/W Max Junction Temperature TJ Still Air 125 ºC Thermal Resistance Junction to Ambient ΘJA Still Air 108 ºC/W Thermal Resistance Junction to Board ΘJB Still Air 84 ºC/W Max Junction Temperature TJ Still Air 125 ºC 3.2 x 5 mm, 6-pin DFN 2.5 x 3.2 mm, 6-pin DFN Table 2.6: Absolute Maximum Ratings1 Parameter Symbol Rating Unit TAMAX 105 ºC TS -55 to 125 ºC Supply Voltage VDD -0.5 to 3.8 V Input Voltage VIN -0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 4.0 kV Solder Temperature3 TPEAK 260 ºC Solder Time at TPEAK3 TP 20 - 40 sec Maximum Operating Temperature2 Storage Temperature Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. For VDD = 1.8V only; otherwise 85ºC. 3. The device is compliant with JEDEC J-STD-020. aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 6 AS5003 Datasheet 3. CMOS Buffer and Output Terminations Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple XOs with a single AS5003 device. Figure 3.1: Integrated 1:2 CMOS Buffer Supports In-Phase or Complementary Outputs AS50xx AS50xx VDD VDD CLK+ CLK CLK- CMOS Receiver NC CMOS Receiver Single CMOS Termination Dual CMOS Termination Figure 3.2: CMOS Output Terminations aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 7 AS5003 Datasheet 4. Recommended Output Terminations The output drivers support AC-coupled or DC-coupled terminations as shown in figures below. AS50xx AS50xx VDD (3.3V, 2.5V) VDD (3.3V, 2.5V) R1 CLK+ 0.1 µF CLK- 0.1 µF R1 R1 R1 R2 R2 CLK+ CLK- R2 R2 LVPECL Receiver AC-Coupled LVPECL – Thevenin Termination LVPECL Receiver DC-Coupled LVPECL – 50 Ω w/ VTT Bias AS50xx AS50xx VDD (3.3V, 2.5V) VDD (3.3V, 2.5V) CLK+ VDD CLK- VDD (3.3V, 2.5V) VDD (3.3V, 2.5V) R1 CLK+ 0.1 µF VDD R2 CLK- 0.1 µF R1 R2 LVPECL Receiver LVPECL Receiver DC-Coupled LVPECL – Thevenin Termination AC-Coupled LVPECL – 50 Ω w/ VTT Bias Termination Resistor Values VDD 3.3 V 1 7 R1 8 5 R2 2.5 V 50 6 5 Figure 4.1: LVPECL Output Terminations aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 8 AS5003 Datasheet DC-Coupled LVDS AC-Coupled CML Figure 4.2: LVDS / CML Output Terminations AS50xx AS50xx VDD VDD CLK+ CLK+ CLK- CLKHCSL Receiver HCSL Receiver Source Terminated HCSL Destination Terminated HCSL Figure 4.3: HCSL Output Terminations aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 9 AS5003 Datasheet 5. Configuring via I2C Interface 5.1 I2C Serial Interface The I2C interface on the AS5003 is fully compatible with the “UM10 0 I2C-bus specification and user manual, Rev. 6 standard, as described in Table 5.1. Table 5.1: I2C compatibility I2C Speed Compliance Notes Standard 100 kHz Compliant N/A Fast 400 kHz Compatible SDA failing edge can be faster than 20 ns depending on loading Fast+ 1 MHz Compatible SDA falling edge can be faster than 20 ns depending on loading. April 01 ” SDA max pull down current is 6 mA. 5.2 I2C Register Write and Read Protocol AS5003 implements an 8-bit I2C address space with 256 addressable byte register locations. Certain device register and bits are reserved, and they must not be changed from their default reset state. In an I2C bus system, the AS5003 acts as a slave device connected to the I 2C serial interface bus. It is accessed via a 7-bit factory programmed (per user specification) slave address. Allowed values of this device address are in the range from 16 to 119. Both write and read register transactions with register address autoincrement are enabled as shown in Figure 5.1. I2C Register Wr S DevAddr 0 Register write data A Addr W A A: D0 A A D1 A DN-1 A+1 ... A+N-1 I2C Register Rd S DevAddr 0 A P/Sr Write to address Register read data A Addr W A Sr A: S .. START P .. STOP Sr .. RESTART DevAddr 1 R A D0 A A D1 A DN-1 A+1 ... A+N-1 A .. ACK N .. NACK R .. Read W .. Write N P/Sr Read from address Figure 5.1: I2C write and read transactions Write register transaction is an I2C write transaction with an 8-bit register address data byte stream. It is followed by one or more register data bytes. Read register sequence starts after a write transaction to set the read register address. It is followed by the I2C read transaction to read one or more data bytes. The register address autoincrement is enabled upon power up. It is incremented till a maximum address 0xFF of the I2C register space is reached. The register address autoincrement is disabled by writing register bI2C_INC_DIS=1 and re-enabled again by writing bI2C_INC_DIS=0. During this process, all bytes in the I2C transactions are written to or read from a set address. Having the register autoincrement disabled is required for a DCXO streaming mode. Data and address bytes appear on the SDA bus with the most significant bit (MSB) first per I2C standard. During I2C transactions, SCL clock bus is never stalled by the device. aeonsemi.com | Enabling Edge Computing Network Rev. 0.9 | 10 AS5003 Datasheet 5.3 Device Operation After an initial power up sequence, the device operates in either Ready state or an Active state depending on customization in factory. The Ready state is a power down standby state when majority of internal circuitries are powered down. The Active state is the device active mode with all internal circuitries powered up. Writing to register bUSYS_CTRL can move the device between Ready state and Active state. The following three power up options are available for factory configuration: 1. Ready state: The device is in the power down standby mode. Writing transaction to register bUSYS_CTRL is required to enable the device and enable the Active state. Active state with bODIV_CTRL=0: The device generates frequency internally, but output is disabled. Writing transaction to register bODIV_CTRL is required to enable output driver to propagate output frequency. Active state with bODIV_CTRL=1: The device is fully functional, and output is enabled. I2C intervention is not necessary. 2. 3. In the state 1 and 2 above, user can write to I2C to change drive mode or central frequency from the factory set values prior to enabling the device output or before moving to Active state. 5.4 Changing Frequency and Output Driver Mode After startup, the device is at the factory set frequency, output driver mode, and device state. The device is ready to be controlled by I2C register writes. All register writes can take immediate effect, except fUSER_FREQ and bDRV_MODE registers which require a follow on Apply command. User frequency register, “fUSER_FREQ”, is a -byte big endian register representing frequency as a binary32 IEEE 754- 008 standard number, in [Hz] units User driver mode register, “bDRV_MODE” is a single byte number representing driver mode described in Table 5.19. Changing frequency and driver mode requires two steps: 1. Writing fUSER_FREQ and/or bDRV_MODE registers with the new desired central frequency and/or driver mode. Only the changing register needs to be written. Writing order in bytes is not essential. Writing these registers only records the new values, but does not invoke any internal processing. Writing bUSYS_CTRL register with one of four Apply* commands. Once the Apply* command is accepted, the device uses the fUSER_FREQ and bDRV_MODE register values and invokes internal central frequency and/or driver mode. 2. Changing frequency can be completed by either disabling the output driver or keeping the output drive enabled. This is determined by applying different Apply* commands. The bUSYS_CTRL values and descriptions are shown in Table 5.2. Table 5.2: System control register bUSYS_CTRL Value Mnemonic Description 0 UsysNop No operation -- 1 UsysReady Ready standby power down state -- 2 UsysActive Active state -- 3 No operation -- 4 UsysRstSys Invoke system reset restart -- 5 UsysRstPor Invoke power-on reset restart -- 6 Do not use -- 7 Do not use -- UsysApply Apply: Disable output if active, update only changed frequency/driver mode Check/Set UsysApplyForce Apply force: Disable output if active, force frequency/driver mode update Check/Set UsysApplyAct Apply active: Keep output running if active, update only changed frequency/driver mode Check/Set UsysApplyActForce Apply active force: Keep output running if active, force frequency/driver mode update Check/Set UsysRefresh Refresh: Refresh fUSER_FREQ and bDRV_MODE register values to reflect the actual current device frequency and driver mode settings Check/Set 8 9 10 11 12 Others Do not use aeonsemi.com | Enabling Edge Computing Network stat_busy -- Rev. 0.9 | 11 AS5003 Datasheet Writing to “bUSYS_CTRL” register generates an acceptance request When this command is accepted, the “bUSYS_CTRL” register is cleared. If a read from “bUSYS_CTRL” returns a non-zero value, it means that the writing command is still waiting to be accepted. A command acceptance happens in less than 5 us from the finishing of writing to the “bUSYS_CTRL” register An accepted command can be either processed or ignored. Commands other than “Apply*” and “Refresh” are always processed after the acceptance It is possible to interrupt any “Apply*” or “Refresh” command under processing A processing time depends on the command and its current state of the device, in most cases it is 1 ~ 5 us, but can be up to 160 us when the command is generated in the middle of the frequency change. “Apply*” and “Refresh” commands are only processed when “bUSYS_STATS stat_busy” = 0 When “bUSYS_STATS stat_busy” = 1, although new “Apply*” and “Refresh” commands are accepted, they are ignored The “bUSYS_STATS stat_busy” = 1 status bit is the beginning of internal processing The “bUSYS_STATS stat_busy” = 0 occurs after this internal processing finishes. Changing frequency and output driver must be completed before invoking a new command. Issuing a “Refresh” command reset the values of registers to match the actual state of the device During a normal operation, the device keeps the values of fUSER_FREQ and bDRV_MODE synchronized with the internal state of the device. Reading these registers represent the actual frequency and output driver mode. However, the values could be different if writing occurs before applying the “Apply*” or “Refresh” command If the “Apply*” command is not applied, then the registers value are the previous written values. Thus, issuing the “Refresh” command is necessary. “fUSER_FREQ” and “bUSYS_STAT” registers are located back to back in I 2C address space. As a result, the most used operation is done in a single I2C transaction as shown in Figure 5.2. This example shows changing the frequency to a 70 MHz, which corresponds a 32-bit floating point number, 0x c8583b0 in [Hz] It is followed by a “Apply” command to invoke the internal frequency update, and assumed that the I2C register address autoincrement is enabled, which is a default. 70.0 MHz frequency change S DevAddr 0 A 0x55 A 0x4c 70.0 MHz Apply fUSER_FREQ bUSYS_CTRL 0x85 A A 0x83 A 0xb0 A 0x08 A P/Sr W Figure 5.2: Frequency change I2C transaction 5.5 System Status “bUSYS_STAT” is a read only system status register It is readable any time and it reflects the current device status. All possible values of the register are listed in Table 5.3. Table 5.3: System status bUSYS_STAT register values stat_busy -- -- stat_trans stat_rst stat_tune stat_actifve stat_ready bUSYS_STAT [7] [6] [5] [4] [3] [2] [1] [0] 0 0 0 0 0 0 0 0 Start up v 0 0 0 0 0 0 1 Ready state v 0 0 0 0 0 1 0 Active state v 0 0 0 0 1 1 0 Active state, tuning to new frequency v 0 0 1 0 0 0 1 Ready  Active transition v 0 0 1 0 0 1 0 Active  Ready transition 0 0 0 1 1 0 0 0 Reset processing, shutting down 0 0 0 0 1 0 0 0 Reset accepted aeonsemi.com | Enabling Edge Computing Network Description Rev. 0.9 | 12 AS5003 Datasheet stat_busy bit [7] value v denotes value 0 or 1. The bit is 1 at the beginning of Apply* and Refresh commands internal processing and is 0 when the processing is done. 5.6 Output Drive Control The output driver is powered up only in an Active state. CLKP and CLKM output signals are enabled or disabled by OE control register bits, “bUDRV_CTRL.udrv_oe_stop” and “bODIV_CTRL.odiv_oe_ena”. The simplified control flow of output driver is shown in Figure 5.3. Active bUSYS_CTRL on VDD CLKM Output Divider Driver CLKP udrv_oe_stop bDRV_CFG bUDRV_CTRL bDRV_MODE odiv_oe_ena bODIV_CTRL Figure 5.3: Driver control flow Putting system to Ready state or disabling the driver with “bDRV_MODE” = 0 to issue one of the “Apply*” commands power down the output driver. 5.7 Center Frequency Control Changing “fUSER_FREQ” register value controls the center frequency. The step does not apply to the DCXO feature. Frequency change request shown in Figure 5.4 and Figure 5.5 marks the time when a “Apply*” command is written to a “bUSYS_CTRL” register which corresponds with the write of the last data bit to this “bUSYS_CTRL” register. Figure 5.4 shows a timing of frequency change by using “Apply” command when a “fUSER_FREQ” register value is different from the current frequency; or using “ApplyForce” command with the output disabled during the frequency change. fCURR fNEW Frequency change request Steady OUT Off Tune to fUSER_FREQ OUT On tDRVOFF tTUNE tDRVON 5 .. 25 μs