ZD25Q16B
ZD25Q16B
Ultra Low Power, 16M-bit
Serial Multi I/O Flash Memory Datasheet
Performance Highlight
Wide Supply Range from 2.7 to 3.6V for Read, Erase and Program
Ultra Low Power consumption for Read, Erase and Program
X1, X2 and X4 Multi I/O Support
High reliability with 100K cycling and 20 Year-retention
1
ZD25Q16B
Contents
1. FEATURES.............................................................................................................................................4
2. GENERAL DESCRIPTION........................................................................................................................5
3. MEMORY ORGANIZATION................................................................................................................... 7
4. DEVICE OPERATION............................................................................................................................. 8
5. DATA PROTECTION.............................................................................................................................. 9
6. STATUS REGISTER.............................................................................................................................. 11
7. COMMANDS DESCRIPTION................................................................................................................ 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.23.
7.24.
7.25.
7.26.
7.27.
7.28.
7.29.
7.30.
7.31.
Write Enable (WREN) (06H).......................................................................................................................16
Write Disable (WRDI) (04H)....................................................................................................................... 16
Read Status Register (RDSR) (05H or 35H)................................................................................................ 17
Write Status Register (WRSR) (01H).......................................................................................................... 17
Write Enable for Volatile Status Register (50H)........................................................................................ 18
Read Data Bytes (READ) (03H)...................................................................................................................18
Read Data Bytes at Higher Speed (Fast Read) (0BH).................................................................................19
Dual Output Fast Read (3BH).....................................................................................................................19
Quad Output Fast Read (6BH)................................................................................................................... 20
Dual I/O Fast Read (BBH)........................................................................................................................... 20
Quad I/O Fast Read(EBH).......................................................................................................................... 22
Quad I/O Word Fast Read(E7H)................................................................................................................ 23
Page Program (PP) (02H)........................................................................................................................... 24
Quad Page Program (32H)......................................................................................................................... 25
Sector Erase (SE) (20H).............................................................................................................................. 26
32KB Block Erase (BE) (52H)...................................................................................................................... 26
64KB Block Erase (BE) (D8H)......................................................................................................................27
Chip Erase (CE) (60/C7H)........................................................................................................................... 27
Deep Power-Down (DP) (B9H)...................................................................................................................28
Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH).............29
Read Manufacture ID/ Device ID (REMS) (90H)........................................................................................ 30
Read Identification (RDID) (9FH)............................................................................................................... 31
Continuous Read Mode Reset (CRMR) (FFH)............................................................................................ 32
Read Unique ID (4BH)................................................................................................................................ 33
Program/Erase Suspend (PES) (75H)......................................................................................................... 33
Program/Erase Resume (PER) (7AH)......................................................................................................... 34
Erase Security Registers (44H)...................................................................................................................34
Program Security Registers (42H)..............................................................................................................35
Read Security Registers (48H)....................................................................................................................36
Enable Reset (66H) and Reset (99H)..........................................................................................................37
Read Serial Flash Discoverable Parameter (5AH)......................................................................................37
8. ELECTRICAL CHARACTERISTICS.......................................................................................................... 42
8.1.
8.2.
POWER-ON TIMING................................................................................................................................... 42
INITIAL DELIVERY STATE.............................................................................................................................42
2
ZD25Q16B
8.3.
8.4.
8.5.
8.6.
9.
ABSOLUTE MAXIMUM RATINGS................................................................................................................42
CAPACITANCE MEASUREMENT CONDITIONS........................................................................................... 43
DC CHARACTERISTICS.................................................................................................................................44
AC CHARACTERISTICS.................................................................................................................................46
ORDERING INFORMATION.................................................................................................................51
10. PACKAGE INFORMATION................................................................................................................... 52
10.1.
10.2.
10.3.
10.4.
8-Lead SOP(150mil)................................................................................................................................... 52
8-Lead SOP(208mil)................................................................................................................................... 53
8-Lead TSSOP(173mil)................................................................................................................................54
8-Land WSON(6x5mm).............................................................................................................................. 55
11. REVISION HISTORY.............................................................................................................................56
3
ZD25Q16B
1. FEATURES
◆
16M-bit Serial Flash
◆
Fast Program/Erase Speed
-2048K-Byte
-Page Program time: 1.1ms typical
-256 Bytes per programmable page
-Sector Erase time: 5.1ms typical
-Block Erase time: 5.1ms typical
◆
Standard, Dual, Quad SPI
-Chip Erase time: 5.2ms typical
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
◆
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
Flexible Architecture
-Uniform Sector of 4K-Byte
-Uniform Block of 32/64K-Byte
◆
High Speed Clock Frequency
-120MHz for fast read with 30PF load
◆
◆
◆
Low Power Consumption
-Dual I/O Data transfer up to 240Mbits/s
-0.65uA typical deep power down current
-Quad I/O Data transfer up to 480Mbits/s
-8uA typical standby current
Software/Hardware Write Protection
◆
Advanced Security Features
-Write protect all/portion of memory via software
-128-Bit Unique ID for each device
-Enable/Disable protection with WP# Pin
-4x256-Byte security registers with OTP locks
-Top/Bottom Block protection
-Discoverable parameters (SFDP) register
Minimum 100,000 Program/Erase Cycles
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
◆
Data Retention
-20-year data retention typical
◆
Package Information
-SOP8 (150mil)
◆
Allows XIP (execute in place) Operation
-SOP8 (208mil)
-TSSOP8 (173mil)
-WSON8 (6*5mm)
-Continuous Read With 8/16/32/64-Byte Wrap
-TFBGA-24(6*4 ball array)
4
ZD25Q16B
2. GENERAL DESCRIPTION
The ZD25Q16B(16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI:
Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed
of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
CONNECTION DIAGRAM
1
CS#
8
2
SO
WP#
GND
Vcc
7
HOLD
3
6
SCLK
4
5
Top View
SI
8-PIN SOP (150mil/200mil) and TSSOP
Top View
4
3
2
Nc
Vcc
Nc
Vss
Nc
1
WP# HOLD
Nc
Nc
Nc
SI
Nc
Nc
SCLK CS#
SO
Nc
Nc
Nc
Nc
Nc
Nc
Nc
Nc
A
B
C
D
E
F
24-BALL TFBGA
PIN DESCRIPTION
Pin Name
I/O
Description
CS#
I
Chip Select Input
SO (IO1)
I/O
Data Output (Data Input Output 1)
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
Ground
GND
SI (IO0)
I/O
Data Input (Data Input Output 0)
SCLK
I
Serial Clock Input
HOLD# (IO3)
I/O
Hold Input (Data Input Output 3)
VCC
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
ZD25Q16B
BLOCK DIAGRAM
Din
Hv PageLatch
High Voltage
Generator
HOLD#(IO3)
SCLK
WP#(IO2)
SO(IO1)
CS
SPI
Command
&
Control Logic
Row Decoder
SI(IO0)
High Voltage
Control
Flash - cell
Array
Address
Latch
Coumun Mux
Dout
6
Sense Amplifier
ZD25Q16B
3. MEMORY ORGANIZATION
ZD25Q16B
Each device has
Each block has
Each sector has
Each page has
2M
64/32K
4K
256
Bytes
8K
256/128
16
-
pages
512
16/8
-
-
sectors
32/64
-
-
-
blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
ZD25Q16B 64K Bytes Block Sector Architecture
Block
31
30
……
……
2
1
0
Sector
Address range
511
1FF000H
1FFFFFH
……
……
……
496
1F0000H
1F0FFFH
495
1EF000H
1EFFFFH
……
……
……
480
1E0000H
1E0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
7
ZD25Q16B
4. DEVICE OPERATION
SPI Mode
Standard SPI
The ZD25Q16B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The ZD25Q16B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the standard
SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The ZD25Q16B supports Quad SPI operation when using the “Quad Output Fast Read” (6BH), ”Quad I/O Fast
Read”(EBH), “Quad I/O Word Fast Read” (E7H) and “Quad Page Program” (32H) commands. These commands allow data
to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI
and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI
commands require the non-volatile Quad Enable bit (QE) in Status Register to beset.
Hold
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated
data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure 1. Hold Condition
CS #
SCLK
HOLD
HOLD
HOLD
8
ZD25Q16B
5. DATA PROTECTION
The ZD25Q16B provide the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
◆
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory
◆
array that can be read but not change.
◆
Hardware Protection Mode: WP# goes low to protect the BP0~BP4 bits and SRP0~1 bits.
◆
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1.0 ZD25Q16B Protected area size (CMP=0)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
31
1F0000H-1FFFFFH
64KB
Upper 1/32
0
0
0
1
0
30 to 31
1E0000H-1FFFFFH
128KB
Upper 1/16
0
0
0
1
1
28 to 31
1C0000H-1FFFFFH
256KB
Upper 1/8
0
0
1
0
0
24 to 31
180000H-1FFFFFH
512KB
Upper 1/4
0
0
1
0
1
16 to 31
100000H-1FFFFFH
1M
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/32
0
1
0
1
0
0 to 1
000000H-01FFFFH
128KB
Lower 1/16
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/8
0
1
1
0
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/4
0
1
1
0
1
0 to 15
000000H-0FFFFFH
1M
Lower 1/2
X
X
1
1
X
0 to 31
000000H-1FFFFFH
2M
ALL
1
0
0
0
1
31
1FF000H-1FFFFFH
4KB
Top Block
1
0
0
1
0
31
1FE000H-1FFFFFH
8KB
Top Block
1
0
0
1
1
31
1FC000H-1FFFFFH
16KB
Top Block
1
0
1
0
X
31
1F8000H-1FFFFFH
32KB
Top Block
1
1
0
0
1
0
000000H-000FFFH
4KB
Bottom Block
1
1
0
1
0
0
000000H-001FFFH
8KB
Bottom Block
1
1
0
1
1
0
000000H-003FFFH
16KB
Bottom Block
1
1
1
0
X
0
000000H-007FFFH
32KB
Bottom Block
9
ZD25Q16B
Table1.1 ZD25Q16B Protected area size (CMP=1)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
0 to 31
000000H-1FFFFFH
2M
ALL
0
0
0
0
1
0 to 30
000000H-1EFFFFH
1984KB
Lower 31/32
0
0
0
1
0
0 to 29
000000H-1DFFFFH
1920KB
Lower 15/16
0
0
0
1
1
0 to 27
000000H-1BFFFFH
1792KB
Lower 7/8
0
0
1
0
0
0 to 23
000000H-17FFFFH
1536KB
Lower 3/4
0
0
1
0
1
0 to 15
000000H-0FFFFFH
1M
Lower 1/2
0
1
0
0
1
1 to 31
010000H-1FFFFFH
1984KB
Upper 31/32
0
1
0
1
0
2 to 31
020000H-1FFFFFH
1920KB
Upper 15/16
0
1
0
1
1
4 to 31
040000H-1FFFFFH
1792KB
Upper 7/8
0
1
1
0
0
8 to 31
080000H-1FFFFFH
1536KB
Upper 3/4
0
1
1
0
1
16 to 31
100000H-1FFFFFH
1M
Upper 1/2
X
X
1
1
X
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 31
000000H-1FEFFFH
2044KB
Lower 511/512
1
0
0
1
0
0 to 31
000000H-1FDFFFH
2040KB
Lower 255/256
1
0
0
1
1
0 to 31
000000H-1FBFFFH
2032KB
Lower 127/128
1
0
1
0
X
0 to 31
000000H-1F7FFFH
2016KB
Lower 63/64
1
1
0
0
1
0 to 31
001000H-1FFFFFH
2044KB
Upper 511/512
1
1
0
1
0
0 to 31
002000H-1FFFFFH
2040KB
Upper 255/256
1
1
0
1
1
0 to 31
004000H-1FFFFFH
2032KB
Upper 127/128
1
1
1
0
X
0 to 31
008000H-1FFFFFH
2016KB
Upper 63/64
10
ZD25Q16B
6. STATUS REGISTER
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
Reserved
Reserved
Reserved
LB
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
BP1
BP0
WEL
WIP
SRP0
BP4
BP3
BP2
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1
SRP0
#WP
Status Register
0
0
X
Software Protected
0
1
0
Hardware Protected
0
1
1
Hardware Unprotected
1
0
X
1
1
X
Power Supply
Lock-Down(1)
(2)
One Time Program(2)
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
WP#=0, the Status Register locked and cannot be written to.
WP#=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be written
to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0)state.
2. This feature is available on special order. Please contact Zetta Device for details.
11
ZD25Q16B
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (It is best to set the QE bit to 0 to avoid short issues if the WP# or HOLD# pin is tied directly to the power
supply or ground).
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control
and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers
will become read-onlypermanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0
bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.
The default setting is CMP=0.
SUS bit
The SUS bit is a read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend
(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, powerup cycle.
12
ZD25Q16B
7.
COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-Byte command code must be shifted in to the device, with
most significant bit first on SI, and each bit is latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-Byte command code. Depending on the command, this might
be followed by address Bytes, or by data Bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been completed. For the commands of Read, Fast Read, Read Status Register or Release from Deep PowerDown, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can
be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to
deselected status.
For the commands of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a Byte boundary, otherwise the command
is rejected, and is not executed. That means CS# must be driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if CS# is driven high at any time the input Byte is not a full Byte,
nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Byte 2
Byte 3
Byte 4
Byte 5
Command Name
Write Enable
Write Disable
Byte 1
06H
04H
Volatile SR
Write Enable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
50H
05H
35H
01H
03H
0BH
(S7-S0)
(S15-S8)
S7-S0
A23-A16
A23-A16
S15-S8
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(Next Byte)
(D7-D0)
(continuous)
(continuous)
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)
Continuous Read Mode
Reset
Page Program
Quad Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
3BH
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(1)
(continuous)
BBH
A23-A8(2)
(D7-D0)(1)
6BH
A23-A16
A7-A0
M7-M0(2)
A15-A8
EBH
A23-A0
M7-M0(4)
A23-A0
M7-M0(4)
dummy(5)
(D7-D0)(3)
(continuous)
dummy(6)
(D7-D0)(3)
(continuous)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
Chip Erase
C7/60
H
66H
99H
Enable Reset
Reset
Program/Erase
Suspend
E7H
Byte 6
(continuous)
(continuous)
A7-A0
(continuous)
dummy
(D7-D0)(3)
FFH
02 H
32H
20H
52H
D8H
n-Bytes
75H
13
D7-D0
D7-D0
Next Byte
(continuous)
ZD25Q16B
Program/Erase Resume
7AH
Deep Power-Down
B9H
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
Manufacturer/
Device ID
dummy
dummy
dummy
(DID7DID0)
(continuous)
90H
dummy
dummy
00H
(MID7MID0)
Read Unique ID
4BH
dummy
dummy
dummy
dummy
Read Serial Flash
Discoverable
Parameter
5AH
A23-A16
A15-A8
A7-A0
dummy
Read Identification
9FH
(MID7M0)
(JDID15JDID8)
(JDID7JDID0)
Erase Security
Registers(8)
Program Security
Registers(8)
44H
A23-A16
A15-A8
A7-A0
42H
A23-A16
A15-A8
A7-A0
D7-D0
D7-D0
Read Security
Registers(8)
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
ABH
IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A7, A5, A3, A1, M7, M5, M3, M1
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
14
(continuous)
(D7-D0)
(continuous)
(continuous)
(continuous)
NOTE:
1. Dual Output data
3. Quad Output Data
(DID7DID0)
(UID7UID0)
ZD25Q16B
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register0: A23-A16=00H, A15-A8=00H, A7-A0= Byte Address;
Security Register1: A23-A16=00H, A15-A8=01H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=02H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=03H, A7-A0= Byte Address.
9. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x,
MID7, MID3, DID7, DID3, …)
Table of ID Definitions:
ZD25Q16B
Operation Code
MID7-MID0
ID15-ID8
ID7-ID0
9FH
BA
60
15
90H
BA
14
ABH
14
15
ZD25Q16B
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
Figure 2. Write Enable Sequence Diagram
CS #
0
1
2
3
4
5
6
7
SCLK
Command
SI
06H
SO
High-Z
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low
the Write Disable command
goes high. The WEL bit is reset by following condition: Power-
up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program
Security Registers and Reset commands.
Figure 3. Write Disable Sequence Diagram
CS #
0
1
2
3
4
SCLK
Command
SI
04H
SO
High-Z
16
5
6
7
ZD25Q16B
7.3. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The
command code “35H”, the SO will output Status Register bitsS15~S8.
Figure4. Read Status Register Sequence Diagram
CS #
0
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Command
05H or 35H
SI
7-S0 or S15-S8out
SO
7 6
5
4
3
S7-S0 or S15-S8 out
2
1
0
7
6
5
4
3
2
1
0
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch(WEL).
The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status Register. CS# must be
driven high after the eighth or sixteen bit of the data Byte has been latched in. If not, the Write Status Register (WRSR)
command is not executed. If CS# is driven high after eighth bit of the data Byte, the CMP and QE bit will not change. As
soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) isreset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status
Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with
the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to
be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware
Protected Mode is entered.
Figure5. Write Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
SI
SO
01H
Status Register in
7
6
MSB
5
4
3
High -Z
17
2
1
0
15 14
13 12 11 10
9
8
ZD25Q16B
7.5. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command and any other commands can't be inserted between them.
Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command
will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status
Register bit values.
Figure 6. Write Enable for Volatile Status Register Sequence Diagram
CS #
0
1
2
3
4
5
6
7
SCLK
Command(50H)
SI
SO
High-Z
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0), and each bit is latched-in on the
rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max
frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically
incremented to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
SCLK
0
1 2
3
4
5
6
7
8
9 10
24 -bit address
Command
SI
SO
03H
High - Z
28 29 30 31 32 33 34 35 36 37 38 39
23 22 21
3
2
1 0
Data Out1
MSB
MSB
18
7
6
5
4
3
2
Data Out2
1
0
ZD25Q16B
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3- Byte
address (A23-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte
of data is shifted out.
Figure 8. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
SCLK
1
2
5
4
3
6
7
8
9
10
Command
24- bit address
0BH
SI
28 29 30 31
23 22 21
3
0
2 1
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1 0
Data Out1
SO
7
6 5
MSB
4
3
Data Out2
2
1 0
7
6 5
MSB
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, each bit being latched
in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The
command sequence is shown in followed Figure 9 The first Byte addressed can be at any location. The address is
automatically incremented to the next higher address after each Byte of data is shifted out.
Figure 9. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
SI
24- bit address
3BH
23 22 21
3
2 1
0
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
MSB
19
MSB
ZD25Q16B
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure 10. The first Byte addressed can be at any location. The
address is automatically incremented to the next higher address after each Byte of data is shifted out.
Figure10. Quad Output Fast Read Sequence Diagram
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the
3-Byte address (A23-0) and a “Continuous Read Mode” Byte 2-bit per clock by SI and SO, and each bit is latched in on the
rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence
is shown in followed Figure 11. The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shiftedout.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next Dual
I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure 11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next
command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M7-0) before issuing normal command.
20
ZD25Q16B
4
7
21
5
ZD25Q16B
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-Byte address (A23-0) and a “Continuous Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO2, IO3, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first Byte addressed can be at any location. The
address is automatically incremented to the next higher address after each Byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast readcommand.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 13. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS #
0
1
2
3
4 5
6
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
8
SCLK
Command
4
0
4
0 4
0 4
0
4
0 4
0
SO( IO1)
5
1
5
1 5
1
5
1
5
1 5
1
WP#( IO2)
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3 7
EBH
SI (IO0)
HOLD
#( IO3)
A23-16 A15-8
M7-0
A7-0
Dummy
Figure14. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
0
SCLK
1
2
3
4
5
6 7
8
9 10 11 12 13 14 15
SI(IO0)
4
0
4
0
4
0
4
0
4
0 4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP # (IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
3 77
3
7
3
7
3
7
3
7
3
7
HOLD #(IO3)
7
A23- 16 A15-8
A7-0
M7-0
Dummy
22
Byte 1 Byte2
6 2
3
Byte 1 Byte2
ZD25Q16B
7.12. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address
bit (A0) must be equal 0 and there are only 2-dummy clock. The command sequence is shown in followed Figure15. The
first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each
Byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word
Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the
next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code.
The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode”
Reset command can be used to reset (M7-0) before issuing normalcommand.
Figure15. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS #
0
1
2
3
4 5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
4
0
4
0 4
0
4
0
4
0
4
0
SO( IO1)
5
1
5
1
5
1
5
1
5
1 5
1
WP#( IO2)
6
2
6
2
6
2
6
2
6
2 6
2
7
3
7
3
7
3
7
3
7
3
3
SCLK
Command
E7H
SI (IO0)
HOLD
#( IO3)
A23-16 A15-8 A7-0
M7-0 Dummy Byte 1 Byte2
Figure16. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)
CS#
0
SCLK
1
2
3
4
5
6 7
8
9 10 11 12
SI(IO0)
4
0 4
0
4
0 4
0
4
0 4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1 5
1
5
WP # (IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD #(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23- 16 A15-8
A7-0
M7-0Dummy Byte 1 Byte2
23
7
ZD25Q16B
7.13. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
Bytes and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low sending Page Program command 3-Byte address on SI at least
1 Byte data on SI CS# goes high. The command sequence is shown in Figure17. If more than 256 Bytes are sent to the
device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within
the same page. If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data
Byte has been latched in; otherwise the Page Program (PP) command is notexecuted.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit isreset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) is not executed.
Figure17. Page Program Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
2078
2079
2077
2076
2075
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
7
Byte1
6 5 4 3 2 1
2074
CS#
0
2073
02H
SI(IO0)
2072
24-bit address
23 22 21
3 2 1
Command
SCLK
Byte2
SI(IO0)
7
6
5
4
3 2 1
0
7 6 5
Byte3
4 3 2 1
24
Byte256
0
7
6 5 4
3 2 1
0
0
ZD25Q16B
7.14. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use
Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address Bytes
and at least one data Byte on IO pins.
The command sequence is shown in Figure18. If more than 256 Bytes are sent to the device, previously latched data
are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than
256 data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects
on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the
Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
Figure18.Quad Page Program Sequence Diagram
CS#
0
1 2
3
4
5
6
7
8
28 29 30 31 32 33 34 35 36 37 38 39
9 10
SCLK
24- bit address
Command
SI(IO0)
32H
23 22 21
3
Byte1 Byte2
2
1
0
0
4
0
4
0
4
0
55 1
5
1
5
1 5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
SO(IO1)
4
CS#
SCLK
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11 Byte12
Byte253
Byte256
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0 4
0
4
0
4
0
4
0
4
0
SO(IO1)
6
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5 1
5
1
5
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
7 3
7
3
7
3
7
3
7
3
7 3
WP#(IO2)
HOLD#(IO3)
25
ZD25Q16B
7.15. Sector Erase (SE) (20H)
The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address Byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-Byte address on SI
CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth bit of the last
address Byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
Figure19. Sector Erase Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9
Command
SI
29 30 31
24-bit address
20H
23 22
2
1
0
7.16. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside
the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-Byte address
on SI CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the
last address Byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is notexecuted.
Figure20. 32KB Block Erase Sequence Diagram
CS #
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
52H
24-bit address
23 22
MSB
26
2
1
0
ZD25Q16B
7.17. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside
the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the
sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-Byte address
on SI CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the
last address Byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure21. 64KB Block Erase Sequence Diagram
CS #
0
SCLK
1
2
3
4 5
6
7
8
9
Command
SI
29 30 31
24-bit address
D8H
23 22
2
1
0
MSB
7.18. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The
command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and
is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more sectors are
protected.
Figure22. Chip Erase Sequence Diagram
CS#
SCLK
0
1
2
3
4
Command
SI
60H or C7H
27
5
6
7
ZD25Q16B
7.19. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. These commands can release the device from this mode. The
Release from Deep Power-Down and Read Device ID (RDI) command releases the device from deep power down mode ,
also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after PowerUp.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes
high. The command sequence is shown in Figure23. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure23. Deep Power-Down Sequence Diagram
CS #
tDP
SCLK
Command
SI
Standby mode
B9H
28
Deep power-down mode
ZD25Q16B
7.20. Release from Deep Power-Down or High Performance Mode and Read Device
ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can
be used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the
CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure24. Release from Power-Down will
take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other c omma
nd are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy Byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. The Device ID value is listed in
Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by
driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure25, except that after CS# is driven high it must remain high for a time duration
of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command
will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle
is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure24. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
SCLK
0
1
2
4
5 6
7
29 30 31 32 33 34 35 36 37 38
8 9
tRES2
3 Dummy Bytes
Command
SI
SO
3
23 22
ABH
2
1
0
MSB
High-Z
7
MSB
6
Electronic SignatureOut
5 4 3 2 1 0
Deep Power- down mode
Figure 25. Release Power-Down/Read Device ID Sequence Diagram
CS#
SCLK
0
1
2
3
4
5 6
tRES1
7
Command
SI
ABH
Deep Power - down mode
29
Stand-by mode
Standby Mode
ZD25Q16B
7.21. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command
that provides both the JEDEC assigned Manufacturer ID and the specific DeviceID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure26. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2 3
4 5
6
7
8
28 29 30 31
9 10
SCLK
2dummy byte and
1 address byte
23 22 21
3 2
Command
SI
90H
SO
High-Z
CS#
SCLK
SI
SO
Device ID
ManufactureID
7 6
MSB
5 4
3
2
1 0
7
6
MSB
30
5
4
3
2
1
0
1
0
ZD25Q16B
7.22. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two Bytes
of device identification. The device identification indicates the memory type in the first Byte, and the memory capacity of the
device in the second Byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory, Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure27. The Read Identification (RDID) command is terminated by driving CS# high
at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and executecommands.
Figure27. Read Identification ID Sequence Diagram
CS#
SCLK
SI
0 1
2
3 4
5
6 7 8
9FH
SO
CS#
SCLK
9 10 11 12 13 14 15
7
MSB
6
ManufacturerID
5 4 3 2 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI
SO
MemoryType ID
7 6 5 4 3 2 1
MSB
0
7 6
MSB
31
CapacityID
5 4 3 2 1
0
0
ZD25Q16B
7.23. Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce
command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the
BBH/EBH/E7H command code.
Because the ZD25Q16B has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the
ZD25Q16B will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the
Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence
is show in Figure29.
Figure 28. Continuous Read Mode Reset Sequence Diagram
CS #
0
1
2
3
4
SCLK
Command
SI
FFH
SO
High-Z
32
5
6
7
ZD25Q16B
7.24. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each
ZD25Q16B device. The Unique ID can be used in conjunction with user software methods to help prevent
copying or cloning of a system. The Read Unique ID command sequence: CS# goes low sending Read Unique
ID command Dummy Byte1 Dummy Byte2 Dummy Byte3 Dummy Byte4128bit Unique ID Out CS#
goes high. The command sequence is show below.
Figure 29. Read Unique ID Sequence Diagram
CS#
0
1
2
3 4
5
6
7
8
9 10
28 29 30 31
SCLK
3 bytes dummy
Command
SI
SO
4BH
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43
164 165 166
SCLK
DummyByte
SI
128 bit unique serialnumber
SO
127 126 125 124
MSB
3
2
1
0
7.25. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H) and Erase/Program
Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command
(02H / 32H) are not allowed during Program suspend. The Write Status Register command (01H/31H/11H) and Erase
Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during Erase
suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of
time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status Register equal
to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS bit equal to
1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1 to 0 within
“tsus” and the SUS bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend
period will reset the device and release the suspend state. The command sequence is show in Figure31.
33
ZD25Q16B
Figure 30. Program/Erase Suspend Sequence Diagram
CS #
tSUS
SCLK
Command
SI
SO
75 H
High-Z
Accept read command
7.26. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after
a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS bit equal to 1 and the WIP bit equal to 0. After issued the SUS bit in the status register will be cleared from 1 to 0
immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or
the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active. The command sequence is show in Figure32.
Figure 31. Program/Erase Resume Sequence Diagram
CS #
SCLK
Command
SI
7AH
Resume Erase/Program
7.27. Erase Security Registers (44H)
The ZD25Q16B provides four 256-Byte Security Registers which can be read and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from the
main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command 3-Byte
address on SI CS# goes high. The command sequence is shown in Figure33. CS# must be driven high after the eighth bit of
the command code has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is
driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers
cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security RegistersLock Bit (LB) in the Status
Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently
locked; the Erase Security Registers command will be ignored.
34
ZD25Q16B
Address
Security Registers
A23-A16
00H
A15-A8
00H
A7-A0
Don’t Care
Figure32. Erase Security Registers command Sequence Diagram
CS#
0
SCLK
1
2
6
4 5
3
7
8
9
Command
24 bit address
44H
SI
29 30 31
23 22
1
2
0
7.28. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
one pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch
(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered
by driving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon
as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit isreset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security
Registers command will be ignored.
Address
A23-A16
A15-A8
A7-A0
Security Registers 0
00H
00H
Byte Address
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Byte Address
Figure33. Program Security Registers command Sequence Diagram
CS#
0
1
2
3 4
5
6
7
8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
2078
2079
2077
2076
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
7
2075
CS#
0
Byte1
6 5 4 3 2 1
2074
42H
SI(IO0)
2073
24-bit address
23 22 21
3 2 1
2072
Command
SCLK
Byte2
SI(IO0)
7
6
5
4
3 2 1
0
7
Byte3
6 5 4 3 2 1
35
Byte256
0
7
6 5 4
3 2 1
0
0
ZD25Q16B
7.29. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-Byte
address (A23-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte
of data is shifted out. Once the A7-A0 address reaches the last Byte of the register (Byte FFH), it will reset to 00H, the
command is completed by driving CS# high.
Address
A23-A16
A15-A8
A7-A0
Security Registers 0
00H
00H
Byte Address
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Byte Address
Figure34. Read Security Registers command Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
9 10
7 8
24- bitaddress
Command
SI
28 29 30 31
23 22 21
48H
3
2
1
0
High -Z
SO
CS#
SCLK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DummyByte
SI
SO
7
6
5
4
3 2
1
0
Data Out2
Data Out1
7
6
5
4
3
2
1
0
7
6
MSB
MSB
36
5
ZD25Q16B
7.30. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous Read Mode bit setting (M7M0) and Wrap Bit Setting (W6-W4).
The “Reset (99H)” command sequence as follow: CS# goes low Sending Enable Reset command CS# goes
high CS# goes low Sending Reset command CS# goes high. Once the Reset command is accepted by the device,
the device will take approximately tRST = 30us / 4ms to reset. During this period, no command will be accepted. Data
corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command
sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before
issuing the Reset command sequence.
Figure35. Enable Reset and Reset command Sequence Diagram
CS#
0
1 2 3
4 5
0
6 7
1 2 3
4 5
6 7
SCLK
Command
SI
Command
66H
99H
High-Z
SO
7.31. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can
be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure36. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1 2
3
4
5 6
7
8
9 10
28 29 30 31
SCLK
Command
SI
5AH
SO
High-Z
CS#
24-bit address
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
SI
SO
7
6
5
4
3
2
1
0
Data Out2
Data Out1
7 6
5
37
4 3
2
1
0 7 6
5
ZD25Q16B
Table3. Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed:50444653H
Add(H)
DW Add
Data
Data
(Byte)
(Bit)
00H
07:00
53H
53H
01H
15:08
46H
46H
02H
23:16
44H
44H
03H
31:24
50H
50H
SFDP Minor Revision Number
Start from 00H
04H
07:00
06H
06H
SFDP Major Revision Number
Start from 01H
05H
15:08
01H
01H
Number of Parameters Headers
Start from 00H
06H
23:16
01H
01H
Unused
Contains 0xFFH and can never
07H
31:24
FFH
FFH
08H
07:00
00H
00H
Start from 0x00H
09H
15:08
06H
06H
Start from 0x01H
0AH
23:16
01H
01H
Parameter Table Length
How many DWORDs in the
0BH
31:24
09H
09H
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
0CH
07:00
30H
30H
Parameter table
0DH
15:08
00H
00H
0EH
23:16
00H
00H
0FH
31:24
FFH
FFH
10H
07:00
BAH
BAH
be changed
ID number (JEDEC)
00H: It indicates a JEDEC
specified header
Parameter Table Minor
Revision Number
Parameter Table Major
Revision Number
Unused
Contains 0xFFH and can never
be changed
ID Number
It is indicates Zetta Device
(Zetta Device Manufacturer ID)
manufacturer ID
Parameter Table Minor
Start from 0x00H
11H
15:08
00H
00H
Start from 0x01H
12H
23:16
01H
01H
Parameter Table Length
How many DWORDs in the
13H
31:24
03H
03H
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of Zetta
14H
07:00
90H
90H
Device Flash Parameter
15H
15:08
00H
00H
table
16H
23:16
00H
00H
Contains 0xFFH and can never
17H
31:24
FFH
FFH
Revision Number
Parameter Table Major
Revision Number
Unused
be changed
38
ZD25Q16B
Table4. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
Data
Data
00: Reserved; 01: 4KB erase;
Block/Sector Erase Size
10: Reserved;
01:00
01b
02
1b
03
0b
11: not support 4KB erase
Write Granularity
Write Enable Instruction
Requested for Writing to
Volatile
Status Registers
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
1: Volatile status bit (BP
status register bit)
30H
0: Use 50H Opcode, 1:
Write Enable Opcode Select for
Use 06H Opcode,
Writing to Volatile Status Registers
Note: If target flash status
E5H
04
0b
07:05
111b
15:08
20H
16
1b
18:17
00b
19
0b
20
1b
register is Nonvolatile, then bits 3
and 4 must be set to 00b.
Unused
Contains 111b and can never be
changed
4KB Erase Opcode
31H
(1-1-2) Fast Read
0=Not support, 1=Support
Address Bytes Number used in
00: 3Byte only, 01: 3 or 4Byte,
addressing flash array
10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
clocking
0=Not support, 1=Support
32H
(1-2-2) Fast Read
0=Not support, 1=Support
(1-4-4) Fast Read
0=Not support, 1=Support
21
1b
(1-1-4) Fast Read
0=Not support, 1=Support
22
1b
23
1b
31:24
FFH
31:00
00FFFFFFH
Unused
Unused
33H
37H:34
Flash Memory Density
H
(1-4-4) Fast Read Number of
00000b: Wait states (Dummy
Wait states
Clocks) not support
(1-4-4) Fast Read Number of
Mode Bits
04:00
(1-4-4) Fast Read Opcode
39H
(1-1-4) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
(1-1-4) Fast Read Opcode
3BH
39
FFH
44H
07:05
010b
15:08
EBH
20:16
01000b
3AH
000b:Mode Bits not support
F1H
00100b
38H
000b:Mode Bits not support
20H
EBH
08H
23:21
000b
31:24
6BH
6BH
ZD25Q16B
Description
Comment
(1-1-2) Fast Read Number of
0 0000b: Wait states (Dummy
Wait states
Clocks) not support
(1-1-2) Fast Read Number
of Mode Bits
of Wait states
Clocks) not support
1=support
Unused
0=not support
01000b
07:05
000b
15:08
3BH
40H
1=support
Unused
3BH
00000b
3EH
3FH
Data
08H
20:16
000b: Mode Bits not support
0=not support
Data
3CH
(1-2-2) Fast Read Opcode
(4-4-4) Fast Read
(Bit)
3DH
0 0000b: Wait states (Dummy
(2-2-2) Fast Read
(Byte)
000b: Mode Bits not support
(1-2-2) Fast Read Number
of Mode Bits
DW Add
04:00
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number
Add(H)
80H
23:21
100b
31:24
BBH
00
0b
03:01
111b
04
0b
07:05
111b
BBH
EEH
Unused
43H:41H
31:08
0xFFH
0xFFH
Unused
45H:44H
15:00
0xFFH
0xFFH
20:16
00000b
(2-2-2) Fast Read Number
0 0000b: Wait states (Dummy
of Wait states
Clocks) not support
(2-2-2) Fast Read Number
of Mode Bits
46H
000b: Mode Bits not support
(2-2-2) Fast Read Opcode
Unused
(4-4-4)
of
Fast Read Number
Wait states
(4-4-4) Fast Read Number
of Mode Bits
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
47H
31:24
FFH
49H:48H
15:00
0xFFH
20:16
00000b
000b: Mode Bits not support
Sector Type 1 erase Opcode
Sector Type 2 Size
000b
4AH
(4-4-4) Fast Read Opcode
Sector Type 1 Size
23:21
0 0000b: Wait states (Dummy
Clocks) not support
00H
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode
40
FFH
0xFFH
00H
23:21
000b
4BH
31:24
FFH
FFH
4CH
07:00
0CH
0CH
4DH
15:08
20H
20H
4EH
23:16
0FH
0FH
4FH
31:24
52H
52H
50H
07:00
10H
10H
51H
15:08
D8H
D8H
52H
23:16
00H
00H
53H
31:24
FFH
FFH
ZD25Q16B
Table5. Parameter Table (1): Zetta Device Flash Parameter Tables
Description
Comment
2000H=2.000V
Vcc Supply Maximum Voltage
Add(H)
DW Add
(Byte)
(Bit)
61H:60
2700H=2.700V
H
3600H=3.600V
Data
Data
15:00
3600H
3600H
31:16
2700H
2700H
1650H=1.650V
Vcc Supply Minimum Voltage
2250H=2.250V
63H:62
2300H=2.300V
H
2700H=2.700V
HW Reset# pin
0=not support
1=support
00
0b
HW Hold# pin
0=not support
1=support
01
1b
Deep Power Down Mode
0=not support
1=support
02
1b
SW Reset
0=not support
1=support
03
1b
Should be issu Reset Enable(66H)
SW Reset Opcode
65H:64
before Reset cmd.
11:04
99H
H
799EH
Program Suspend/Resume
0=not support
1=support
12
1b
Erase Suspend/Resume
0=not support
1=support
13
1b
14
1b
15
0b
66H
23:16
FFH
FFH
67H
31:24
64H
64H
1=support
00
0b
1=Nonvolatile
01
0b
09:02
FFH
10
0b
11
1b
Unused
Wrap-Around Read mode
Wrap-Around
Read
0=not support
1=support
mode
Opcode
08H:support 8B wrap-around read
16H:8B&16B
Wrap-Around Read data length
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
0=not support
0=Volatile
Individual block lock Opcode
Individual block lock Volatile
protect bit default protect status
0=protect
1=unprotect
6BH:68
Secured OTP
0=not support
1=support
Read Lock
0=not support
1=support
12
0b
Permanent Lock
0=not support
1=support
13
1b
Unused
15:14
11b
Unused
31:16
FFFFH
H
41
EBFCH
FFFFH
ZD25Q16B
8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully
accessible
VWI
Time
Table6. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min.
tVSL
VCC (min) To CS# Low
1.8
VWI
Write Inhibit Voltage
1.5
Max.
Unit
ms
2.5
V
8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each Byte contains FFH).The
Status Register contains 00H (all Status Register bits are 0).
8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Operating Temperature
Value
Unit
-40 to 85
℃
-40 to 105
Storage Temperature
-65 to 150
Applied Input / Output Voltage
-0.6 to VCC+0.4
V
Transient Input / Output Voltage(note: overshoot)
-2.0 to VCC+2.0
V
-0.6 to 4.2
V
VCC
42
℃
ZD25Q16B
Figure38. Maximum Negative and Positive Overshoot Waveform
Maximum NegativeOvershoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
20ns
Vcc
20ns
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
CL
Load Capacitance
Min.
Typ.
Max.
Unit
pF
VIN=0V
8
pF
VOUT=0V
pF
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
V
Output Timing Reference Voltage
0.5VCC
43
Conditions
6
30
Input Rise And Fall time
20ns
V
ZD25Q16B
8.5. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit.
ILI
Input Leakage Current
±2
μA
ILO
Output Leakage Current
±2
μA
ICC1
Standby Current
CS#=VCC,
8
μA
VIN=VCC or VSS
ICC2
Deep Power-Down Current
CS#=VCC,
0.65
22
μA
3.1
4.2
mA
2.2
3.2
mA
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
at 120MHz,
ICC3
Operating Current (0B Read)
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
at 80MHz,
Q=Open(*1,*2,*4 I/O)
ICC4
Operating Current (PP)
CS#=VCC
3
mA
ICC5
Operating Current (WRSR)
CS#=VCC
3
mA
ICC6
Operating Current (SE)
CS#=VCC
2
mA
ICC7
Operating Current (BE)
CS#=VCC
2
mA
ICC8
Operating Current (CE)
CS#=VCC
2
mA
VIL
Input Low Voltage
0.2VCC
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL =100μA
VOH
Output High Voltage
IOH =-100μA
0.7VCC
V
0.2
VCC-0.2
Note:
1.
Typical values given for TA=25°C.
2.
Value guaranteed by design and/or characterization, not 100% tested inproduction.
44
V
V
ZD25Q16B
(T= -40℃~105℃, VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit.
ILI
Input Leakage Current
±2
μA
ILO
Output Leakage Current
±2
μA
ICC1
Standby Current
CS#=VCC,
8
μA
VIN=VCC or VSS
ICC2
Deep Power-Down Current
CS#=VCC,
0.65
25
μA
3.1
4.2
mA
2.2
3.2
mA
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
at 120MHz,
ICC3
Operating Current (0B Read)
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
at 80MHz,
Q=Open(*1,*2,*4 I/O)
ICC4
Operating Current (PP)
CS#=VCC
3.5
mA
ICC5
Operating Current (WRSR)
CS#=VCC
3.5
mA
ICC6
Operating Current (SE)
CS#=VCC
2.5
mA
ICC7
Operating Current (BE)
CS#=VCC
2.5
mA
ICC8
Operating Current (CE)
CS#=VCC
2.5
mA
VIL
Input Low Voltage
0.2VCC
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL =100μA
VOH
Output High Voltage
IOH =-100μA
0.7VCC
0.2
VCC-0.2
Note:
1.
V
Typical values given for TA=25°C.
Value guaranteed by design and/or characterization, not 100% tested inproduction
45
V
V
ZD25Q16B
8.6. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf)
Symbol
Parameter
Min.
Typ.
Max.
Unit.
104
MHz
80
MHz
120
MHz
120
MHz
80
MHz
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O (EBH),
FC
Quad Output (6BH) (Dual I/O & Quad I/O Without
High Performance Mode), on 3.0V-3.6V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O
fC1
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O
fC2
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O With High
Performance Mode), on 2.7V-3.6V power supply
Serial Clock Frequency For: Fast Read (0BH), Write Status
fC3
Register (01H) with or without High Performance Mode on
2.7V-3.6V power supply
fR
Serial Clock Frequency For: Read (03H) Read ID (90H, 9FH
and ABH), Read Status Register (05H and 35H)
tCLH
Serial Clock High Time
4
ns
tCLL
Serial Clock Low Time
4
ns
tCLCH
Serial Clock Rise Time (Slew Rate)
0.1
V/ns
tCHCL
Serial Clock Fall Time (Slew Rate)
0.1
V/ns
tSLCH
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
5
ns
tSHSL
CS# High Time (Read/Write)
20
ns
tSHQZ
Output Disable Time
tCLQX
Output Hold Time
1.2
ns
tDVCH
Data In Setup Time
2
ns
tCHDX
Data In Hold Time
2
ns
tHLCH
HOLD# Low Setup Time (Relative To Clock)
5
ns
tHHCH
HOLD# High Setup Time (Relative To Clock)
5
ns
tCHHL
HOLD# High Hold Time (Relative To Clock)
5
ns
tCHHH
HOLD# Low Hold Time (Relative To Clock)
5
ns
tHLQZ
HOLD# Low To High-Z Output
6
ns
tHHQX
HOLD# High To Low-Z Output
6
ns
tCLQV
Clock Low To Output Valid
7
ns
tWHSL
Write Protect Setup Time Before CS# Low
20
ns
tSHWL
Write Protect Hold Time After CS# High
100
ns
tDP
6
CS# High To Deep Power-Down Mode
25
46
ns
μs
ZD25Q16B
tRES1
tRES2
CS# High To Standby Mode Without Electronic Signature
Read
CS# High To Standby Mode With Electronic Signature
Read
tSUS
CS# High To Next Command After Suspend
tRS
Latency Between Resume And Next Suspend
μs
25
μs
20
μs
100
μs
CS# High To Next Command After Reset (Except From
tRST
25
WRSR)
CS# High To Next Command After Reset (From WRSR)
30
μs
4
ms
tW
Write Status Register Cycle Time
2.6
4
ms
tPP
Page Programming Time
1.1
1.6
ms
tSE
Sector Erase Time (4K Bytes)
5.1
7.6
ms
tBE1
Block Erase Time (32K Bytes)
5.1
7.6
ms
tBE2
Block Erase Time (64K Bytes)
5.1
7.6
ms
tCE
Chip Erase Time (ZD25Q16B)
5.2
7.8
ms
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested inproduction
47
ZD25Q16B
Symbol
Parameter
Min.
Typ.
Max.
Unit.
70
MHz
60
MHz
80
MHz
70
MHz
80
MHz
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O (EBH),
FC
Quad Output (6BH) (Dual I/O & Quad I/O Without
High Performance Mode), on 3.0V-3.6V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O
fC1
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O Without High
Performance Mode), on 2.7V-3.0V power supply
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O
fC2
(EBH), Quad Output (6BH) (Dual I/O & Quad I/O With High
Performance Mode), on 2.7V-3.6V power supply
Serial Clock Frequency For: Fast Read (0BH), Write Status
fC3
Register (01H) with or without High Performance Mode on
2.7V-3.6V power supply
fR
Serial Clock Frequency For: Read (03H) Read ID (90H, 9FH
and ABH), Read Status Register (05H and 35H)
tCLH
Serial Clock High Time
4
ns
tCLL
Serial Clock Low Time
4
ns
tCLCH
Serial Clock Rise Time (Slew Rate)
0.2
V/ns
tCHCL
Serial Clock Fall Time (Slew Rate)
0.2
V/ns
tSLCH
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
5
ns
tSHSL
CS# High Time (Read/Write)
20
ns
tSHQZ
Output Disable Time
tCLQX
Output Hold Time
1.2
ns
tDVCH
Data In Setup Time
2
ns
tCHDX
Data In Hold Time
2
ns
tHLCH
HOLD# Low Setup Time (Relative To Clock)
5
ns
tHHCH
HOLD# High Setup Time (Relative To Clock)
5
ns
tCHHL
HOLD# High Hold Time (Relative To Clock)
5
ns
tCHHH
HOLD# Low Hold Time (Relative To Clock)
5
ns
tHLQZ
HOLD# Low To High-Z Output
6
ns
tHHQX
HOLD# High To Low-Z Output
6
ns
tCLQV
Clock Low To Output Valid
7
ns
tWHSL
Write Protect Setup Time Before CS# Low
20
ns
tSHWL
Write Protect Hold Time After CS# High
100
ns
tDP
6
CS# High To Deep Power-Down Mode
25
(T= -40℃~105℃, VCC=2.7~3.6V, CL=30pf)
48
ns
μs
ZD25Q16B
tRES1
tRES2
CS# High To Standby Mode Without Electronic Signature
Read
CS# High To Standby Mode With Electronic Signature
Read
tSUS
CS# High To Next Command After Suspend
tRS
Latency Between Resume And Next Suspend
μs
25
μs
20
μs
100
μs
CS# High To Next Command After Reset (Except From
tRST
25
WRSR)
CS# High To Next Command After Reset (From WRSR)
30
μs
4.5
ms
4.5
ms
tW
Write Status Register Cycle Time
2.6
tPP
Page Programming Time
1.1
2
ms
tSE
Sector Erase Time (4K Bytes)
5.1
8.2
ms
tBE1
Block Erase Time (32K Bytes)
5.1
8.2
ms
tBE2
Block Erase Time (64K Bytes)
5.1
8.2
ms
tCE
Chip Erase Time (ZD25Q16B)
5.2
8.4
ms
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested inproduction
49
ZD25Q16B
3. Figure40. Serial Input Timing
tSHSL
CS#
tCHSL
SCLK
tCLH tCLL
tSLCH
tDVCH
tCHSH
MSB
SO
High - Z
tCHCL
tCLCH
tCHDX
SI
tSHCH
LSB
Figure41. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLL
tCLQX
tCLQX
tQLQH
LSB
tQHQL
SO
SI
Least
significant address bit (LIB) in
Figure 42. Resume to Suspend Timing Diagram
tRS
Resume Command
Suspend Command
CS#
Figure43. Hold Timing
CS#
SCLK
SO
tCHHL
tHLCH
tCHHH
tHLQZ
HOLD#
SI do not care during HOLD operation.
50
tHHCH
tHHQX
ZD25Q16B
9.
ORDERING INFORMATION
I:Industrial(-40℃~105℃)
51
ZD25Q16B
10. PACKAGE INFORMATION
10.1.
8-Lead SOP(150mil)
θ
8
5
E1
E
L
1
L1
h
4
C
D
A3
A2 A
A1
SEATING PLANE
0.10
b
e
Dimensions
Symbol
A
A1
A2
A3
b
C
D
E
E1
Min
-
0.10
1.30
0.6
0.39
0.20
4.80
5.80
3.80
Nom
-
-
1.40
0.65
-
-
4.90
5.90
3.90
Max
1.75
0.225
1.50
0.7
0.47
0.24
5.00
6.20
4.00
Min
-
Nom
-
Unit
mm
Inch
Max
0.004 0.051 0.024 0.015 0.008 0.189 0.228 0.150
-
0.055 0.026
-
-
0.069 0.009 0.059 0.028 0.019 0.009
TITLE
8-Lead SOP(150mil)
e
1.27
BSC
0.050
0.193 0.236 0.154 BSC
0.197 0.244 0.158
DRAWING NO.
REV
A
52
h
θ
0.25
0
-
-
0.80
0.50
8
0.020
0.010
0
-
-
0.020
8
L
L1
0.50
-
0.031
1.05
0.041
REF
JEDEC MS-012
ZD25Q16B
10.2.
8-Lead SOP(208mil)
θ
8
5
E1
E
L1
L
1
4
C
D
A3
A2
A
A1
SEATING PLANE
0.10
b
e
Dimensions
Symbol
A
A1
A2
A3
b
Min
1.75
0.05
1.70
0.55
0.38
Nom
1.9
0.1
1.80
0.60
0.43
Max
2.05
0.15
1.90
0.65
0.48
Min
0.069
0.002
0.067
0.022
0.015
Nom
0.075
0.004
0.071
0.024
0.017
Max
0.081
0.006
0.075
0.026
0.019
Unit
mm
Inch
TITLE
8-Lead SOP(208mil)
C
0.203
REF
0.008
REF
DRAWING NO.
D
E
E1
5.13
7.70
5.18
5.23
7.90
5.28
5.33
8.10
5.38
0.202
0.303
0.204
0.206
0.311
0.208
0.210
0.319
0.212
REV
A
53
e
1.27
REF
0.050
REF
L
L1
θ
0.50
1.21
0
0.65
1.31
-
0.80
1.41
8
0.020
0.048
0
0.026
0.052
-
0.031
0.056
8
REF
ZD25Q16B
10.3.
8-Lead TSSOP(173mil)
8
5
E1 E
“A”
1
4
C
D
b
A3
e
A2
A
0.25
GAUGE PLANE
L
A1
θ
L1
SEATING PLANE
DETAIL “A”
0.10
Dimensions
Symbol
A
A1
A2
A3
b
C
D
E
E1
Min
-
0.05
0.90
0.39
0.20
0.13
2.90
6.20
4.30
Nom
-
-
1.00
0.44
-
-
3.00
6.40
4.40
Max
1.20
0.15
1.05
0.49
0.28
0.17
3.10
6.60
4.50
Min
-
0.002
0.035
0.015
0.008
0.005
0.114
0.244
0.169
Nom
-
-
0.039
0.017
-
-
0.118
0.252
0.173
Max
0.047
0.006
0.041
0.019
0.011
0.007
0.122
0.260
0.177
Unit
mm
Inch
TITLE
8-lead TSSOP
DRAWING NO.
REV
A
54
e
0.65
BSC
0.026
BSC
L
0.45
0.75
0.018
0.030
L1
1.00
REF
0.039
REF
REF
JEDEC MO-153
θ
0
8
0
8
ZD25Q16B
10.4.
8-Land WSON(6x5mm)
D
b
e
L
h
h
PIN1
E
E1
D1
TOP VIEW
BOTTOM VIEW
A
A2
A1
SEATING PLANE
0.05
SIDE VIEW
Dimensions
Symbol
A
A1
b
D
D1
E
E1
Min
0.70
0.00
-
0.35
4.90
3.90
5.90
3.30
Nom
0.75
0.02
0.203
0.40
5.00
4.00
6.00
Max
0.80
0.05
-
0.48
5.10
4.10
Min
0.028
0.000
-
0.014
0.193
Nom
0.030
-
0.008
0.016
Max
0.032
0.002
-
0.019
Unit
mm
Inch
TITLE
DFN8 (0506X0.75-1.27)
A2
L
h
-
0.50
0.30
3.40
1.27
0.60
0.35
6.10
3.50
-
0.75
0.40
0.154
0.232
0.129
-
0.020
0.033
0.197
0.157
0.236
0.134
0.05
0.024
0.039
0.201
0.161
0.240
0.138
-
0.030
0.045
DRAWING NO.
REV
A
55
e
REF
JEDEC MO-220
ZD25Q16B
11. REVISION HISTORY
Version No
1.0
Description
Initial Release
56
Page
Date
All
2020-5-11
工商网监
湘ICP备2023018690号
