NPIC6C4894PWJ

NPIC6C4894 Power logic 12-bit shift register; open-drain outputs Rev. 1 — 17 April 2014 Product data sheet 1. General description The NPIC6C4894 is a 12-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input (D) to the parallel open-drain outputs (QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in each shift register stage is transferred to the storage register when the latch enable (LE) input is HIGH. Data in the storage register drives the gate of the output extended-drain NMOS transistor whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Two serial outputs (QS1 and QS2) are available for cascading a number of NIC6C4894 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. It is used for cascading NPIC6C4894 devices when the clock has a slow rise time. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs, provide protection against inductive transients. This protection makes the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads. 2. Features and benefits          Specified from 40 C to +125 C Low RDSon 12 Power EDNMOS transistor outputs of 100 mA continuous current 250 mA current limit capability Output clamping voltage 33 V 30 mJ avalanche energy capability Low power consumption Latch-up performance exceeds 100 mA per JESD 78 Class II level A ESD protection:  HBM JS-2011 Class 2 exceeds 2500 V  CDM JESD22-C101E exceeds 1000 V NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 3. Applications  LED sign  Graphic status panel  Fault status indicator 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NPIC6C4894D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 NPIC6C4894PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 5. Functional diagram    &3 /( 46  46  43  43  43  43  43  43  43  43  43  43  43  43  ' 2(  Fig 1. DDD Logic symbol NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 2 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs ' &3   67$*(6+,)75(*,67(5   /( 2(  46 %,76725$*(5(*,67(5  23(1'5$,12873876   43   43 43 Fig 2. 46    43 43  43 43   43   43 43 43 43 DDD Functional diagram VCC 43Q 9 GND *1' aaa-002550 Fig 3. DDD Schematic of all inputs Fig 4. 67$*( ' 4 ' 67$*(72 ' 46 Schematic of open-drain outputs (QPn) 67$*( ' )) )) &3 46 4 ' 4 46 /$7&+ &3 &3 /( ' ' 4 4 /$7&+  /$7&+  /( /( /( 2( 43 43 Fig 5. 43 43 DDD Logic diagram NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 3 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 6. Pinning information 6.1 Pinning 13,&& /(   9&& '   2( &3   43 43   43 43   43 43   43 43   43 43   43 43   46 *1'   46 DDD Fig 6. Pin configuration SO20 and TSSOP20 6.2 Pin description Table 2. Pin description Symbol Pin LE 1 latch enable input D 2 serial data input CP 3 clock input QP0 to QP11 4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13 parallel output Description GND 10 ground (0 V) QS1 11 serial output QS2 12 serial output OE 19 output enable input VCC 20 supply voltage NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 4 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 7. Functional description Table 3. Function table[1] At the positive clock edge, the information in the 10th register stage is transferred to the 11th register stage and the QS output Control Input Parallel output Serial output CP OE LE D QP0 QPn QS1[2] QS2[3]  L X X Z Z Q10S no change  L X X Z Z no change Q11S  H L X no change no change Q10S no change  H H L Z QPn1 Q10S no change  H H H L QPn1 Q10S no change  H H H no change no change no change Q11S [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition; Z = high-impedance OFF-state. [2] Q10S = the data in register stage 10 before the LOW to HIGH clock transition. [3] Q11S = the data in register stage 11 before the HIGH to LOW clock transition. &3LQSXW 'LQSXW /(LQSXW 2(LQSXW LQWHUQDO46 )) 43RXWSXW LQWHUQDO46 )) 43RXWSXW VHULDO46 RXWSXW VHULDO46 RXWSXW DDD Fig 7. Timing diagram NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 5 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V VI input voltage VDS drain-source voltage QPn 0.3 +7.0 V - +33 V VO output voltage QSn 0.5 +7.0 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 50 mA IOK output clamping current QSn; VO < 0.5 V or VO > VCC + 0.5 V Id(SD) source-drain diode current continuous - 100 mA - 250 mA - 500 mA - 100 mA [2] - 250 mA single output; Tamb = 25 C [2] - 250 mA - 30 mJ - 200 mA 65 +150 C - 1500 mW - 1250 mW [1] pulsed drain current ID [2] Tamb = 25 C continuous; each output; all outputs on pulsed; each output; all outputs on peak drain current IDM EAS non-repetitive avalanche energy single pulse; see Figure 8 and Figure 16 [3] IAL avalanche current see Figure 8 and Figure 16 [3] Tstg storage temperature Tamb = 25 C [4] total power dissipation Ptot SO20 TSSOP20 Tamb = 125 C [4] SO20 - 300 mW TSSOP20 - 250 mW [1] Each power EDNMOS source is internally connected to GND. [2] Pulse duration  100 s and duty cycle  2 %. [3] VDS = 15 V; starting junction temperature (Tj) = 25 C; L = 1.5 H; avalanche current (IAL) = 200 mA. [4] For SO20 package: above 25 C the value of Ptot derates linearly with 12 mW/C. For TSSOP20 package: above 25 C the value of Ptot derates linearly with 10 mW/C. NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 6 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 8.1 Test circuit and waveform 9 9  9&&  :25' *(1(5$725    O2 &3 ' '87 43Q   W$/ WZ ȍ 9 + 9 O$/ P$ 92 ,2 /( 2( 9%5'66 9 92 *1' PLQ  DDD (1) The word generator has the following characteristics: tr, tf  10 ns; ZO = 50 . (2) The input pulse duration (tW) is increased until peak current IAL = 200 mA. Energy test level is defined as: EAS = IAL  V(BR)DSS  tAL/2 = 30 mJ. Fig 8. Test circuit and waveform for measuring single-pulse avalanche energy 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage ID drain current Tamb ambient temperature Conditions 4.5 pulsed drain output current; VCC = 5 V; Tamb = 25 C; all outputs on Pulse duration  100 s and duty cycle  2 %. [2] Technique should limit Tj  Tamb to 10 C maximum. Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 [1][2] Typ Max Unit 5.0 5.5 V - 5.5 V - - 250 mA 40 - +125 C 0 [1] NPIC6C4894 Min © Nexperia B.V. 2017. All rights reserved 7 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 10. Static characteristics Table 6. Static characteristics At recommended operating conditions unless otherwise specified; Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to 125 C Unit Min Typ Max Min Typ Max VIH HIGH-level input voltage 0.85VCC - - - - - V VIL LOW-level input voltage - - 0.15VCC - - - V VOH HIGH-level QSn; VI = VIH or VIL output voltage IO = 20 A; VCC = 4.5 V 4.4 4.49 - - - - V IO = 4 mA; VCC = 4.5 V 4.0 4.2 - - - - V LOW-level QSn; VI = VIH or VIL output voltage IO = 20 A; VCC = 4.5 V VOL - 0.005 0.1 - - - V - 0.3 0.5 - - - V - - 1 - - - A 37 - - - - V 1.2 0.85 - - - - V OE = LOW - 0.006 200 - - - A OE = HIGH - 0.01 500 - - - A OE = LOW; CP = 5 MHz; see Figure 15 and Figure 17 - 1 5 - - - mA - 140 - - - - mA - 0.002 0.2 - 0.15 0.3 A VCC = 4.5 V; IO = 50 mA - 2.7 9 - VCC = 4.5 V; IO = 100 mA - 2.8 10 - IO = 4 mA; VCC = 4.5 V input leakage current II VCC = 5.5 V; VI = VCC or GND V(BR)DSS drain-source breakdown voltage QPn; IO = 1 mA 33 VSD source-drain voltage QPn; IO = 100 mA ICC supply current VCC = 5.5 V; VI = VCC or GND [1][2][3] IO output current QPn; VO = 0.5 V IOZ OFF-state QPn; VCC = 5.5 V; VDS = 30 V output current RDSon drain-source on-state resistance see Figure 18 and Figure 19 [1][2] [1] Technique should limit Tj  Tamb to 10 C maximum. [2] These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. [3] 4.3  12 - -  The output current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V. NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 8 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 11. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions unless otherwise specified; Voltages are referenced to GND (ground = 0 V); For test circuit, see Figure 15. Symbol Parameter Tamb = 25 C Conditions Unit Min Typ Max - 5 - ns QPn; see Figure 12 - 60 - ns QSn; see Figure 9 - 6 - ns HIGH to LOW output transition time QPn; see Figure 12 - 18 - ns QSn; see Figure 9 - 6 - ns tPLZ LOW to OFF-state propagation delay CP, LE and OE to QPn; IO = 75 mA; see Figure 10, Figure 11, Figure 12 and Figure 20 - 105 - ns tPZL OFF-state to LOW propagation delay CP, LE and OE to QPn; IO = 75 mA; see Figure 10, Figure 11, Figure 12 and Figure 20 - 10 - ns fclk(max) maximum clock frequency CP; see Figure 9 10 - - MHz tsu set-up time D to CP; see Figure 13 20 - - ns th hold time D to CP; see Figure 13 20 - - ns tW pulse width CP, LE; see Figure 9 and Figure 11 trr ta reverse recovery current rise time [1] tpd is the same as tPLH and tPHL. tpd propagation delay CP to QSn; see Figure 9 tTLH LOW to HIGH output transition time tTHL [2] [1] [2] 40 - - ns reverse recovery time IO = 100 mA; dI/dt = 10 A/s; see Figure 14 [3][4] - 120 - ns IO = 100 mA; dI/dt = 10 A/s; see Figure 14 [3][4] - 100 - ns This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second stage. The clock period allows for CP → QSn propagation delay and setup time plus some timing margin. [3] Technique should limit Tj  Tamb to 10 C maximum. [4] These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 9 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 11.1 Waveforms and test circuits IFONPD[ 9, &3LQSXW 90 *1' W: W: W3/+ 92+ W3+/  46RXWSXW 90 92/  W7/+ W7+/ W3+/ 92+  90 46RXWSXW  92/ W7/+ W7+/ DDD Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Propagation delay clock (CP) to output (QS1, QS2), clock pulse width, maximum clock frequency and output transition time 9, 90 &3LQSXW *1' W3/= W3=/ 9 43QRXWSXW 92/ 9< 9; DDD Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Propagation delay clock (CP) to output (QPn) NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 10 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 9, 90 &3LQSXW *1' 9, /(LQSXW 90 *1' W: W3/= W3=/ 9 9< 43QRXWSXW 9; 92/ DDD Measurement points are given in Table 8. VOL is the typical output voltage level that occurs with the output load. Fig 11. Latch enable (LE) to output (QPn) propagation delays and the latch enable pulse width 9, 2(LQSXW 90 *1' W3/= 9 W3=/ 9< 9< 43QRXWSXW 9; 9; 92/ W7/+ RXWSXWV HQDEOHG W7+/ RXWSXWV GLVDEOHG RXWSXWV HQDEOHG DDD Measurement points are given in Table 8. VOL is the typical output voltage level that occurs with the output load. Fig 12. Output enable (OE) to output (QPn) and output transition time NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 11 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 9, 90 &3LQSXW *1' WVX 9, WVX WK WK 90 'LQSXW *1' 9 43QRXWSXW 92/ DDD Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL is the typical output voltage level that occurs with the output load. Fig 13. Set-up and hold times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY 5V 0.5VCC 0.5VDS 0.1VDS 0.9VDS . 43Q '87 P+ —) 9 $ 9 GLGW $—V ,2 ,2 $  W W RI,50 W GULYHU 5* 9, * ,50 WD ȍ WUU DDD (1) The open-drain QPn terminal under test is connected to testpoint K. All other terminals are connected together and connected to testpoint A. (2) The VI amplitude and RG are adjusted for dI/dt = 10 A/s. A VI double-pulse train is used to set IO = 0.1 A, where t1 = 10 s, t2 = 7 s and t3 = 3 s. Fig 14. Test circuit and waveform for measuring reverse recovery current NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 12 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs W: 9,  QHJDWLYH SXOVH 90 90  9 9, WI WU WU WI  90 SRVLWLYH SXOVH 90  9 W: 9(;7 9 9  5/ 9&&  :25' *(1(5$725    &3 43Q ' 46Q /( 2(    &/ &/ 5/ *1'  DDD (1) The word generator has the following characteristics: tr, tf  10 ns; tW = 300 ns; pulsed repetition rate (PRR) = 5 kHz; ZO = 50 . (2) CL includes probe and jig capacitance. Test data is given in Table 9. Definitions for test circuit: VEXT = External voltage for measuring switching times. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 15. Test circuit for measuring switching times Table 9. Test data Supply voltage Input 5V [1] Load VI tr, tf VM CL RL1 RL2[1] 5V  10 ns 50% 30 pF 200  2 k Do not connect RL2 when measuring the supply current (ICC). NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 13 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs aaa-002562 1 DDD  ,&& P$  IAL (A)  10-1    10-2 10-1 1 10      tAL (ms) IO0+] Tamb = 25 C; VCC = 5 V. Tamb = 40 C to 125 C; VCC = 5 V. Fig 16. Avalanche current (peak) versus time duration of avalanche DDD   DDD   5'6RQ ȍ Fig 17. Supply current versus frequency 5'6RQ ȍ                       ,2P$ VCC = 4.5 V; VI = VCC or GND.    VI = VCC or GND; IO = 50 mA. (1) Tamb = 125 C (2) Tamb = 85 C (2) Tamb = 85 C (3) Tamb = 25 C (3) Tamb = 25 C (4) Tamb = 40 C (4) Tamb = 40 C Fig 18. Drain-source on-state resistance versus drain current Product data sheet  9&&9 (1) Tamb = 125 C NPIC6C4894  Fig 19. Static drain-source on-state resistance versus supply voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 14 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs DDD  W QV                7DPEƒ& VCC = 5 V; IO = 75 mA, this technique should limit Tj  Tamb to 10 C maximum. (1) tPLZ. (2) tTLH. (3) tTHL. (4) tPZL. Fig 20. Switching time versus temperature NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 15 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' $ ( ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ PP                                           LQFKHV        =       ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 21. Package outline SOT163-1 (SO20) NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 16 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F +( \ Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 22. Package outline SOT360-1 (TSSOP20) NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 17 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test EDNMOS Extended Drain Negative Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes NPIC6C4894 v.1 20140417 Product data sheet - - NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 18 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. 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NPIC6C4894 Product data sheet Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 19 of 21 NPIC6C4894 Nexperia Power logic 12-bit shift register; open-drain outputs Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com NPIC6C4894 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 17 April 2014 © Nexperia B.V. 2017. All rights reserved 20 of 21 Nexperia NPIC6C4894 Power logic 12-bit shift register; open-drain outputs 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 8.1 9 10 11 11.1 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuit and waveform . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms and test circuits . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 17 April 2014