SIT2025BI-S3-30N-125.000000G

SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Features         Applications AEC-Q100 with extended temperature range (-55°C to 125°C) Frequencies between 115.2 MHz and 137 MHz accurate to 6 decimal points 100% pin-to-pin drop-in replacement to quartz-based XO Excellent total frequency stability as low as ±20 ppm Industry best G-sensitivity of 0.1 PPB/G LVCMOS/LVTTL compatible output 5-pin SOT23-5 package: 2.9 x 2.8 mm x mm RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-free    Automotive, extreme temperature and other high-rel electronics Infotainment systems, collision detection devices, and in-vehicle networking Powertrain control Electrical Characteristics Table 1. Electrical Characteristics All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and nominal supply voltage. Parameters Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range Frequency Stability f F_stab 115.20 – -20 – -25 – -30 – -50 – 137 MHz Refer to Tables 14 to 16 for the exact list of supported frequencies Frequency Stability and Aging Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and +20 ppm variations over operating temperature, rated power supply voltage +25 ppm and load (15 pF ± 10%). +30 ppm +50 ppm Operating Temperature Range Operating Temperature Range (ambient) T_use -40 – +85 °C AEC-Q100 Grade 3 -40 – +105 °C AEC-Q100 Grade 2 -40 – +125 °C AEC-Q100 Grade 1 -55 – +125 °C Extended cold, AEC-Q100 Grade1 Supply Voltage and Current Consumption Supply Voltage Current Consumption Vdd 1.62 1.8 1.98 V 2.25 – 3.63 V – 6 8 mA No load condition, f = 125 MHz, Vdd = 2.25V to 3.63V – 4.9 6 mA No load condition, f = 125 MHz, Vdd = 1.62V to 1.98V DC 45 – 55 % Tr, Tf – 1.5 3 ns Vdd = 2.25V - 3.63V, 20% - 80% – 1.5 2.5 ns Vdd = 1.8V, 20% - 80% Idd All voltages between 2.25V and 3.63V including 2.5V, 2.8V, 3.0V and 3.3V are supported. Contact SiTime for 1.5V support LVCMOS Output Characteristics Duty Cycle Rise/Fall Time Output High Voltage VOH 90% – – Vdd IOH = -4 mA (Vdd = 3.0V or 3.3V) IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V) IOH = -2 mA (Vdd = 1.8V) Output Low Voltage VOL – – 10% Vdd IOL = 4 mA (Vdd = 3.0V or 3.3V) IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V) IOL = 2 mA (Vdd = 1.8V) Input High Voltage VIH 70% – – Vdd Pin 1, OE Input Low Voltage VIL – – 30% Vdd Pin 1, OE Input Pull-up Impedance Z_in – 100 – kΩ Pin 1, OE logic high or logic low Input Characteristics Startup and Resume Timing Startup Time T_start Enable/Disable Time T_oe – – – – 5.5 130 ms ns f = 115.20 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles Standby Current I_std – 2.6 – µA Vdd = 2.8V to 3.3V, ST = Low, Output is weakly pulled down – 1.4 – µA Vdd = 2.5V, ST = Low, Output is weakly pulled down – 0.6 – µA Vdd = 1.8V, ST = Low, Output is weakly pulled down Rev. 1.7 May 22, 2019 Measured from the time Vdd reaches its rated minimum value www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Table 1. Electrical Characteristics (continued) Parameters Symbol Min. Typ. Max. Unit Condition Jitter T_jitt RMS Period Jitter T_phj RMS Phase Jitter (random) – 1.6 2.5 ps f = 125 MHz, 2.25V to 3.63V – 1.8 3 ps f = 125 MHz, 1.8V – 0.7 – ps f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz – 1.5 – ps f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz Table 2. Pin Description Top View Symbol Functionality 1 GND Power 2 NC No Connect Output Enable 3 OE/NC No Connect Electrical ground[1] GND 1 NC 2 OE/NC 3 YXXXX Pin No connect H[2]: specified frequency output L: output is high impedance. Only output driver is disabled. Any voltage between 0 and Vdd or Open[2]: Specified frequency output. Pin 3 has no function. 5 OUT 4 VDD [1] 4 VDD Power Power supply voltage 5 OUT Output Oscillator output Figure 1. Pin Assignments Notes: 1. A capacitor of value 0.1 µF or higher between Vdd and GND is required. 2. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option. Table 3. Absolute Maximum Limits Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Min. Max. Unit Storage Temperature Parameter -65 150 °C Vdd -0.5 4 V Electrostatic Discharge – 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) – 260 °C Junction Temperature[3] – 150 °C Note: 3. Exceeding this temperature for extended period of time may damage the device. Table 4. Thermal Consideration[4] Package SOT23-5 θJA, 4 Layer Board θJC, Bottom (°C/W) (°C/W) 421 175 Note: 4. Refer to JESD51 for θJA and θJC definitions, and reference layout used to determine the θJA and θJC values in the above table. Table 5. Maximum Operating Junction Temperature[5] Max Operating Temperature (ambient) Maximum Operating Junction Temperature 85°C 95°C 105°C 115°C 125°C 135°C Note: 5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. Table 6. Environmental Compliance Parameter Condition/Test Method Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensitivity Level MSL1 @ 260°C Rev. 1.7 Page 2 of 15 www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Test Circuit and Waveform Vout Test Point Vdd tr 15 pF (including probe and fixture capacitance) 80% Vdd 4 5 1 2 tf Power Supply 0.1µF 3 50% 20% Vdd High Pulse (TH) Period Vdd 1k Low Pulse (TL) OE/ST Function Figure 3. Waveform[6] Figure 2. Test Circuit[6] Note: 6. SiT2025 has “no runt” pulses and “no glitch” output during startup or resume. Timing Diagrams Vdd 90% Vdd Vdd 50% Vdd T_oe T_start Pin 4 Voltage OE Voltage No Glitch during start up CLK Output CLK Output HZ HZ T_oe: Time to re-enable the clock output T_start: Time to start from power-off Figure 4. Startup Timing (OE Mode)[7] Figure 5. OE Enable Timing (OE Mode Only) Vdd OE Voltage 50% Vdd T_oe CLK Output HZ T_oe: Time to put the output in High Z mode Figure 6. OE Disable Timing (OE Mode Only) Note: 7. SiT2025 has “no runt” pulses and “no glitch” output during startup or resume. Rev. 1.7 Page 3 of 15 www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Performance Plots[8] 1.8 2.5 2.8 3.0 3.3 DUT1 DUT2 DUT3 DUT4 DUT5 DUT6 DUT7 6.5 DUT8 DUT9 DUT10 DUT11 DUT12 DUT13 DUT14 6.3 DUT15 DUT16 DUT17 DUT18 DUT19 DUT20 25 6.1 20 15 Frequency (ppm) Idd (mA) 5.9 5.7 5.5 5.3 5.1 4.9 10 5 0 -5 -10 -15 4.7 -20 4.5 -25 115 117 119 121 123 125 127 129 131 133 135 -55 137 -35 -15 5 Frequency (MHz) 2.8 V 3.3 V 3.0 V 1.8 V 4.0 55 3.5 54 2.5 2.0 1.5 105 125 2.5 V 2.8 V 3.0 V 3.3 V 52 51 50 49 48 47 46 45 0.0 115 117 119 121 123 125 127 129 131 133 135 115 137 117 119 121 123 Figure 9. RMS Period Jitter vs Frequency 1.8 V 2.5 V 2.8 V 125 127 129 131 133 135 137 Frequency (MHz) Frequency (MHz) Figure 10. Duty Cycle vs Frequency 1.8 V 3.3 V 3.0 V 2.5 2.5 2.0 2.0 Fall time (ns) Rise time (ns) 85 1.0 0.5 1.5 1.0 0.5 2.5 V 2.8 V 3.0 V 3.3 V 1.5 1.0 0.5 0.0 0.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 Temperature (°C) -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Figure 12. 20%-80% Fall Time vs Temperature Figure 11. 20%-80% Rise Time vs Temperature Rev. 1.7 65 53 3.0 Duty cycle (%) RMS period jitter (ps) 2.5 V 45 Figure 8. Frequency vs Temperature Figure 7. Idd vs Frequency 1.8 V 25 Temperature (°C) Page 4 of 15 www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Performance Plots[8] 2.5 V 1.8 V 2.8 V 3.0 V 3.3 V 1.8 V 2.0 2.5 V 3.0 V 2.8 V 3.3 V 1.0 0.9 1.8 IPJ (ps) IPJ (ps) 0.8 1.6 1.4 0.7 0.6 1.2 0.5 1.0 115 117 119 121 123 125 127 129 131 133 135 137 Frequency (MHz) 0.4 115 117 119 121 123 125 127 129 131 133 135 137 Frequency (MHz) Figure 13. RMS Integrated Phase Jitter Random (12 kHz to 20 MHz) vs Frequency[9] Figure 14. RMS Integrated Phase Jitter Random (900 kHz to 20 MHz) vs Frequency[9] Notes: 8. All plots are measured with 15 pF load at room temperature, unless otherwise stated. 9. Phase noise plots are measured with Agilent E5052B signal source analyzer. Rev. 1.7 Page 5 of 15 www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Programmable Drive Strength The SiT2025 includes a programmable drive strength feature to provide a simple, flexible tool to optimize the clock rise/fall time for specific applications. Benefits from the programmable drive strength feature are:  Improves system radiated electromagnetic interference (EMI) by slowing down the clock rise/fall time.  Improves the downstream clock receiver’s (RX) jitter by decreasing (speeding up) the clock rise/fall time.  Ability to drive large capacitive loads while maintaining full swing with sharp edge rates. For more detailed information about rise/fall time control and drive strength selection, see the SiTime Application Notes section. The SiT2025 can support up to 30 pF in maximum capacitive loads with up to 3 additional drive strength settings. Refer to the Rise/Fall Time Tables (Table 7 to 11) to determine the proper drive strength for the desired combination of output load vs. rise/fall time. SiT2025 Drive Strength Selection Tables 7 through 11 define the rise/fall time for a given capacitive load and supply voltage. 1. Select the table that matches the SiT2025 nominal supply voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V). 2. Select the capacitive load column that matches the application requirement (5 pF to 30 pF) 3. Under the capacitive load column, select the desired rise/fall times. 4. The left-most column represents the part number code for the corresponding drive strength. 5. Add the drive strength code to the part number for ordering purposes. EMI Reduction by Slowing Rise/Fall Time Figure 15 shows the harmonic power reduction as the rise/fall times are increased (slowed down). The rise/fall times are expressed as a ratio of the clock period. For the ratio of 0.05, the signal is very close to a square wave. For the ratio of 0.45, the rise/fall times are very close to neartriangular waveform. These results, for example, show that the 11th clock harmonic can be reduced by 35 dB if the rise/fall edge is increased from 5% of the period to 45% of the period. Calculating Maximum Frequency Based on the rise and fall time data given in Tables 7 through 11, the maximum frequency the oscillator can operate with guaranteed full swing of the output voltage over temperature as follows: Max Frequency = 1 5 x Trf_20/80 where Trf_20/80 is the typical value for 20%-80% rise/fall time. Example 1 Calculate fMAX for the following condition: Figure 15. Harmonic EMI reduction as a Function of Slower Rise/Fall Time Jitter Reduction with Faster Rise/Fall Time Power supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to speed up the rise/fall time of the input clock. Some chipsets may also require faster rise/fall time in order to reduce their sensitivity to this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to Table 11) to determine the proper drive strength.  Vdd = 3.3V (Table 11)  Capacitive Load: 30 pF  Desired Tr/f time = 1.46 ns (rise/fall time part number code = U) Part number for the above example: SiT2025BAE12-18E-137.000000 Drive strength code is inserted here. Default setting is “-” High Output Load Capability The rise/fall time of the input clock varies as a function of the actual capacitive load the clock drives. At any given drive strength, the rise/fall time becomes slower as the output load increases. As an example, for a 3.3V SiT2025 device with default drive strength setting, the typical rise/fall time is 0.46 ns for 5 pF output load. The typical rise/fall time slows down to 1 ns when the output load increases to 15 pF. One can choose to speed up the rise/fall time to 0.72 ns by then increasing the driven strength setting on the SiT2025 to “F”. Rev. 1.7 Page 6 of 15 www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Rise/Fall Time (20% to 80%) vs CLOAD Tables Table 7. Vdd = 1.8V Rise/Fall Times for Specific CLOAD Table 8. Vdd = 2.5V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF Drive Strength \ CLOAD 5 pF 15 pF T 0.93 n/a R 1.45 n/a E 0.78 n/a B 1.09 n/a U 0.70 1.48 T or "-": default 0.62 1.28 F or "-": default 0.65 1.30 E 0.54 1.00 U 0.43 0.96 F 0.34 0.88 Table 9. Vdd = 2.8V Rise/Fall Times for Specific CLOAD Table 10. Vdd = 3.0V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF R 1.29 n/a n/a R 1.22 n/a n/a B 0.97 n/a n/a B 0.89 n/a n/a T or "-": default 0.55 1.12 n/a T or "-": default 0.51 1.00 n/a E 0.44 1.00 n/a E 0.38 0.92 n/a U 0.34 0.88 n/a U 0.30 0.83 n/a F 0.29 0.81 1.48 F 0.27 0.76 1.39 Table 11. Vdd = 3.3V Rise/Fall Times for Specific CLOAD Rise/Fall Time Typ (ns) Drive Strength \ CLOAD 5 pF 15 pF 30 pF R 1.16 n/a n/a B 0.81 n/a n/a T or "-": default 0.46 1.00 n/a E 0.33 0.87 n/a U 0.28 0.79 1.46 F 0.25 0.72 1.31 Note: 10. “n/a” indicates that the resulting rise/fall time from the respective combination of the drive strength and output load does not provide rail-to-rail swing and is not available. Rev. 1.7 Page 7 of 15 www.sitime.com SiT2025B High Frequency, Automotive AEC-Q100 SOT23 Oscillator Pin 1 Configuration Options (OE or NC) Pin 1 of the SiT2025 can be factory-programmed to support two modes: Output Enable (OE) or No Connect (NC). These modes can also be programmed with the Time Machine II using Field Programmable Oscillators. In addition, the SiT2025 supports “no runt” pulses and “no glitch” output during startup or when the output driver is reenabled from the OE disable mode as shown in the waveform captures in Figure 16 and Figure 17. Output Enable (OE) Mode In the OE mode, applying logic low to the OE pin only disables the output driver and puts it in Hi-Z mode. The core of the device continues to operate normally. Power consumption is reduced due to the inactivity of the output. When the OE pin is pulled High, the output is typically enabled in