TF2106M-TAH

TF2106M High-Side and Low-SideGate Driver Features Description  F  loating high-side driver in bootstrap operation to 600V  Drives two N-channel MOSFETs or IGBTs in high-side/ low-side configuration  Outputs tolerant to negative transients  Wide low-side gate driver and logic supply: 10V to 20V  Logic inputs CMOS and TTL compatible (down to 3.3V)  Schmitt triggered logic inputs with internal pull down  Undervoltage lockout for VCC  Space-saving SOIC-8 package available  Extended temperature range:-40oC to +125oC The TF2106M is a high voltage, high speed gate driver capable of driving N-channel MOSFETs and IGBTs in a high-side/lowside configuration . TF Semiconductor ’s high voltage process enables the TF2106’s high-side to switch to 600V in a bootstrap operation . The 50 ns (max ) propagation delay matching between the high and the low side drivers allows high frequency switching. The TF2106M is available in a space -saving 8-pin SOIC package and a 8-pin PDIP; the operating temperature extends from -40 °C to +125°C . Applications  DC-DC Converters  AC-DC Inverters  Motor Controls  Class D Power Amplifiers SOIC-8(N) Up to 600V VCC VCC VB HIN HIN HO LIN LIN R4 COM www.tfsemi.com July 2019 VS LO PDIP-8 Ordering Information Typical Application TF2106M The TF2106M logic inputs are compatible with standard TTL and CMOS levels (down to 3.3V) for easy interfacing with controlling devices . The driver outputs feature high pulse current buffers designed for minimum driver cross conduction . The low -side gate driver and logic share a common ground TO LOAD Year Year Week Week PART NUMBER PACKAGE PACK / Qty TF2106M-TAU SOIC-8(N) Tube / 100 TF2106M-TAH SOIC-8(N) T & R/ 2500 TF2106M-3AS PDIP-8 Tube / 50 MARK YYWW TF2106 Lot ID YYWW TF2106 Lot ID YYWW TF2106 Lot ID Rev. 1.2 1 TF2106M High Side and Low Side Gate Driver Pin Diagrams VCC 1 8 VB HIN 2 7 HO LIN 3 6 VS COM 4 5 LO Top View: PDIP-8, SOIC-8 TF2106M Pin Descriptions PIN NAME PIN DESCRIPTION HIN Logic input for high-side gate driver output (HO), in phase LIN Logic input for low-side gate driver output (LO), in phase VB High-side floating supply HO High-side gate drive output VS High-side floating supply return VCC Low-side and logic fixed supply LO Low-side gate drive output COM Low-side return NC “No connect” pin Functional Block Diagram VCC Vcc HIN TF2106M VB UV Detect UV Detect VSS/COM Level Shift Pulse Gen HV Level Shift/ Pulse Filter R Q HO R S High Voltage Well Vs VCC LIN VSS/COM Level Shift Delay LO COM July 2019 2 TF2106M High Side and Low Side Gate Driver Absolute Maximum Ratings (NOTE1) A VB - High side floating supply voltage...............-0.3V to +624V VS - High side floating supply offset voltage....VB -24V to VB+0.3V VHO - High side floating output voltage...............VS-0.3V to VB+0.3V dVS / dt - Offset supply voltage transient...............................50 V/ns PD - Package power dissipation at TA ≤ 25 °C SOIC-8.............................................................................................0.625W PDIP-8..................................................................................................1.0W VCC - Low side and logic fixed supply voltage..............-0.3V to +24V VLO - Low side output voltage..................................-0.3V to VCC+0.3V VIN - Logic input voltage (HIN and LIN)... -0.3V to VCC+0.3V NOTE1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOIC-8 Thermal Resistance (NOTE2) qJC..................................................................................................45 °C/W qJA ...............................................................................................200 °C/W PDIP-8 Thermal Resistance (NOTE2) qJC..................................................................................................35 °C/W qJA ................................................................................................125 °C/W TJ - Junction operating temperature .......................................+150 °C TL - Lead temperature (soldering, 10s) .................................. +300 °C Tstg - Storage temperature range ............................-55 °C to +150 °C NOTE2 When mounted on a standard JEDEC 2-layer FR-4 board. Recommended Operating Conditions Symbol Parameter VB High side floating supply absolute voltage VS High side floating supply offset voltage VHO MIN TYP MAX Unit VS + 10 VS + 20 V NOTE3 600 V High side floating output voltage VS VB V VCC Low side and logic fixed supply voltage 10 20 V VLO Low side output voltage 0 VCC V VIN Logic input voltage (HIN and LIN) 0 5 V TA Ambient temperature -40 125 °C NOTE3 Logic operational for VS = -5 to +600V. July 2019 3 TF2106M High Side and Low Side Gate Driver DC Electrical Characteristics (NOTE4) VBIAS (VCC, VBS ) = 15V, TA = 25 °C , unless otherwise specified. Symbol Parameter Conditions MIN VIH Logic “1” input voltage VCC = 10V to 20V 2.5 VIL Logic “0” input voltage VOH High level output voltage, VBIAS - VO IO = 2mA VOL Low level output voltage, VO IO = 2mA ILK Offset supply leakage current VB = VS = 600V IBSQ Quiescent VBS supply current VIN = 0V or 5V 20 ICCQ Quiescent VCC supply current VIN = 0V or 5V 60 IIN+ Logic “1” input bias current VIN = 5V IIN- Logic “0” input bias current VIN = 0V VCCUV+ VCC supply under-voltage positive going threshold 8 VCCUV- VCC supply under-voltage negative going threshold VBSUV+ TYP MAX Unit V NOTE5. 0.6 V 0.05 0.2 V 0.02 0.1 V 50 mA 75 130 mA 120 180 mA 5 20 mA 2 mA 8.9 9.8 V 7.4 8.2 9 V VBS supply under-voltage positive going threshold 8 8.9 9.8 V VBSUV- VCC supply under-voltage negative going threshold 7.4 8.2 9 V VUVLOH Undervoltage lockout hysteresis 0.3 0.7 V IO+ Output high short circuit pulsed current VO = 0V, VIN = Logic “1”, PW ≤ 10 ms 130 290 mA IO- Output low short circuit pulsed current VO = 15V, VIN = Logic “0”, PW ≤ 10 ms 270 600 mA MIN TYP MAX Unit AC Electrical Characteristics VBIAS (VCC, VBS ) = 15V, TA = 25 °C, and CL = 1000pF, unless otherwise specified. Symbol Parameter Conditions tON Turn-on propagation delay VS = 0V 220 300 ns tOFF Turn-off propagation delay VS = 0V or 600V 200 280 ns tr Turn-on rise time 100 220 ns tf Turn-off fall time 35 80 ns tDM Delay matching 30 ns VS = 0V NOTE4 The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output pins: HO and LO. NOTE5 For optimal operation, it is recommended that the input pulse (to HIN and LIN) should have an amplitude of 2.5V minimum with a pulse width of 440ns minimum. July 2019 4 TF2106M High Side and Low Side Gate Driver Timing Waveforms HIN LIN HIN LIN 50% 50% tON HO LO HO LO Figure 1. Input / Output Timing Diagram HIN LIN 50% LO tr tOFF 90% 90% 10% tf 10% Figure 2. Switching Time Waveform Definitions 50% HO 10% tDM tDM 90% LO HO Figure 3. Delay Matching Waveform Definitions July 2019 5 TF2106M High Side and Low Side Gate Driver Typical Characteristics 150 140 130 ton High Side 120 ton Low Side Turn On Propagation Delay (ns) Turn On Propagation Delay (ns) 150 110 100 90 80 70 60 50 10 12 14 16 18 140 130 ton High Side 120 ton Low Side 110 100 90 80 70 60 50 20 -40 -20 0 Supply Voltage (V) 80 100 120 150 140 130 toff High Side 120 toff Low Side Turn Off Propagation Delay (ns) Turn Off Propagation Delay (ns) 60 Figure 5. Turn-on Propagation Delay vs. Temperature 150 110 100 90 80 70 60 50 10 12 14 16 18 140 130 toff High Side 120 toff Low Side 110 100 90 80 70 60 50 20 -40 -20 0 Supply Voltage (V) 20 40 60 80 100 120 Temperature (°C) Figure 6. Turn-off Propagation Delay vs. Supply Voltage Figure 7. Turn-off Propagation Delay vs. Temperature 100 140 90 tr High Side 120 80 70 Rise Time (ns) Rise Time (ns) 40 Temperature (°C) Figure 4. Turn-on Propagation Delay vs. Supply Voltage 60 50 40 tr High Side 30 tr Low Side tr Low Side 100 80 60 40 20 20 10 0 0 10 12 14 16 Supply Voltage (V) Figure 8. Rise Time vs. Supply Voltage July 2019 20 18 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 9. Rise Time vs. Temperature 6 TF2106M High Side and Low Side Gate Driver Typical Characteristics, cont’d 50 50 45 40 tf High Side 40 35 tf Low Side 35 Fall Time (ns) Fall Time (ns) 45 30 25 20 30 25 20 15 tf High Side 10 10 tf Low Side 5 5 15 0 0 10 12 14 16 18 20 -40 -20 0 20 200 100 120 100 120 200 180 180 160 IBSq 140 ICCq Quiescent Current (µ µA) Quiescent Current (µ µA) 80 Figure 11. Fall Time vs. Temperature Figure 10. Fall Time vs. Supply Voltage 120 100 80 60 40 20 160 IBSq 140 ICCq 120 100 80 60 40 20 0 10 12 14 16 18 0 20 -40 -20 0 20 Supply Voltage (V) 9 9 7 tdmoff Delay Matching (ns) 10 tdmon 60 80 Figure 13. Quiescent Current vs. Temperature 10 8 40 Temperature (°C) Figure 12. Quiescent Current vs. Supply Voltage Delay Matching (ns) 60 Temperature (°C) Supply Voltage (V) 6 5 4 3 8 tdmon 7 tdmoff 6 5 4 3 2 2 1 1 0 0 10 12 14 16 18 Supply Voltage (V) Figure 14. Delay Matching vs. Supply Voltage July 2019 40 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 15. Delay Matching vs. Temperature 7 TF2106M High Side and Low Side Gate Driver 500 500 450 450 400 IO+ High Side 350 IO+ Low Side Output Source Current (mA) Output Source Current (mA) Typical Characteristics, cont’d 300 250 200 150 100 10 12 14 16 18 IO+ High Side 400 IO+ Low Side 350 300 250 200 150 100 20 -40 -20 0 Supply Voltage (V) 80 100 120 800 750 750 IO- High Side 700 Output Sink Current (mA) Output Sink Current (mA) 60 Figure 17. Output Source Current vs. Temperature 800 IO- Low Side 650 600 550 500 450 400 10 12 14 16 18 IO- High Side IO- Low Side 700 650 600 550 500 450 400 20 -40 -20 0 Figure 18. Output Sink Current vs. Supply Voltage 1.4 1.3 1.3 Logic 1 Input Voltage (V) 1.5 1.4 1.2 1.1 1.0 VIH High Side 0.8 VIH Low Side 40 60 80 100 120 Figure 19. Output Sink Current vs. Temperature 1.5 0.9 20 Temperature (°C) Supply Voltage (V) Logic 1 Input Voltage (V) 40 Temperature (°C) Figure 16. Output Source Current vs. Supply Voltage 0.7 1.2 1.1 1.0 0.9 VIH High Side 0.8 VIH Low Side 0.7 0.6 0.6 0.5 0.5 10 12 14 16 18 20 Supply Voltage (V) Figure 20. Logic 1 Input Voltage vs. Supply Voltage July 2019 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 21. Logic 1 Input Voltage vs. Temperature 8 TF2106M High Side and Low Side Gate Driver Typical Characteristics, cont’d 1.5 1.5 1.4 Logic 0 Input Voltage (V) Logic 0 Input Voltage (V) 1.4 VIL High Side 1.3 VIL Low Side 1.2 1.1 1.0 0.9 0.8 0.7 1.3 1.2 1.1 1.0 0.9 0.8 VIL High Side 0.7 VIL Low Side 0.6 0.6 0.5 0.5 10 12 14 16 18 -40 20 -20 0 60 80 100 120 Figure 23. Logic 0 Input Voltage vs. Temperature 16 16 14 14 12 12 VBS UVLO (V) VCC UVLO (V) Figure 22. Logic 0 Input Voltage vs. Supply Voltage 10 8 6 VCCUV+ 10 8 6 VBSUV+ 4 VCCUV- 2 40 Temperature (°C) Supply Voltage (V) 4 20 VBSUV- 2 0 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure 24. VCC UVLO vs. Temperature Figure 25. VBS UVLO vs. Temperature Offset Supply Leakage Current (µ µA) 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 26. Offset Supply Leakage Current Temperature July 2019 9 TF2106M High Side and Low Side Gate Driver Operation Halfbridge Configuration A common configuration used for the TF2106 M is a half - bridge ( see fig . 28 ). In a half - bridge configuration the source of the high-side MOSFET (QH ) and the drain of the low-side MOSFET (QL) are connected . That line (VS) is both the return for the high side in the gate driver IC as well as the output of the half-bridge . When QH is on and QL is off, VS swings to high voltage , and when QH is off and QL is on , VS swings to GND . Hence the output switches from GND to high voltage at the frequency of HIN and LIN , this line drives a transformer for a power supply, or a coil on a motor. In this half-bridge configuration, high voltage DC is input to the MOSFETs, and converted to a high voltage switching signal to output to load (fig 28). The MOSFETs operate in saturation mode and an important function of the gate driver is to turn on the MOSFET quickly to minimize switching losses from the linear region of the MOSFET (turn on and turn off); the TF2106 has a typical rise/fall time of 100ns/35ns into a 1nF load. Another important function of the gate driver IC in the half-bridge configuration is to convert the logic signals of control (TF2106 operates at logic 3.3V), to a voltage level and current capacity to drive the gate of the MOSFET and IGBT; this requires driving large currents initially to turn on/ turn off the MOSFET quickly. Also the floating well of the high-side allows high voltage operation in the bootstrap operation. VHV DB CHV VCC CD PWM Control VCC VB HIN HO LIN TF2106M COM VS LO CB RGH QH RGL QL R4 Figure 28. TF2106M in a half-bridge configuration Bootstrap Operation The supply for the TF 2106M High Side is provided by the bootstrap capacitor CB (see fig 29). In the half -bridge configuration, VS swings from 0V to VHV depending on the PWM input ot the IC. When VS is 0 V, VBS will go below VCC and V CC will charge CB . When HO goes high , VS swings to VHV , and VBS remains at VCC minus a diode drop (DB) due to the voltage on CB . This is the supply for the high side gate driver and allows the gate driver to function with the floating well (VS ) at the high voltage. When considering the value of the bootstrap capacitor CB , it is important that it is sized to provide enough energy to quickly drive the gate of QH . Values of 1 mF to 10mF are recommended , exact value depending on gate capacitance, and the noise in application. It is key to use a low ESR capacitor that is close to the device. This will best quickly supply charge to the gate of the MOSFET. July 2019 VCC DB HV VB Gate Driver IC High Side CB QH HO RGH VS Figure 29. TF2106M high side in bootstrap operation 10 TF2106M High Side and Low Side Gate Driver For a more detailed description on Gate Resistor Selection and Bootstrap Capacitor Selectrion, see the TF Semiconductor’s Gate Driver Application Note (AN1347). Gate Drive Control The most crucial time in the gate drive is the turn on and turn off of the MOSFET, and performing this function quickly, but with minimal noise and ringing is key. Too fast a rise/fall time can cause unnecessary ringing, and too slow a rise/fall time will increase switching losses in the MOSFET. Increasing turn on and turn off has the effect of limiting ringing and noise due to parasitic inductances, hence with a noisy environment, it may be necessary to increase the gate resistors. For gate resistor value selection the exact value depends on the type of application and desired level of noise and ringing expected. Generally, power supplies switch at a fast speed, and want to squeeze out efficiency of the MOSFETs, so lower values are recommended, for example RGH = 5W - 20W. For motors, the switching speed is generally slower, and the application has more inherent noise, so higher values are recommended, for example RGH = 20W - 100W. An example of just the high side gate driver is shown in figure 30 (any selection of gate driver components should be the same for high side and low side drive); two extra components are seen, RDH and DH. With the careful selection of RGH and RDH , it is possible to selectively control the rise time and fall time of the gate drive. For turn on, all current will go from the IC through RGH and charge the MOSFET gate capacitor, hence increasing or decreasing RGH will increase or decrease rise time in the application. With the addition of DH , the fall time can be separately controlled as the turn off current flows from the MOSFET gate capacitor, through DH and RDH to the driver in the IC to VS. So increasing or decreasing RDH will increase or decrease the fall time. VCC VB TF2106M HO RDH DH QH RGH VS OUT Figure 30. Gate Drive Control July 2019 11 TF2106M High Side and Low Side Gate Driver Application Information Layout Considerations Layout plays a considerable role in noise and ringing in a circuit; unwanted noise coupling, unpredicted glitches and abnormal operation could arise due to poor layout of the associated components. Figure 31 shows a halfbridge schematic with parasitic inductances in the high current path (LP1, LP2, LP3, LP4) which would be caused by inductance in the metal of the trace. Considering fig. 31, the length of the tracks in red should be minimized, and the bootstrap capacitor (CB) and the decoupling capacitor (CD) should be placed as close to the IC as possible. Low ESR ceramic capacitors should be used to minimize inductance. And finally the gate resistors (RGH and RGL) and the sense resistor (RS) should be surface mount devices. These suggestions will reduce the parasitics due to the PCB traces. RGH A layout example is seen in figure 32. Here there are two bootstrap capacitors (CB1 and CB2) and two decoupling capacitors (C1 and C2), and the caps are placed as close as possible to the HVIC. But even if only using one boostrap cap and one decoupling capacitor, it needs to be as close as possible to minimize inductance between the cap and the driver. Generally, for the decoupling capacitor on VCC, at least one low ESR capacitor is recommended with it close to the device as shown in figure 32. Recommended values are 1mF to 10mF. A second smaller decoupling capacitor is sometimes added to provide better high frequency response (for example 0.1mF). CHV HO VB VS VCC CB VCC Minimize area LP1 LP2 CD Keep high voltage and high current line away from logic and analog lines RGL LO COM LP3 RS LP4 Figure 31. Layout Suggestions for TF2106M in a halfbridge July 2019 Figure 32 . Layout example for TF 2106 M (U 1 ) in a halfbridge, notice the bootstrap caps (CB1, CB2), VCC caps ( C1 and C2), and bootstrap diode (DB1) adjacent to the IC. 12 TF2106M High Side and Low Side Gate Driver Application Example 400V US1M VCC VCC 2.2 F 50R HO VDD TF2106M VB To MCU 2.2 F VS HIN LIN R4 M 50R LO COM 400V PMSM 400W Compressor US1M VCC 2.2 F 50R HO VDD TF2106M VB HIN To MCU 2.2 F VS LIN R4 LO COM 50R US1M VCC 2.2 F COM 50R 2.2 F VS LIN R4 July 2019 VDD TF2106M VB HIN To MCU HO 50R LO To MCU RCS 13 TF2106M High Side and Low Side Gate Driver Package Dimensions (SOIC-8 N) Please contact support@tfsemi.com for package availability. July 2019 14 TF2106M Package Dimensions (PDIP-8) July 2019 High Side and Low Side Gate Driver 15 TF2106M High Side and Low Side Gate Driver Revision History Rev. Change Owner Date 1.0 First release, final datasheet Keith Spaulding 3/22/16 1.1 Text edit Keith Spaulding 9/10/17 1.2 Add Note 5 Duke Walton 7/28/19 Important Notice TF Semiconductor Solutions (TFSS) PRODUCTS ARE NEITHER DESIGNED NOR INTENDED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS UNLESS THE SPECIFIC TFSS PRODUCTS ARE SPECIFICALLY DESIGNATED BY TFSS FOR SUCH USE. BUYERS ACKNOWLEDGE AND AGREE THAT ANY SUCH USE OF TFSS PRODUCTS WHICH TFSS HAS NOT DESIGNATED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS IS SOLELY AT THE BUYER’S RISK. TFSS assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using TFSS products. Resale of TFSS products or services with statements different from or beyond the parameters stated by TFSS for that product or service voids all express and any implied warranties for the associated TFSS product or service. TFSS is not responsible or liable for any such statements. ©2019 TFSS. All Rights Reserved. Information and data in this document are owned by TFSS wholly and may not be edited , reproduced, or redistributed in any way without the express written consent from TFSS. For additional information please contact support@tfsemi.com or visit www.tfsemi.com July 2019 16