SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
SOUTHCHIP CONFIDENTIAL
SC8815 High Efficiency, Synchronous, Bi-Directional Buck-Boost
Charger Controller with I2C Interface
1
Description
2
Features
SC8815 is a synchronous buck-boost charger controller
•
Buck-Boost Battery Charger for 1 to 6 Cell Batteries
which can support reverse discharging operation. It can
•
Charging Management including Trickle Charge,
support up to 36V battery voltage, so can be used to
CC Charge, CV Charge and Charge Termination
effectively manage the charging for 1~6 cell Li-ion
•
Buck-Boost Reverse Discharging Mode
batteries no matter adapter voltage is higher, lower or
•
Wide VBAT Range: 2.7 V to 36 V, 40V sustainable
equal to battery voltage. When a system needs to
•
Wide VBUS Range: 2.7 V to 36 V, 40V sustainable
generate an output from the battery, SC8815 can also
•
I2C Programmable Charging Current and Voltage
discharge the cells and delivers desired output up to
•
I2C Programmable Discharging Output Voltage
36V.
•
I2C Programmable Input / Output Current Limit
Through its I2C interface, user can set the charging /
•
I2C Programmable Switching Frequency
discharging mode easily, and program the charging
•
High Efficiency Buck-Boost Conversion
current, charging voltage, reserve output voltage,
•
10-bit ADC resources
current
other
•
Charging Status Indication
parameters flexibly. Besides that, SC8815 integrates
•
Event Detections, including Automatic Adapter
limits,
switching
frequency
and
10-bit ADC, so user can read the VBUS / VBAT voltage
Insert and Automatic Load Insert Detection
and current in real time, simplifying the system design.
•
Power Path Control
SC8815 supports internal current limit, over voltage
•
Under Voltage Protection, Over Voltage Protection,
protection, output short protection and over temperature
Over Current Protection, Short Circuit Protection
protections to ensure safety under different abnormal
and Thermal Shutdown Protection
conditions.
•
QFN-32 Package
The SC8815 is in a 32 pin 4x4 QFN package.
4
3
Device Information
Applications
•
Power Bank with Fast Charge Function
•
USB Power Delivery
•
Type C Hub
•
Industrial Power Supplies
Part Number
Package
Dimension
SC8815QDER
32 pin QFN
4.0mm x 4.0mm x 0.75mm
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
5
SOUTHCHIP CONFIDENTIAL
Typical Application Circuit
OTG = 0, charging
OTG = 1, discharging
AC adapter /
Micro USB
VBAT
VBUS
+
PGND
LD1
SW1
BT1
HD1
SNS1N
SNS1P
USB_A
VCC
VDRV
VBUS
LD2
FB
SW2
BT2
SC8815
HD2
GPO
SNS2P
PGATE
SNS2N
ACIN
VBATS
COMP
AGND
CP
/CE
ADIN
INT
SCL
SDA
VDD
PSTOP
VBAT
INDET
Host
Control
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
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6
SOUTHCHIP CONFIDENTIAL
Terminal Configuration and Functions
24
23
VDRV
VCC
LD2
22
PGND
25
SW2
21
LD1
26
HD2
20
SW1
27
BT2
19
HD1
28
VBAT
/CE
18
BT1
29
SNS2P
PSTOP
17
VBUS
30
6
31
7
32
8
SNS1N
Top View
SNS2N
12
13
14
FB
15
16
VBATS
11
ADIN
10
AGND
SCL
9
INT
ACIN
SDA
INDET
33
PGND
COMP
1
2
3
PGATE/DITHER
GPO
5
CP
4
SNS1P
TERMINAL
I/O
DESCRIPTION
SNS1P
I
Positive input of a current sense amplifier. Connect to one pad of the current sense resistor
(typical 10 mΩ) on the power path to sense the current into or out from VBUS.
2
GPO
O
Open drain output for general purpose. It is controlled by GPO_CTRL bit. User can use this pin to
drive external PMOS with a pull up resistor.
3
CP
O
Driver for external charge pump circuit. (CHARGE PUMP NOT RECOMMENDED. It is
suggested to leave this pin floating, and connect VDRV with VCC. Consult local FAE if
charge pump is needed)
4
PGATE/DITHER
IO
PMOS gate driver controlled by PGATE bit, used to control the external PMOS on the power
path. This pin can be configured through I2C for switching frequency dithering function. Connect
a ceramic capacitor (typical 100nF) from this pin to ground when for frequency dither function.
5
INDET
I
Connect this pin to a USB-A port to detect the load insertion event. When an insertion event is
detected, the IC sets INDET bit and outputs an INT interrupt pulse to inform MCU.
6
ACIN
I
Connect this pin to AC adapter input node or micro-USB port to detect an AC adapter insertion
event. When an insertion event is detected, the IC sets AC_OK bit and outputs an INT interrupt
pulse to inform MCU.
7
/CE
I
NUMBER
NAME
1
Chip enable control. Pull this pin to logic low to enable the IC; pull this pin to logic high to disable
the IC.
This pin is internally pulled low.
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
3
SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
8
PSTOP
I
SOUTHCHIP CONFIDENTIAL
Power stop control. Pull this pin to logic low to enable the power blocks; pull this pin to logic high
to disabled the power blocks, and the IC enters into Standby mode. In Standby mode, only the
AC adapter and load insert detection functions and the I2C circuits keep working.
This pin is internally pulled low.
I2C interface clock. Connect SCL to the logic rail through a pull up resistor (typical 10 kΩ). The IC
works as a slave, and the I2C address is 0x74H.
9
SCL
I
10
SDA
I/O
I2C interface data. Connect SDA to the logic rail through a pull up resistor (typical 10 kΩ).
11
INT
O
An open drain output for interrupt signal. The IC sends a logic low pulse at INT pin to inform the
host if an interrupt event happens.
12
AGND
I/O
Analog ground. Connect PGND and AGND together at the thermal pad under IC.
13
ADIN
I
ADC input pin. Apply an analog signal (≤ 2.048V) to this pin, the internal 10-bit ADC can convert
this analog signal to digital signals, and store the digital values in a register.
14
FB
I
Feedback node for VBUS voltage. Connect a resistor divider from VBUS to FB to set the VBUS
discharging output voltage in external way. The FB reference can also be programmed through
I2C.
15
COMP
I
Connect resistor and capacitor at this pin to compensate the control loop.
16
VBATS
I
Sense node for VBAT voltage. Connect to VBAT rail if internal way is selected for VBAT charging
termination voltage setting; connect a resistor divider at VBATS external way is selected.
17
SNS2N
I
Negative input of a current sense amplifier. Connect to one pad of the current sense resistor
(typical 10 mΩ) on the power path to sense the current into or out from battery.
18
SNS2P
I
Positive input of a current sense amplifier. Connect to the other pad of the current sense resistor
(typical 10 mΩ) on the power path to sense the current into or out from battery.
19
VBAT
I
Power supply to the IC. Connect to the battery positive node. Place a 1 μF capacitor from this pin
to PGND as close to the IC as possible.
20
BT2
I
Connect a 100nF capacitor between BT2 pin and SW2 pin to bootstrap a bias voltage for high
side MOSFET driver.
21
HD2
O
Gate driver output to control the external high side power MOSFET.
22
SW2
I/O
Switching node. Connect to the inductor.
23
LD2
O
Gate driver output to control the external low side power MOSFET.
24
VCC
O
Output of an internal 5V linear regulator. Connect a 1 μF capacitor from VCC pin to PGND as
close to the IC as possible.
25
VDRV
I
Power supply input for internal driver circuits. One way of getting the power supply is to connect
VCC to this pin directly. Another way is to use the CP driver to implement a charge pump
between VCC and VDRV pin. (CHARGE PUMP WAY IS NOT RECOMMENDED. CONSULT
LOCAL FAE IF CHARGE PUMP IS USED)
26
PGND
I/O
Power ground. Connect PGND and AGND together at the PGND thermal pad under IC.
27
LD1
O
Gate driver output to the external low side MOSFET.
28
SW1
I/O
Switching Node. Connect to the inductor.
29
HD1
O
Gate driver output to the external high side MOSFET.
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
4
SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
SOUTHCHIP CONFIDENTIAL
30
BT1
I
Connect a 100nF capacitor between BT1 pin and SW1 pins to bootstrap a bias voltage for high
side MOSFET driver.
31
VBUS
I
Power supply to the IC. Connect to the VBUS rail. Place a 1 μF capacitor from this pin to PGND
as close to the IC as possible.
32
SNS1N
I
Negative input of a current sense amplifier. Connect to one pad of the current sense resistor
(typical 10 mΩ) on the power path to sense the current into or out from VBUS.
33
Thermal Pad
PGND thermal pad. Connect PGND and AGND together at the thermal pad under IC.
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
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SOUTHCHIP SEMICONDUCTOR
7
Specifications
7.1
Absolute Maximum Ratings
SOUTHCHIP CONFIDENTIAL
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
Unit
-0.3
6.5
V
PSTOP
-0.3
6
V
SCL, SDA, INT, ADIN, COMP
-0.3
5
V
FB
-0.3
30
V
VBUS, SNS1N, SNS1P, GPO, PGATE, INDET, ACIN, VBATS, SNS2N,
SNS2P, VBAT, SW2, SW1, /CE
-0.3
40
V
VBUS to SNS1P, SNS1N
-0.3
11
V
VBAT to SNS2P, SNS2N
-0.3
11
V
SNS1P to SNS1N
-10
10
V
SNS2P to SNS2N
-10
10
V
BT1, HD1, BT2, HD2
-0.3
45
V
BT1 to HD1, BT2 to HD2
-0.3
6.5
V
TJ
Operating junction temperature range
-40
150
°C
Tstg
Storage temperature range
-65
150
°C
CP, LD2, VCC, VDRV, LD1
HD1 to SW1, BT1 to SW1, BT2 to SW2, HD2 to SW2
Voltage range at
terminals(2)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to network ground terminal.
7.2
Thermal Information
THERMAL RESISTANCE(1)
QFN-32 (4mmX4mm)
UNIT
θJA
Junction to ambient thermal resistance
35
°C/W
θJC
Junction to case resistance
7
°C/W
(1)
7.3
Measured on JESD51-7, 4-layer PCB.
Handling Ratings
PARAMETER
DEFINITION
(2)
ESD(1)
Human body model (HBM) ESD stress voltage
(3)
Charged device model (CDM) ESD stress voltage
MIN
MAX
UNIT
-2
2
kV
-750
750
V
(1)
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2)
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3)
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
7.4
VBUS
Recommended Operating Conditions
VBUS voltage range
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
MIN
MAX
UNIT
2.7
36
V
6
SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
SOUTHCHIP CONFIDENTIAL
VBAT
VBAT voltage range
2.7
CBUS, CBAT
VBUS Capacitance, VBAT capacitance
30
L
Inductance
2.2
10
µH
RSNS1/2
Current Sensing Resistor
5
10
mΩ
TA
Operating ambient temperature
-40
85
C
TJ
Operating junction temperature
-40
125
C
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
36
V
µF
7
SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
7.5
SOUTHCHIP CONFIDENTIAL
Electrical Characteristics
TJ= 25°C and VBUS = 5V, VBAT = 10.8V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
V
SUPPLY VOLTAGE
VUVLO_VBUS
VUVLO_VBAT
IQ_VBAT
IQ_VBUS
ISB_VBAT
VBUS under-voltage lockout
threshold
Rising edge
2.5
Hysteresis
170
VBAT under-voltage lockout
threshold
Rising edge
2.4
Hysteresis
170
VBUS = 5V
PSTOP = L, non-switching
2.4
4
mA
2.4
4
mA
PSTOP = L, non-switching
25
40
μA
VBUS open
PSTOP = H, AD_START = 0
17
40
μA
VBUS open
PSTOP = H, AD_START = 1
0.65
1.2
mA
Quiescent current into VBAT
Quiescent current into VBUS
Standby current into VBAT
VBUS = 5V
PSTOP =
termination
L,
after
charging
mV
2.6
V
mV
ISB_VBUS
Standby current into VBUS
PSTOP = H, AD_START = 0
12
50
μA
ISD_VBAT
Shutdown current into VBAT
/CE = H, VBUS = open
10
20
μA
PSTOP = L, VBUS = 9V
5.0
5.3
V
PSTOP = L, VBUS = 5V
4.96
5
V
3
V
30
mA
VCC, DIRVER AND POWER SWITCH
VCC
VCC regulation voltage
PSTOP = H,VBAT=3.6V
PSTOP = L
VBUS = 5V, VCC = 4.5V
IVCC_LIM
VCC current limit
17
PSTOP = L
VBUS = 9V, VCC = 4.5V
25
PSTOP = H
VDRV
VDRV regulation voltage
mA
160
1
mA
change pump connected
VBUS = 5V, IDRV = 0mA
5.8
6.2
6.5
V
change pump connected
VBUS = 9V, IDRV = 30mA
5.7
6.1
6.4
V
RHS/LS_PU
High/low side MOS driver pull up
resistor
4
Ω
RHS/LS_PD
High/low side MOS driver pull
down resistor
1
Ω
REFERENCE VOLTAGE IN CHARGING MODE
VBATS_ext
VBATS reference voltage for
external setting
VBAT_SEL = 1
VBATS_int
VBATS accuracy for internal
setting, over VBATS target
VBAT_SEL = 0, CSEL = 00
VCELL_SET=000~111
VTRICKLE_int
Trickle charge threshold voltage
for internal setting
VBAT_SEL = 0, Cell number = N
VCELL_SET = 000~1111,
TRICKLE_SET = 0
2.73*N
VBAT_SEL = 0, Cell number = N
2.31*N
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
1.197
1.203
1.209
V
0.5
%
2.94*N
3.15*N
V
2.52*N
2.73*N
V
-0.5
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SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
SOUTHCHIP CONFIDENTIAL
VCELL_SET = 000~1111,
TRICKLE_SET = 1
VTRICKLE_ext
Trickle charge threshold for
external setting, over VBAT target
VBAT_SEL = 1,
TRICKLE_SET = 0
65
70
75
%
VBAT_SEL = 1,
TRICKLE_SET = 1
55
60
65
%
VEOC
EOC voltage threshold, over VBAT
target
VBAT_SEL = 0/1
97%
98%
99%
VRECH
Recharge threshold voltage, over
VBAT target
VBAT_SEL = 0/1
94.8%
95.8%
96.8%
4.5V target
VINREG_SET = 0x2C,
VINREG_RATIO = 0
4.3
4.5
4.7
V
15V target
VINREG_SET = 0x95,
VINREG_RATIO = 0
14.7
15
15.3
V
4.48V target
VINREG_SET = 0x6F,
VINREG_RATIO = 1
4.4
4.5
4.6
V
10V target
VINREG_SET = 0xF9,
VINREG_RATIO = 1
9.8
10
10.2
V
103%
105.5%
108%
VINREG
VBAT_OVP
VINREG reference voltage
VBAT OVP threshold, over VBAT
target
VBAT_SEL = 0/1
VCLAMP
125
mV
REFERENCE VOLTAGE IN DISCHARGING MODE
VFB
VBUS
FB reference voltage for external
setting
FB_SEL = 1, VBUSREF_E_REF
target from 0.5V to 2.048V
-2%
2%
FB_SEL = 0
VBUS_RATIO = 1 (5x)
VBUS = 3.6 ~10.24V
-2%
2%
FB_SEL = 0
VBUS_RATIO = 0 (12.5x)
VBUS = 9 ~ 24V
-2%
2%
VBUS OVP threshold, rising edge
VBUSREF_I_SET = 1V
VBUSREF_E_SET = 1V
107.3%
Hysteresis
VBUSREF_I_SET = 1V
VBUSREF_E_SET = 1V
VBUS reference voltage accuracy
for internal setting
VBUS_OVP
110%
113%
3%
CURRENT LIMIT
IBUS_LIM
IBUS current limit accuracy
Charging mode, 6A target
IBUS_RATIO = 01 (6x)
IBUS_LIM = 0x7F
-10%
10%
Charging mode, 3A target
IBUS_RATIO = 10 (3x)
IBUS_LIM = 0x7F
-10%
10%
Discharging mode, 6A target
IBUS_RATIO = 01 (6x)
IBUS_LIM = 0x7F
-10%
10%
Discharging mode, 3A target
IBUS_RATIO = 10 (3x)
IBUS_LIM = 0x7F
-10%
10%
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SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
IBAT_LIM
ITRICKLE
IEOC
IBAT current limit accuracy
SOUTHCHIP CONFIDENTIAL
Charging mode, 6A target
IBAT_RATIO = 0 (6x)
IBAT_LIM = 0xFF
-10%
10%
Charging mode, 12A target
IBAT_RATIO = 1 (12x)
IBAT_LIM = 0xFF
-10%
10%
Discharging mode, 6A target
IBAT_RATIO = 0 (6x)
IBAT_LIM = 0xFF
-15%
15%
Discharging mode, 12A target
IBAT_RATIO = 1 (12x)
IBAT_LIM = 0xFF
-15%
15%
Trickle charge current, over
IBAT_LIM setting
10%
Trickle charge current, over
IBUS_LIM setting
22%
EOC current threshold, over
IBUS_LIM / IBAT_LIM setting
EOC_SET= 0
4%
EOC_SET= 1
10%
ERROR AMPLIFIER
GmEA
Error amplifier gm
ROUT
Error amplifier output resistance (1)
ISINK_COMP
COMP sink current
ISRC_COMP
COMP source current
IBIAS_FB
FB pin input bias current
0.12
0.15
0.18
mS
20
MΩ
LOOP_SET = 0/1
25
μA
LOOP_SET = 0
18
μA
LOOP_SET = 1
32
μA
FB_SEL = 1
FB in regulation
50
nA
SWITCHING
fSW
Switching frequency
FREQ_SET = 00 (150kHz)
140
155
170
kHz
FREQ_SET = 01 (300kHz)
270
305
330
kHz
FREQ_SET = 11 (450kHz)
400
450
500
kHz
POWER PATH MANAGEMENT
RPU_PGATE
PGATE pin pull up resistor
EN_PGATE = 0
20
kΩ
RPD_PGATE
PGATE pin pull down resistor
EN_PGATE = 1
6
kΩ
VCLAMP
Clamp voltage from VBUS to
PGATE pin
EN_PGATE = 1
RRD_GPO
GPO pin pull down resistor
GPO_CTRL = 1
6.9
7.35
7.7
6
V
kΩ
DETECTION
VAC_DET
AC detection threshold
VSHORT
Short circuit detection threshold
2.9
3.1
3.4
V
0.95
1
1.05
V
0.75
1
1.25
MΩ
0.4
V
I2C AND LOGIC CONTROL
RPD
PSTOP pin internal pull down
resistor
VIL
PSTOP, SCL, SDA input low
voltage
VIH
PSTOP, SCL, SDA input high
voltage
ISINK_INT
INT pin sink current
1.2
VINT = 0.4V
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co., Ltd.
0.3
V
0.375
0.45
mA
10
SC8815 DATASHEET
SOUTHCHIP SEMICONDUCTOR
ISINK_SCL/SDA
SCL/SDA pin sink current
tPULSE
Interrupt pulse width (logic low)
SOUTHCHIP CONFIDENTIAL
VSCL/SDA = 0.4V
mA
100
0.6
1
1.5
ms
SOFTSTART
tdeglitch
Deglitch time for charging
PSTOP = L, OTG_SET = 0
VBUS = 5V, from PSTOP low to IC
starting charging
220
ms
tSS
Internal soft-start time
VBUS from 0V to 5V in discharging
mode
VBUS_Ratio = 1 (5x)
12
ms
165
°C
15
°C
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature (1)
Thermal shutdown hysteresis
(1)
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SOUTHCHIP SEMICONDUCTOR
8
its current limit value first. For example, if IBUS current limit
is set to 3A, IBAT limit is set to 10A, and when IBUS reaches
3A, IBAT is only 6A, which is much lower than IBAT limit 10A,
then the IC limits the IBUS at 3A.
Detailed Description
8.1
SOUTHCHIP CONFIDENTIAL
Charging Mode
Charging mode and discharging mode is selected by
EN_OTG bit.
When EN_OTG bit is 0, the IC works in charging mode. The
current flows from VBUS to VBAT to charge the battery cells.
When in charging mode, the IC charges the battery cells
according to below typical charging profile. When battery
voltage is lower than trickle charge threshold, the IC charges
the cells with small charging current; when cell voltage is
higher than the threshold, the IC enters into Constant Current
charging phase, and charges the cells with constant current
set by IBUS limit or IBAT limit. When the cell voltage reaches
the termination voltage target, the IC enters into Constant
Voltage charge phase, and charges the cells with gradually
decreased current until the current is lower than termination
current threshold. Once termination voltage and termination
current conditions are satisfied, the IC enters into End of
Charge phase. In this phase the IC can either terminate the
charging or keep charging the cells.
Termination voltage
Recharge-threshold
It is not allowed to set any of the current limits to 0A. Keep
the minimum current limit above 0.3A.
8.1.3
CV Charge (Constant Voltage Charge)
The battery target voltage can be set internally, by CSEL bits
and VCELL_SET bits. The CSEL bits set the battery cell
numbers connected in series, and VCELL_SET bits set the
battery voltage per cell. For example, if the battery cells are
in xp2s connection (several cells are connected in parallel,
and two cells in series) and the cell voltage is 4.3V, the user
should set CSEL to 01 (2S), and set VCELL_SET bits to 011
(4.3V).
When the battery charging voltage is set internally, the user
should connect VBATS pin to VBAT terminal to sense the
battery voltage, and the VBAT_SEL bit should be set to 0.
If VBAT_SEL is set to 1, it means the battery voltage is set
externally. Under this condition, the user should use resistor
divider at VBATS pin to set the target voltage as below.
VCELL_SET and CSEL bits don’t work. The reference of
VBATS is 1.2V.
CC (constant
current) charge
VBAT = VBATS_REF× (1+
RUP
)
RDOWN
Trickle charge
threshold
EOC indication
VBAT
Trickle charge current
+
Termination current
Trickle charge
CC (constant
current) charge
CV (constant
voltage) charge
End of
recharge
charge
VBATS
A. VBAT_SEL = 0
Figure 1 Typical Charging Profile
8.1.1
Trickle Charge
The trickle charge voltage threshold can be set to 60% or 70%
of 4.2V/cell by TRICKLE_SET bit. When in trickle charge
phase, the charging current is reduced to a small value for
the good of battery cells. If ICHAR_SEL bit is 0, the IBUS is
reduced to 22% of the IBUS current limit set value; if
ICHAR_SEL bit is 1, the IBAT is reduced to 10% of IBAT
current limit set value.
VBAT
Rup
+
VBATS
Rdown
B. VBAT_SEL = 1
If trickle charging phase is not needed, the user can set
DIS_TRICKLE bit to 1 to disable it.
8.1.2
CC Charge (Constant Current Charge)
When cell voltage is higher than the trickle threshold, the IC
charges the battery cells with constant current set by IBUS
limit or IBAT limit, which are set respectively through
IBUS_LIM_SET and IBAT_LIM_SET registers. The current
limit value can be changed dynamically, and is also related to
the current sense resistor and ratio bits. Please see Register
Map section for details.
In charging mode, the IC regulates the current which reaches
Figure 2 Battery voltage setting
When the battery cell voltage reaches 98% of the cell target
voltage, the IC enters into CV charge phase. In this phase,
the VBAT voltage is regulated at target value, and the
charging current reduces gradually.
8.1.4
EOC (End of Charge)
When both of below voltage condition and current condition
for EOC detection are satisfied, the IC enters into EOC
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phase, and informs the MCU through EOC interrupt bit.
1.
2.
the cell voltage is higher than 98% of set value
the IBUS or IBAT current (decided by ICHAR_SEL bit) is
lower than 1/10 or 1/25 (decided by EOC_SET bit) of its
current limit value
SOUTHCHIP CONFIDENTIAL
changed dynamically, and the recommended VBUS voltage
range is from 3V to 36V. When VBUS is lower than 10.24V, it
is suggested to set the VBUS_RATIO to 5x, and so the
minimum changing step is 10mV/step; when VBUS is higher
than 10.24V, VBUS_RATIO should be set to 12.5x, and the
minimum changing step is 25mV/step.
In EOC phase, the IC can terminate the charging process or
keep charging the battery cells, which can be set by
DIS_TERM bit. If IC keeps charging, it regulates the battery
cell voltage at set value.
If FB_SEL is set to 1, the VBUS voltage target is set
externally, that is, by the resistor divider connected at FB pin,
and can be calculated as below.
8.1.5
Even if VBUS is set externally, the user can still change the
VBUS voltage dynamically by changing the reference voltage
VBUSREF_E
through
VBUSREF_E_SET
and
VBUSREF_E_SET2 registers. The default VBUSREF_E is
1V, and recommended VBUSREF_E voltage range is from
0.7V to 2.048V.
Recharge
If the IC terminates the charging process after EOC is
detected, the battery voltage may drop slowly due to leakage
or operation current from battery cells. Once the VBAT
voltage drops below 95% of the set voltage, the EOC bit is
cleared, and the IC enters into CC charge phase and
recharges the battery.
8.1.6
Self-adaptive Charging Current (VINREG)
The IC features dynamic power management. The allowed
minimum VBUS operation voltage is VINREG threshold,
which can be set by VINREG_SET register and
VINREG_RATIO bit dynamically. During charging, if the
IBUS charging current is higher than adapter’s current
capability, the adapter will be overloaded and the VBUS
voltage is pulled low. Once the IC detects the VBUS voltage
drops at VINREG threshold, it reduces the charging current
automatically and regulates the VBUS voltage at VINREG
threshold.
8.1.7
Battery Impedance Compensation
The IC provides the function of battery impedance
compensation. User can set the impedance through IRCOMP
bits, then the VBAT target voltage in CV phase is
compensated as
VBAT_cmp = VBAT_set + min(IBAT∙IRCOMP, VCLAMP)
Where,
VBAT_cmp is the compensated battery voltage target;
VBAT_set is the originally set battery termination target; IBAT
is the charging current at battery side; IRCOMP is the
resistance compensation value set by IRCOMP bits;
VCLAMP is the allowed maximum compensation value, fixed
at 125mV.
User should carefully evaluate the real battery impedance. If the
value set by IRCOMP bits is higher than the real value, it will cause
over charge.
8.2
Discharging Mode
When EN_OTG bit is set to1, the IC enters into discharging
mode. In discharging mode, the battery (VBAT) is discharged
and the current flows from VBAT to VBUS.
If FB_SEL is set to 0, the VBUS output voltage is set
internally, through VBUSREF_I_SET and VBUSREF_I_SET2
registers and the VBUS_RATIO bit. The VBUS can be
VBUS = VBUSREF_E x (1+
RUP
)
RDOWM
Please see Register Map section for details.
The IBUS current limit and IBAT current limit are still
functional in discharging mode and can be changed
dynamically.
It is not allowed to set any of the current limits to 0A. Keep
the minimum current limit above 0.3A.
8.2.1
Soft Start
The IC integrates soft-start control to generate VBUS voltage
in discharging mode. When VBUS is lower than VSHORT (typ.
1V), both IBUS and IBAT current limits are fold back to 1/10
of the setting value. Meanwhile, the IC ramps up the internal
reference voltage gradually (~10ms) to avoid inrush current.
If there is a load at VBUS at the beginning of the startup, the
IC may fail to boost the VBUS voltage beyond VSHORT due to
the 1/10 current limits for both IBUS and IBAT. If startup with
loading is required, user shall set the DIS_ShortFoldBack bit
to 1 to disable the current limit fold back function. After
startup, the user can set DIS_ShortFoldBack bit back to 0, so
to enable this function for short circuit protection. See VBUS
Short Protection section for details.
8.2.2
Slew Rate Setting
When the VBUS voltage is changed dynamically through
reference
voltage
(VBUSREF_I_SET
and
VBUSREF_I_SET2 registers or VBUSREF_E_SET and
VBUSREF_E_SET2 registers), the reference voltage change
rate can be controlled through SLEW_SET bits. For example,
the VBUS is set in internal way with 5x ratio, and the
VBUSREF_I = 1V at first (VBUS = 5V), then the user sets the
VBUSREF_I voltage to 1.6V to get 8V output. If the slew rate
is 2mV/ μs, the VBUS voltage will increase to 8V in 600mV /
2mV/μs = 300μs.
8.2.3
PFM Operation
The IC supports PFM operation in discharging mode by
setting EN_PFM bit to 1. In PWM mode, the IC always works
with constant switching frequency for the whole load range.
This helps achieve the best output voltage performance, but
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the efficiency is low at light load condition because of the
high switching loss.
In PFM mode, the IC still works with constant switching
frequency under heavy load condition, but under light load
condition, the IC automatically changes to pulse frequency
modulation operation to reduce the switching loss. The
efficiency can be improved under light load condition while
output voltage ripple will be a little larger compared with
PWM operation. Below figure shows the output voltage
behavior of PFM mode.
SOUTHCHIP CONFIDENTIAL
8.5
Phone Insert Detection
If connecting INDET pin to USB-A port as shown in Typical
Application Circuit, the IC can detect the phone detection.
Once the IC detects a phone is inserted, it sets the INDET
interrupt bit to inform MCU. The INDET bit is cleared after it
is read by MCU.
8.6
Adapter Attachment / Detachment
Detection
If connecting ACIN pin to Micro-USB port as shown in Typical
Application Circuit, the IC can detect the attachment /
detachment of the adapter.
PFM operation at light load
PFM VOUT
Vout
Normal VOUT
Change to PWM operation at heavy load
Figure 3 PFM mode illustration
8.3
ADC for Voltage and Current Monitor
The IC integrates a 10-bit ADC, so the IC can monitor the
VBUS/VBAT voltages and IBUS/IBAT current no matter in
charging mode or discharging mode. Besides these, the IC
provides an analog input: ADIN pin for 10-bit ADC sampling.
The maximum voltage the ADC can sample at ADIN pin is
2.048V, and the sampling resolution is 2mV/step. The ADC
function is enabled after AD_START bit is set to 1. When
ADC is enabled in standby mode, the IC will 0.5mA~1mA
operation current. Please see Register Map section for
details.
8.4
Power Path Management
The IC offers power path management function at PGATE
and GPO pins. The PGATE pin can be used to drive PMOS
connected at VBUS. The PGATE pin is connected to a 6 kΩ
pull down resistor internally when EN_PGATE is set to 1, and
the maximum voltage between VBUS and PGATE is
clamped at 7.35V; when EN_PGATE is set to 0, PGATE pin
is connected to VBUS rail through a 20 kΩ pull up resistor
internally
The GPO pin is an open drain output, so external pull up
resistor is needed. When GPO_CTRL bit is set to 0, GPO
outputs high impedance; when GPO_CTRL is set to1, GPO
is pulled down internally and the pull down resistance is 6 kΩ.
User can use PGATE pin and GPO pin to control the
isolation MOSFETs between adapter input and USB output
as shown in Typical Application Circuit. However, the MCU or
system controller controls the bits through I2C interface,
which takes time for communication, so the PMOS may not
be turned on/off very quickly. In the application where the
isolation PMOS needs to be controlled very fast, it is
suggested to use the I/O pins of MCU to control the PMOS
on/off directly.
Once the ACIN pin voltage is higher than 3V, which means
the adapter is inserted, the IC sets the AC_OK interrupt bit to
inform MCU about the attachment. If the ACIN pin voltage is
lower than 3V, which means the adapter is removed, the IC
clears AC_OK bit to inform the MCU about the detachment.
8.7
Switching and Frequency Dithering
The IC switches in fixed frequency which can be adjusted
through FREQ_SET bits. The switching dead time can also
be set through DT_SET pins. Please see Register Map
section for details.
The IC also offers frequency dithering function. This function
can be enabled by setting EN_DITHER bit to 1. When the
function is enabled, the switching frequency is not fixed, but
varies within +/- 5% range. For example, if the switching
frequency is set to 300kHz (FREQ_SET = 01), the frequency
will change from 285kHz to 315kHz gradually and then back
to 285kHz back and forth. The time it varies from the lowest
to the highest frequency or from highest to lowest frequency
can be controlled by a capacitor connected at
PGATE/DITHER pin as below equation shows. For example,
if 100nF capacitor is connected, the time is 1.2 ms.
T_dither =
120 mV × C
10 μA
When EN_DITHER is set to 1, the PGATE driver function is
disabled, and the PGATE/DITHER pin only operates for
dithering function.
8.8
VCC Regulator and Driver Supply
The IC integrates a regulator which is powered by VBUS
voltage and generates a 5V voltage at VCC pin with typically
25 mA driving capability.
When in Standby mode, the VCC voltage is not regulated
and has very limited current capability. It is not suggested to
use VCC in Standby mode.
The internal driving circuit is powered from VDRV pin, and
user should provide a supply at VDRV pin to power the circuit.
The user can connect VCC to VDRV directly, or connect an
external power supply to VDRV. Besides the two ways, the
IC offers a charge pump driver at CP pin, which can pump
the VCC voltage to power VDRV pin. With charge pump
circuit, the IC can regulate the VDRV voltage at 6V.
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Charge pump is not recommended for VDRV. Consult local FAE
if charge pump is used.
8.11 Protection
VCC = 5V
8.11.1
VBUS Over Voltage Protection
User can enabled / disable VBUS over voltage protection in
discharging mode by DIS_OVP bit. When OVP is enabled,
the IC stops switching when VBUS is higher than the target
voltage by 10%.
VCC
CP
VDRV
8.11.2
The IC implements VBAT over voltage protection in both
charging mode and discharging mode. Once the VBAT
voltage is higher than target voltage by 10%, the IC stops
switching.
A. connect VC to VDRV directly
(HIGHLY RECOMMENDED)
VDRV = 6V
VCC = 5V
8.11.3
VCC
VBAT Over Voltage Protection
CP
In discharging mode, if the VBUS voltage is detected lower
than VSHORT (typ. 1V), the IC sets the VBUS_SHORT
interrupt bit to inform the MCU. In the same time, it reduces
IBUS limits to 22% of the set values and IBAT limit to 10% of
the set value at the same time to protect the IC. If
DIS_ShortFoldBack bit is set to 1, the current limits will not
be reduced.
VDRV
B. Use charge pump to power VDRV
(NOT RECOMMEND)
External supply
(=300mA
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Table 7 0x06H IBAT_LIM_SET Register
Bit
Mode
7-0
R/W
Bit Name
IBAT_LIM_SE
T
Default value
@POR
1111 1111
Description
Notes
Set IBAT current limit, which is valid for both charging and discharging
modes.
IBAT_LIM (A) =
IBAT_LIM_SET+1
256
× IBAT_RATIO ×
10 mΩ
RS2
IBAT_LIM_S
ET must
be >=300mA
RS2 is the current sense resistor at VBAT side.
IBAT_LIM_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
…
1111 1111: 255 (default)
E.g., if RS2 = 10 mΩ, the default IBAT current limit is
(255+1)/256 x 12 x 10 mΩ / 10 mΩ = 12 A
Table 8 0x07H VINREG_SET Register
Bit
Mode
7-0
R/W
Bit Name
VINREG_SET
Default value
@POR
0010 1100
Description
Notes
Set VINREG reference voltage for charging mode.
VINREG = （VINREG_SET+1) × VINREG_RATIO (mV)
VINREG_SET range: 0 ~ 255
0000 0000: 0
0000 0001: 1
…
0010 1100: 44 (default)
…
1111 1111: 255
If VINREG_RATIO = 1 (40x), the default VINREG voltage is 1.8V, and
the maximum VINREG voltage which can be set is 10.24V;
If VINREG_RATIO = 0 (100x), the default VINREG voltage is 4.5V,
and the maximum VINREG voltage which can be set is 25.6V.
Table 9 0x08H RATIO Register
Bit
Mode
Bit Name
Default value
@POR
Description
7-6
R/W
Reserved
00
Internal use. Don’t overwrite this bit.
5
R/W
Reserved
1
Internal use. Don’t overwrite this bit.
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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4
R/W
IBAT_RATIO
1
SOUTHCHIP CONFIDENTIAL
IBAT_LIM setting ratio
0: 6x
1: 12x (default)
3-2
R/W
IBUS_RATIO
10
IBUS_LIM setting ratio
00: not allowed
01: 6x
Set this bit
during
PSTOP pin
is high
Set this bit
during
PSTOP pin
is high
10: 3x (default)
11: not allowed
1
R/W
VBAT_MON_
RATIO
0
Ratio setting for VBAT voltage monitor
0: 12.5x (default)
1: 5x
Set this bit
during
PSTOP pin
is high
The battery voltage is monitored through ADC and can be calculated
as below:
VBAT = (4 x VBAT_FB_VALUE + VBAT_FB_VALUE2 + 1) x
VBAT_MON_RATIO x 2 mV
VBAT_FB_VALUE and VBAT_FB_VALUE2 are ADC register values.
For 1S and 2S battery applications (VBAT < 9V), set this bit to 1.
0
R/W
VBUS_RATIO
0
Set the ratio for VBUS voltage setting and VBUS voltage monitor.
0: 12.5x (default)
1: 5x
Set this bit
during
PSTOP pin
is high
Table 10 0x09H CTRL0_SET Register
Bit
Mode
Bit Name
Default value
@POR
7
R/W
EN_OTG
0
Description
Notes
Enable OTG operation
0: set the charger to work in charging mode (default)
1: set the charger to work in discharging mode
6
R/W
Reserved
0
Internal use. Don’t overwrite this bit.
5
R/W
Reserved
0
Internal use. Don’t overwrite this bit.
4
R/W
VINREG_RAT
IO
0
VINREG setting ratio
0: 100x (default)
1: 40x
Set this bit to 1 when VBUS < 12V.
3-2
R/W
FREQ_SET
01
Switching frequency setting
00: 150kHz
01: 300kHz (default)
Set this bit
during
PSTOP pin
is high
10: 300kHz
11: 450kHz
1-0
R/W
DT_SET
00
Switching dead time setting
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Set this bit
during
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00: 20ns (default)
PSTOP pin
is high
01: 40ns
10: 60ns
11: 80ns
Table 11 0x0AH CTRL1_SET Register
Bit
Mode
7
R/W
Symbol
Default value
@POR
ICHAR_SEL
0
Description
Charging current selection
0: IBUS as charging current, the trickle charging current and
termination current will be based on IBUS (default)
Notes
Set this bit
during
PSTOP pin
is high
1: IBAT as charging current, the trickle charging current and
termination current will be based on IBAT
6
R/W
DIS_TRICKLE
0
Trickle charge control
0: enable trickle charge phase (default)
1: disable trickle charge phase
5
R/W
DIS_TERM
0
Charging termination control
0: enable auto-termination (default)
1: disable auto-termination
4
R/W
FB_SEL
0
VBUS voltage setting control, only for discharging mode
0: internal VBUS setting, VBUS output voltage is set by
VBUS_RATIO bit and VBUSREF_I_SET bits (default)
Set this bit
during
PSTOP pin
is high
Set this bit
during
PSTOP pin
is high
Set this bit
during
PSTOP pin
is high
1: external VBUS setting, VBUS output voltage is set by resistor
divider at FB pin
3
R/W
TRICKLE_SET
0
Trickle charge phase threshold setting
0: 70% of VBAT voltage setting (default)
1: 60% of VBAT voltage setting
2
R/W
DIS_OVP
0
Set this bit
during
PSTOP pin
is high
OVP protection setting for discharging mode
0: enable OVP protection (default)
1: disable OVP protection
1
R/W
Reserved
0
Internal use. Don’t overwrite this bit.
0
R/W
Reserved
1
Internal use. Don’t overwrite this bit.
Table 12 0x0BH CTRL2_SET Register
Bit
Mode
Symbol
Default value
@POR
7-4
R/W
Reserved
0000
3
R/W
FACTORY
0
Description
Internal use. Don’t overwrite this bit.
Factory setting bit. MCU shall write this bit to 1 after power up.
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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2
R/W
EN_DITHER
0
SOUTHCHIP CONFIDENTIAL
Enable switching frequency dithering function at PGATE pin:
0: disable frequency dithering function, PGATE pin used as PMOS
gate control (default)
Set this bit
during
PSTOP pin
is high
1: enable frequency dithering function, PGATE pin used to set the
frequency dithering
1-0
R/W
SLEW_SET
01
Slew rate setting for VBUS dynamic change in discharging mode
00: 1mV/μs
01: 2mV/μs (default)
Set this bit
during
PSTOP pin
is high
10: 4mV/μs
11: 8mV/μs
Table 13 0x0CH CTRL3_SET Register
Bit
Mode
7
R/W
Symbol
EN_PGATE
Default value
@POR
0
Description
Notes
PGATE control
0: PGATE outputs logic high to turn off PMOS (default)
1: PGATE outputs logic low to turn on PMOS
6
R/W
GPO_CTRL
0
GPO output control
0: Open drain output (default)
1: Logic low output
5
R/W
AD_START
0
ADC control
0: stop ADC conversion (default)
1: start ADC conversion, MCU can read the voltage/current values
from ADC registers
4
R/W
ILIM_BW_SEL
0
ILIM loop bandwidth setting:
0: 5kHz (default)
1: 1.25kHz
3
R/W
LOOP_SET
0
Loop response control
0: Normal loop response (default)
1: Improve the loop response
2
R/W
DIS_ShortFold
Back
0
Set this bit
during
PSTOP pin
is high
Set this bit
during
PSTOP pin
is high
IBUS and IBAT current foldback control for VBUS short circuit
condition, only valid in discharging mode
0: IBUS and IBAT current limit value are fold-back to 22% and 10% of
setting value respectively (default)
1: disable fold-back.
1
R/W
EOC_SET
1
Current threshold setting for End Of Charging (EOC) detection
0: 1/25 of charging current
1: 1/10 of charging current (default)
0
R/W
EN_PFM
0
PFM control under light load condition, only for discharging mode
0: disable PFM mode (PWM mode enabled) (default)
1: enable PFM mode
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Set this bit
during
PSTOP pin
is high
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Table 14 0x0DH VBUS_FB_VALUE Register
Bit
Mode
7-0
R
Symbol
VBUS_FB_VA
LUE
Default value
@POR
0000 0000
Description
Notes
The highest 8-bit of the ADC reading of VBUS voltage (total 10-bit).
VBUS voltage is calculated as
VBUS = (4 x VBUS_FB_VALUE + VBUS_FB_VALUE2 + 1) x
VBUS_RATIO x 2 mV
VBUS_FB_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
Table 15 0x0EH VBUS_FB_VALUE_2 Register
Bit
Mode
7-6
R
Symbol
VBUS_FB_VA
LUE2
Default value
@POR
00
Description
Notes
The lowest 2-bit of the ADC reading of VBUS voltage (total 10-bit).
VBUS voltage is calculated as VBUS voltage is calculated as
VBUS = (4 x VBUS_FB_VALUE + VBUS_FB_VALUE2 + 1) x
VBUS_RATIO x 2 mV
VBUS_FB_VALUE2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
5-0
Reserved
00 0000
Table 16 0x0FH VBAT_FB_VALUE Register
Bit
Mode
7-0
R
Symbol
VBAT_FB_VA
LUE
Default value
@POR
0000 0000
Description
The highest 8-bit of the ADC reading of VBAT voltage (total 10-bit).
VBAT voltage is calculated as
VBAT = (4 x VBAT_FB_VALUE + VBAT_FB_VALUE2 + 1) x
VBAT_MON_RATIO x 2 mV
VBAT_FB_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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0000 0010: 2
….
1111 1111: 255
Table 17 0x10H VBAT_FB_VALUE_2 Register
Bit
Mode
7-6
R
Symbol
VBAT_FB_VA
LUE_2
Default value
@POR
00
Description
Notes
The lowest 2-bit of the ADC reading of VBAT voltage (total 10-bit).
VBAT voltage is calculated as
VBAT = (4 x VBAT_FB_VALUE + VBAT_FB_VALUE2 + 1) x
VBAT_MON_RATIO x 2 mV
VBAT_FB_VALUE_2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
5-0
Reserved
00 0000
Table 18 0x11H IBUS_VALUE Register
Bit
Mode
7-0
R
Symbol
IBUS_VALUE
Default value
@POR
0000 0000
Description
Notes
The highest 8-bit of the ADC reading of IBUS current (total 10-bit).
IBUS current is calculated as
IBUS (A) =
(4 x IBUS_VALUE + IBUS_VALUE2 + 1)×2
10 mΩ
× IBUS_RATIO ×
1200
RS1
IBUS_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
Table 19 0x12H IBUS_VALUE_2 Register
Bit
Mode
7-6
R
Symbol
IBUS_VALUE
2
Default value
@POR
00
Description
The lowest 2-bit of the ADC reading of IBUS current (total 10-bit).
IBUS current is calculated as
IBUS (A) =
(4 x IBUS_VALUE + IBUS_VALUE2 + 1)×2
10 mΩ
× IBUS_RATIO ×
1200
RS1
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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IBUS_VALUE2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
5-0
Reserved
00 0000
Table 20 0x13H IBAT_VALUE Register
Bit
Mode
7-0
R
Symbol
IBAT_VALUE
Default value
@POR
0000 0000
Description
Notes
The highest 8-bit of the ADC reading of IBAT current (total 10-bit).
IBAT current is calculated as
IBAT (A) =
(4 x IBAT_VALUE + IBAT_VALUE2 + 1)×2
10 mΩ
× IBAT_RATIO ×
1200
RS2
IBAT_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
Table 21 0x14H IBAT_VALUE_2 Register
Bit
Mode
7-6
R
Symbol
IBAT_VALUE
2
Default value
@POR
00
Description
Notes
The lowest 2-bit of the ADC reading of IBAT current (total 10-bit).
IBAT current is calculated as
IBAT (A) =
(4 x IBAT_VALUE + IBAT_VALUE2 + 1)×2
10 mΩ
× IBAT_RATIO ×
1200
RS2
IBAT_VALUE2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
5-0
Reserved
00 0000
Table 22 0x15H ADIN_VALUE Register
Bit
Mode
Symbol
Default value
@POR
Description
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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7-0
R
ADIN_VALUE
0000 0000
SOUTHCHIP CONFIDENTIAL
The highest 8-bit of the ADC reading of ADIN voltage (total 10-bit).
ADIN voltage is calculated as
VADIN = (4 x ADIN_VALUE + ADIN_VALUE2 + 1) x 2 mV
ADIN_VALUE range: 0 ~ 255
0000 0000: 0
0000 0001: 1
0000 0010: 2
….
1111 1111: 255
Table 23 0x16H ADIN_VALUE_2 Register
Bit
Mode
7-6
R
Symbol
ADIN_VALUE
2
Default value
@POR
00
Description
Notes
The lowest 2-bit of the ADC reading of ADIN voltage (total 10-bit).
ADIN voltage is calculated as
VADIN = (4 x ADIN_VALUE + ADIN_VALUE2 + 1) x 2 mV
ADIN_VALUE_2 range: 0 ~ 3
00: 0
01: 1
10: 2
11: 3
5-0
Reserved
00 0000
Table 24 0x17H STATUS Register
Bit
Mode
Symbol
Default value
@POR
Description
7
R
Reserved
0
Reserved
6
R
AC_OK
0
1: AC adapter is inserted
5
R
INDET
0
1: USB-A load insert is detected at INDET pin
4
R
Reserved
0
Reserved
3
R
VBUS_SHORT
0
1: VBUS short circuit fault happens in discharging mode
2
R
OTP
0
1: OTP fault happens
1
R
EOC
0
1: EOC conditions are satisfied
0
R
Reserved
0
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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Table 25 0x19H MASK Register
Bit
Mode
Symbol
Default value
@POR
Description
7
R/W
Reserved
1
Internal use. Don’t overwrite this bit.
6
R/W
AC_OK_Mask
0
1: Interrupt is disabled
5
R/W
INDET_Mask
0
1: Interrupt is disabled
4
R/W
Reserved
0
Internal use. Don’t overwrite this bit.
3
R/W
VBUS_SHORT_
Mask
0
1: Interrupt is disabled
2
R/W
OTP_Mask
0
1: Interrupt is disabled
1
R/W
EOC_Mask
0
1: Interrupt is disabled
0
R/W
Reserved
0
Internal use. Write this bit to 1 after power up.
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
Notes
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SOUTHCHIP SEMICONDUCTOR
MECHANICAL DATA
QFN32L(0404x0.75-0.40)
Copyright © 2017, Southchip Semiconductor Technology (Shanghai) Co.,Ltd.
SOUTHCHIP CONFIDENTIAL
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