FT800 Embedded Video Engine Datasheet
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Bridgetek Pte Ltd
FT800
(Embedded Video Engine)
The FT800 is an easy to use graphic controller
targeted for embedded applications to generate
high-quality Human Machine Interfaces (HMIs). It
has the following features:
Support for LCD display in WQVGA (480x272)
and QVGA (320x240) formats with data
enable
(DE)
support
mode
and
VSYNC/HSYNC mode
FT800 functionality includes graphic controller,
audio
processing,
and
resistive
touch
controller.
The FT800 calculates for 8-bit colour despite
only providing pins for 6-bit (RGB-6,6,6); this
improves the half tone appearance
Embedded Video Engine (EVE) with widget
support can offload the system MPU and
provide a variety of graphic features
Display enable control output to LCD panel
Mono audio channel output with PWM output
64 voice polyphonic sound synthesizer
Audio wave playback for mono 8-bit linear
PCM, 4-bit ADPCM and µ-Law coding format at
sampling frequency from 8 kHz to 48 kHz.
Built-in digital filter reduces the system design
complexity of external filtering
PWM output for backlight dimming control for
LED
Low
power
consumption
for
portable
application, 24mA active (typical) and 10-25
uA sleep (typical)
No frame buffer RAM required
Built-in graphics operations allow users with
little expertise to create high-quality display
Integrated with 4-wire touch-screen controller
incorporating median filtering and touch force
sensing. Hardware engine can recognize touch
tags and track touch movement. It provides
notification for up to 255 touch tags.
Standard serial interface to host MPU/MCU
with SPI up to 30MHz or I²C clocking up to
3.4MHz
Programmable interrupt controller provides
interrupts to host MPU/MCU
Built-in 12MHz crystal oscillator with PLL
providing 48MHz or 36MHz system clock
Video RGB parallel output (default RGB data
width of 6-6-6)
with 2 bit dithering;
configurable to support resolution up to
512x512 and LCD R/G/B data width of 1 to 6
Advanced object oriented architecture enables
low cost MPU/MCU as system host using I2C
and SPI interfaces
Power mode control allows chip to be put in
power down, sleep and standby states
Supports host interface I/O voltage from 1.8V
to 3.3V
Internal voltage regulator supplies 1.2V to the
digital core
-40°C
to
85°C
temperature range
Available in a compact Pb-free, VQFN-48,
7mm X 7mm X 0.9mm package, RoHS
compliant
Programmable timing to adjust HSYNC and
VSYNC
timing,
enabling
interface
to
numerous displays
extended
operating
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its
documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made
or implied. Bridgetek Pte Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this
product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical
appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This
document provides preliminary information that may be subject to change without notice. No freedom to use patents or other
intellectual property rights is implied by the publication of this document. Bridgetek Pte Ltd, 178 Paya Lebar Road, #07-03,
Singapore 409030. Singapore Registered Company Number: 201542387H
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FT800 Embedded Video Engine Datasheet
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1 Typical Applications
Point of Sales Machines
Power meter
Multi-function Printers
Home appliance devices
Instrumentation
Set-top box
Home Security Systems
Thermostats
Graphic touch pad – remote, dial pad
Sprinkler system displays
Tele / Video Conference Systems
Medical Appliances
Phones and Switchboards
GPS / SatNav
Medical Appliances
Vending Machine Control Panels
Blood Pressure displays
Elevator Controls
Heart monitors
……and many more
Glucose level displays
Breathalyzers
Gas chromatographs
1.1 Part Numbers
Part Number
FT800Q-x
Package
48 Pin VQFN, pitch 0.5mm, body 7mm x 7mm x 0.9mm
Table 1- Video Controller Part Numbers
Note: Packaging codes for x is:
-R: Taped and Reel, (VQFN in 3000 pieces per reel)
-T: Tray packing, (VQFN in 260 pieces per tray)
For example: FT800Q-R is 3000 VQFN pieces in taped and reel packaging
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FT800 Embedded Video Engine Datasheet
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2 FT800 Block Diagram
Figure 2-1 FT800 Block Diagram
For a description of each function please refer to Section 4.
Figure 2-2 FT800 System Design Diagram
FT800 or EVE (Embedded Video Engine) simplifies the system architecture for advanced human
machine interfaces (HMIs) by providing functionality for display, audio, and touch as well as an
object oriented architecture approach that extends from display creation to the rendering of the
graphics.
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FT800 Embedded Video Engine Datasheet
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Table of Contents
1
Typical Applications................................................. 2
1.1
Part Numbers ......................................................................2
2
FT800 Block Diagram .............................................. 3
3
Device Pin Out and Signal Description ..................... 6
3.1
VQFN-48 Package Pin Out ...................................................6
3.2
Pin Description ....................................................................7
4
Function Description ............................................. 10
4.1
Serial Host Interface ......................................................... 10
4.1.1
SPI Interface .................................................................................... 12
4.1.2
I²C Interface .................................................................................... 12
4.1.3
Serial Data Protocol........................................................................... 12
4.1.4
Host Memory Read ............................................................................ 12
4.1.5
Host Memory Write ........................................................................... 13
4.1.6
Host Command ................................................................................. 13
4.1.7
Interrupts ........................................................................................ 14
4.2
System Clock .....................................................................15
4.2.1
Clock Source .................................................................................... 15
4.2.2
Phase Locked Loop ............................................................................ 16
4.2.3
Clock Enable .................................................................................... 16
4.2.4
Clock Frequency ............................................................................... 16
4.3
Graphics Engine ................................................................ 16
4.3.1
Introduction ..................................................................................... 16
4.3.2
ROM and RAM Fonts .......................................................................... 17
4.4
Parallel RGB Interface ....................................................... 20
4.5
Miscellaneous Control ....................................................... 21
4.5.1
Backlight Control Pin ......................................................................... 21
4.5.2
DISP Control Pin ............................................................................... 21
4.5.3
General Purpose IO pins .................................................................... 21
4.5.4
Pins Drive Current Control.................................................................. 22
4.6
Audio Engine .....................................................................22
4.6.1
Sound Synthesizer ............................................................................ 22
4.6.2
Audio Playback ................................................................................. 24
4.7
Touch-Screen Engine ......................................................... 24
4.8
Power Management ........................................................... 26
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4.8.1
Power supply .................................................................................... 26
4.8.2
Internal Regulator and POR ................................................................ 26
4.8.3
Power Modes .................................................................................... 27
5
FT800 Memory Map ............................................... 30
5.1
6
FT800 Registers ................................................................ 30
Devices Characteristics and Ratings ...................... 33
6.1
Absolute Maximum Ratings ...............................................33
6.2
DC Characteristics ............................................................. 33
6.3
Touch Sense Characteristics ..............................................34
6.4
AC Characteristics ............................................................. 35
6.4.1
System clock .................................................................................... 35
6.4.2
Host Interface SPI Mode 0 ................................................................. 35
6.4.3
Host Interface I2C Mode Timing .......................................................... 36
6.4.4
RGB Video Timing ............................................................................. 36
7
Application Examples ............................................ 38
7.1
Examples of LCD Interface connection .............................. 38
7.2
Examples of PWM Audio Circuits .......................................38
8
Package Parameters .............................................. 39
8.1
VQFN-48 Package Dimensions ...........................................39
8.1.1 Top Side ............................................................................................... 39
8.1.2 Bottom Side .......................................................................................... 39
8.2
VQFN-48 Package Dimensions ...........................................40
8.3
Solder Reflow Profile ......................................................... 41
9
Contact Information .............................................. 42
Appendix A – References ............................................. 43
Document References ................................................................ 43
Acronyms and Abbreviations ..................................................... 43
Appendix B - List of Figures and Tables ....................... 44
List of Figures ............................................................................44
List of Tables .............................................................................44
Appendix C - Revision History ...................................... 46
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3 Device Pin Out and Signal Description
3.1 VQFN-48 Package Pin Out
Figure 3-1 Pin Configuration VQFN-48 (top view)
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3.2 Pin Description
1
Pin No.
Name
AUDIO_L
O
2
3
GND
SPI_SCLK/ I2C_SCL
P
I
4
MISO/ I2C_SDA
I/O
5
MOSI/ I2C_SA0
I
6
CS_N/ I2C_SA1
I
7
GPIO0/ I2C_SA2
I/O
8
GPIO1
I/O
9
VCCIO
P
10
MODE
I
11
INT_N
OD
12
PD_N
I
13
X1/ CLK
I
14
X2
O
15
16
17
GND
VCC
VCC1V2
P
P
O
18
19
VCC
X+
P
AI/O
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Type
Description
Audio PWM out, push-pull output, 16mA
sink/source current.
Pad powered from pin VCC.
Ground
In SPI mode: SPI SCLK input.
In I2C mode: SCL input, need external 1kΩ ~
4.7kΩ pull up to VCCIO.
Input pad with Schmitt trigger, 3.3V tolerant.
Pad powered from pin VCCIO.
In SPI mode: SPI MISO output.
In I2C mode: SDA input/Open Drain Output,
need external1kΩ ~ 4.7kΩ pull up to VCCIO.
Input with Schmitt trigger, 3.3V tolerant,
4/8/12/16mA sink/source current.
Pad powered from pin VCCIO.
In SPI mode: SPI MOSI input.
In I2C mode: Input, bit 0 of I2C device address.
Input pad, 3.3V tolerant.
Pad powered from pin VCCIO.
In SPI mode: SPI CS_N input, active low.
In I2C mode: Input, bit 1 of I2C device address.
Input pad, 3.3V tolerant.
Pad powered from pin VCCIO.
In SPI mode: General purpose input, output port.
In I2C mode: Input, bit 2 of I2C device address.
Push-pull, three-state output. 3.3V tolerant,
4/8/12/16mA sink/source current.
Pad powered from pin VCCIO.
General purpose input, output port.
Push-pull, three-state output. 3.3V tolerant,
4/8/12/16mA sink/source current.
Pad powered from pin VCCIO.
I/O power supply, connect a 0.1uF decoupling
capacitor. Support 1.8V, 2.5V or 3.3V.
Note: VCCIO supply to IO pads from pin 3 to 12
only.
Host interface SPI(pull low) or I2C(pull up) mode
select input, 3.3V tolerant
Pad powered from pin VCCIO.
Host Interrupt, open drain output, active low,
pull up to VCCIO through a 1kΩ ~10kΩ resistor.
Power down input, active low, 3.3V tolerant, pull
up to VCCIO through 47kΩ resistor and 100nF to
ground.
Pad powered from pin VCCIO.
Crystal oscillator or clock input; Connect to GND
if not used.
3.3V peak input allowed.
Pad powered from pin VCC.
Crystal oscillator output; leave open if not used.
Pad powered from pin VCC.
Ground
3.3V power supply input.
1.2V regulator output pin. Connect a 4.7uF
decoupling capacitor to GND.
3.3V power supply input.
Connect to X right electrode of 4-wire touchscreen panel.
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FT800 Embedded Video Engine Datasheet
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Pin No.
Name
Type
20
Y+
AI/O
21
X-
AI/O
22
Y-
AI/O
23
24
GND
BACKLIGHT
P
O
25
DE
O
26
VSYNC
O
27
HSYNC
O
28
DISP
O
29
PCLK
O
30
B7
O
31
B6
O
32
B5
O
33
B4
O
34
B3
O
35
B2
O
36
37
GND
G7
P
O
38
G6
O
39
G5
O
40
G4
O
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Description
Pad powered from pin VCC.
Connect to Y top electrode of 4-wire touch-screen
panel.
Pad powered from pin VCC.
Connect to X left electrode of 4-wire touchscreen panel.
Pad powered from pin VCC.
Connect to Y bottom electrode of 4-wire touchscreen panel.
Pad powered from pin VCC.
Ground
LED Backlight brightness PWM controls signal,
push-pull output, 4/8mA sink/source current.
Pad powered from pin VCC.
LCD Data Enable, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
LCD Vertical Sync, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
LCD Horizontal Sync, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
General purpose output pin for LCD Display
Enable, push-pull output, 4/8mA sink/source
current. Control by writing to Bit 7 of REG_GPIO
register.
Pad powered from pin VCC.
LCD Pixel Clock, push-pull output, 4/8mA
sink/source current.
Pad powered from pin VCC.
Bit 7 of Blue RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 6 of Blue RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 5 of Blue RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 4 of Blue RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 3 of Blue RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 2 of Blue RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Ground
Bit 7 of Green RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 6 of Green RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 5 of Green RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
Bit 4 of Green RGB signals, push-pull output,
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Pin No.
Name
41
G3
42
G2
43
R7
44
R6
45
R5
46
R4
47
R3
48
R2
EP
GND
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Type
Description
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 3 of Green RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 2 of Green RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 7 of Red RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 6 of Red RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 5 of Red RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 4 of Red RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 3 of Red RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
O
Bit 2 of Red RGB signals, push-pull output,
4/8mA sink/source current.
Pad powered from pin VCC.
P
Ground. Exposed thermal pad.
Table 3-1 FT800Q pin description
Note:
P
I
O
OD
I/O
AI/O
:
:
:
:
:
:
Power or ground
Input
Output
Open drain output
Bi-direction Input and Output
Analog Input and Output
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4 Function Description
The FT800 is a single chip, embedded graphic controller with the following function blocks:
Serial Host Interface
System Clock
Graphics Engine
Parallel RGB video interface
Audio Engine
Touch-screen Engine
Power Management
The functions for each block are briefly described in the following subsections.
4.1 Serial Host Interface
The FT800 uses a standard serial interface to communicate with most types of microcontrollers and
microprocessors. The interface mode is configurable by pull down for SPI and pull up for I²C on pin 10
(MODE). Figure 4-1 shows the two alternative mode connections.
Figure 4-1 Host Interface Options
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Figure 4-2 illustrates a direct connection to a 1.8-3.3V IO MPU/MCU.
1.8-3.3V
3.3V
Vio
MPU/MCU
4.7k
4.7k
VCC
FT800
CS_N
CS_N
MISO
MISO
MOSI
MOSI
SCLK
SCLK
PD_N
PD_N
INT_N
INT_N
GND
GND
Figure 4-2 SPI Interface 1.8-3.3V connection
Figure 4-3 illustrates the FT800 connected to a 5V IO MPU/MCU. The 74LCX125 logic buffer can tolerate
5V signal from the MPU/MCU, and the FT800 input signals are limited to 3.3V.
3.3V
5V
74LCx125
Vio
MPU/MCU
VCC
FT800
CS_N
CS_N
MISO
MISO
MOSI
MOSI
SCLK
SCLK
PD_N
PD_N
INT_N
INT_N
GND
4.7K
3.3V
GND
4.7K
GND
Figure 4-3 SPI Interface 5V connection
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SPI Interface
The SPI slave interface operates up to 30MHz. Only SPI mode 0 is supported. Refer to section 6.4.2 for
detailed timing specification.
The SPI interface is selected when the MODE pin is tied to GND.
4.1.2
I²C Interface
The I²C slave interface operates up to 3.4MHz, supporting standard-mode, fast-mode, fast-mode plus
and high-speed mode. Refer to section 6.4.3for detailed timing specification.
The I²C device address is configurable between 20h to 27h depending on the I²C_SA[2:0] pin setting,
i.e. the 7-bit I2C slave address is 0b’0100A2A1A0.
The I²C interface is selected when the MODE pin is tied to VCCIO.
4.1.3
Serial Data Protocol
The FT800 appears to the host MPU/MCU as a memory-mapped SPI or I²C device. The host
communicates with the FT800 using reads and writes to a large (4 megabyte) address space. Within this
address space are dedicated areas for graphics, audio and touch control. Refer to section 5 for the
detailed memory map.
The host reads and writes the FT800 address space using SPI or I²C transactions. These transactions are
memory read, memory write and command write. Serial data is sent by the most significant bit first. For
I²C transactions, the same byte sequence is encapsulated in the I²C protocol.
For SPI operation, each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s
no limit on data length within one transaction, as long as the memory address is continuous.
4.1.4
Host Memory Read
For SPI memory read transaction, the host sends two zero bits, followed by the 22-bit address. This is
followed by a dummy byte. After the dummy byte, the FT800 responds to each host byte with read data
bytes.
7
6
0
0
5
4
3
2
1
0
Address [21:16]
Address [15:8]
Write
Address
Address [7:0]
Dummy byte
Byte 0
Read Data
Byte n
Table 4-1 Host memory read transaction (SPI)
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For I2C memory read transaction, bytes are packed in the I2C protocol as follow:
[start]
[restart]
....
[stop]
4.1.5
Host Memory Write
For SPI memory write transaction, the host sends a ‘1’ bit and ‘0’ bit, followed by the 22-bit address. This
is followed by the write data.
7
6
1
0
5
3
4
1
2
0
Address [21:16]
Address [15:8]
Address [7:0]
Write
Address
Byte 0
Byte n
Table 4-2 Host memory write transaction (SPI)
For
I2C,
memory write transaction bytes are packed in the I2C protocol as follow:[start]
....
[stop]
4.1.6
Write Data
Host Command
When sending a command, the host transmits a 3 byte command. Table 4-3 lists all the host command
functions.
Note: ACTIVE command is generated by dummy memory read from address 0 when FT800 is in sleep or
standby mode.
For SPI command transaction, the host sends a ‘0’ bit and ‘1’ bit, followed by the 6-bit command code.
This is followed by 2 bytes 00h.
7
6
0
1
0
0
0
0
0
0
0
0
0
0
5
4
3
1
0
0
0
0
0
0
0
2
Command [5:0]
Table 4-3 Host command transaction (SPI)
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For I2C command transaction, bytes are packed in the I2C protocol as follows:
[start]
[stop]
2nd byte
3rd byte
Command
Description
00000000b
00000000b
00000000b
00h
ACTIVE
01000001b
00000000b
00000000b
41h
STANDBY
01000010b
00000000b
00000000b
Switch from Standby/Sleep modes to
active mode. Dummy read from address
0 generates ACTIVE command.
Put FT800 core to standby mode. Clock
gate off, PLL and Oscillator remain on
(default).
Put FT800 core to sleep mode. Clock
gate off, PLL and Oscillator off.
01010000b
00000000b
00000000b
1st Byte
Power Modes
42h
SLEEP
50h
PWRDOWN
Switch off 1.2V internal regulator. Clock,
PLL and Oscillator off.
Clock Switching
01000100b
00000000b
00000000bN
A
01100010b
00000000b
00000000bN
A
01100001b
00000000b
00000000b
44h
CLKEXT
62h
CLK48M
61h
CLK36M
Enable PLL input from Crystal oscillator
or external input clock.
Switch PLL output clock to 48MHz
(default).
Switch PLL output clock to 36MHz.
Miscellaneous
00000000b
Send reset pulse to FT800 core. All
registers and state machines will be
reset.
Table 4-4 Host Command Table
Note: Any command code not specified is reserved and should not be used by the software
01101000b
4.1.7
00000000b
68h
CORERST
Interrupts
The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tristate (pulled to
high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when any of the interrupt
flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Writing a ‘1’ in any bit of
REG_INT_MASK will enable the correspond interrupt. Each bit in REG_INT_FLAGS is set by a
corresponding interrupt source. REG_INT_FLAGS is readable by the host at any time, and clears when
read.
When the FT800 is in sleep mode, a touch event detected on the touch-screen will drive the INT_N pin to
low regardless the setting of REG_INT_EN and REG_INT_MASK. The MCU can use this signal to serve as
a wakeup event.
Bit
Interrupt Sources
Conditions
Bit
Interrupt Sources
Conditions
7
CONVCOMPLETE
Touch-screen
conversions
completed
3
SOUND
Sound effect
ended
Table 4-5
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6
CMDFLAG
Command FIFO
flag
2
TAG
Touch-screen tag
value change
Interrupt Flags bit
5
CMDEMPTY
Command FIFO
empty
1
TOUCH
Touch-screen
touch detected
assignment
4
PLAYBACK
Audio playback
ended
0
SWAP
Display list swap
occurred
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4.2 System Clock
4.2.1
Clock Source
The FT800 can be configured to use any of the three clock sources for system clock:
Internal relaxation oscillator clock
External 12MHz crystal
External 12MHz square wave clock
Figure 4-5 and Figure 4-6 shows the pin connections for these clock options. Commands CLKEXT and
CLKINT switch between internal oscillator and external crystal oscillator and are synchronised to VSYNC
on the fly.
The external crystal oscillator is recommended for applications which require higher quality audio
reproduction.
Figure 4-4 Internal Relaxation Oscillator Connection
Figure 4-5 Crystal oscillator connection
Figure 4-6 External clock input
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Phase Locked Loop
The internal PLL takes input from the crystal oscillator. The PLL outputs clock to all internal circuits,
including graphics engine, audio engine and touch engine.
4.2.3
Clock Enable
Upon power on the FT800 enters standby mode, the system clock will be enabled when following steps
are executed:
-
Host sends an “ACTIVE” command (dummy read at address 0)
If the application choose to use the external clock source (12MHz crystal or clock), the following steps
shall be executed:
-
Host sends an “ACTIVE” command (dummy read at address 0)
Host sends an “CLKEXT” command
Host writes to REG_PCLK with non-zero value (i.e. 5)
If SPI is used as host interface, the SPI clock shall not exceed 11MHz before system clock is enabled.
After system clock is properly enabled, the SPI clock is allowed to go up to 30MHz.
4.2.4
Clock Frequency
Upon power-on the internal relaxation oscillator is untrimmed. The frequency range could be quite wide
from chip to chip (refer to table x-y for internal relaxation oscillator specifications). If the application
utilises the internal clock without external clock source, it is recommended to perform clock trimming by
software for better performance. For the details of clock trimming mechanism please refer to application
note AN_299_FT800_FT801_Internal_Clock_Trimming.
By default the system clock is 48MHz when the input clock is 12MHz. Host is allowed to switch the system
clock between 48MHz and 36MHz by the host command “CLK48MHz” and “CLK36MHz” respectively. The
clock switching is synchronised to VSYNC edge on the fly. This is to avoid possible graphics glitch during
clock switching. As a result, the clock switch will only take effect if the REG_PCLK is a non-zero value.
4.3 Graphics Engine
4.3.1
Introduction
The graphics engine executes the display list once for every horizontal line. It executes the primitive
objects in the display list and constructs the display line buffer. The horizontal pixel content in the line
buffer is updated if the object is visible at the horizontal line.
Main features of the graphics engine are:
The primitive objects supported by the graphics processor are: lines, points, rectangles, bitmaps
(comprehensive set of formats), text display, plotting bar graph, edge strips, and line strips, etc.
Operations such as stencil test, alpha blending and masking are useful for creating a rich set of
effects such as shadows, transitions, reveals, fades and wipes.
Anti-aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the viewer.
Bitmap transformations enable operations such as translate, scale and rotate.
Display pixels are plotted with 1/16th pixel precision.
Four levels of graphics states
Tag buffer detection
The graphics engine also supports customized build-in widgets and functionalities such as jpeg decode,
screen saver, calibration etc. The graphics engine interprets commands from the MPU host via a 4 Kbyte
FIFO in FT800 memory at RAM_CMD. The MPU/MCU writes commands into the FIFO, and the graphics
engine reads and executes the commands. The MPU/MCU updates register REG_CMD_WRITE to indicate
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Clearance No.: BRT#001
that there are new commands in the FIFO, and the graphics engine updates REG_CMD_READ after
commands have been executed.
Main features supported are:
Drawing of widgets such as buttons, clock, keys, gauges, text displays, progress bars, sliders,
toggle switches, dials, gradients, etc.
JPEG decode (Only baseline is supported)
Inflate functionality (zlib inflate is supported)
Timed interrupt (generate an interrupt to host processor after a specified number of
milliseconds)
In built animated functionalities such as displaying logo, calibration, spinner, screen saver and
sketch
Snapshot feature to capture the current graphics display
For a complete list of graphics engine display commands and widgets refer to FT800 Series Programmers
Guide, Chapter 4.
4.3.2
ROM and RAM Fonts
The FT800 has built in ROM character bitmaps as font metrics. The graphics engine can use these metrics
when drawing text fonts. There are total 16 ROM fonts, numbered with font handle 16-31. The user can
define and load customized font metrics into RAM_G, which can be used by display command with handle
0-15.
Each font metric block has a 148 byte font table which defines the parameters of the font and the pointer
of font image. The font table format is shown in Table 4-6.
Address Offset
0
128
132
136
140
144
Size(byte)
Parameter Description
128
width of each font character, in pixels
4
font bitmap format, for example L1, L4 or L8
4
font line stride, in bytes
4
font width, in pixels
4
font height, in pixels
4
pointer to font image data in memory
Table 4-6 Font table format
The ROM fonts are stored in the memory space ROM_FONT. The ROM font table is also stored in the
ROM. The starting address of ROM font table for font index 16 is stored at ROM_FONT_ADDR, with other
font tables follow. The ROM font table and individual character width (in pixel) are listed in Table 4-7
through Table 4-9. Font index 16, 18 and 20-31 are for basic ASCII characters (code 0-127), while font
index 17 and 19 are for Extended ASCII characters (code 128-255). The character width for font index 17
or 19 is fixed at 8 pixels for any of the Extended ASCII characters.
20
L1
2
10
13
21
L1
2
13
17
22
L1
2
14
20
23
L1
3
17
22
24
L1
3
24
29
25
L1
4
30
38
26
L4
6
12
16
Image pointer
start address
(hex)
FFBFC
FF7FC
FEFFC
FE7FC
FDAFC
FCD3C
FBD7C
FA17C
F7E3C
F3D1C
F201C
27
L4
8
16
20
28
L4
9
18
25
29
L4
11
22
28
30
L4
14
28
36
31
L4
18
36
49
BB23C
19
L1
1
8
16
D2C3C
18
L1
1
8
16
E01BC
17
L1
1
8
8
E7F9C
16
L1
1
8
8
EDC1C
Font Index
Font format
Line stride
Font width
Font height
29
-
30
-
31
-
Table 4-7 ROM font table
ASCII
Character width
in pixels
Font Index =>
0
NULL
1
SOH
2
STX
3
ETX
4
EOT
5
ENQ
16
-
18
-
Copyright © Bridgetek Pte Ltd
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
17
FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Font Index =>
6
ACK
7
BEL
8
BS
9
HT
10
LF
11
VT
12
FF
13
CR
14
SO
15
SI
16
DLE
17
DC1
18
DC2
19
DC3
20
DC4
21
NAK
22
SYN
23
ETB
24
CAN
25
EM
26
SUB
27
ESC
28
FS
29
GS
30
RS
31
US
32
space
33
!
34
"
35
#
36
$
37
%
38
&
39
'
40
(
41
)
42
*
43
+
44
,
45
46
.
47
/
48
0
49
1
50
2
51
3
52
4
53
5
54
6
55
7
56
8
57
9
58
:
59
;
60
<
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Copyright © Bridgetek Pte Ltd
20
3
3
4
6
6
9
8
2
4
4
4
6
3
4
3
3
6
6
6
6
6
6
6
6
6
6
3
3
6
21
4
4
5
8
8
12
10
3
5
5
7
9
3
4
3
4
8
8
8
8
8
8
8
8
8
8
3
4
8
22
5
5
6
9
9
14
11
3
6
6
6
10
4
5
4
5
9
9
9
9
9
9
9
9
9
9
4
4
10
23
5
6
5
10
10
16
13
3
6
6
7
10
5
6
5
5
10
10
10
10
10
10
10
10
10
10
5
5
10
24
6
6
8
14
13
22
17
6
8
8
10
14
6
8
6
7
13
13
13
13
13
13
13
13
13
13
6
6
15
25
9
9
12
19
18
29
22
6
11
11
13
19
9
11
9
9
18
18
18
18
18
18
18
18
18
18
9
9
19
26
3
4
5
9
8
10
9
3
5
5
6
8
3
6
4
6
8
8
8
8
8
8
8
8
8
8
4
4
7
27
4
4
6
11
10
12
11
4
6
6
7
10
4
8
5
7
10
10
10
10
10
10
10
10
10
10
4
4
9
Clearance No.: BRT#001
28
5
6
8
13
12
15
13
5
7
7
9
12
5
9
6
9
12
12
12
12
12
12
12
12
12
12
5
5
11
29
6
6
9
15
14
18
15
5
8
8
10
14
5
11
6
10
14
14
14
14
14
14
14
14
14
14
6
6
12
30
8
8
11
19
18
23
19
7
11
10
13
18
7
14
8
13
17
17
17
17
17
17
17
17
17
17
8
8
16
18
31
10
11
15
26
24
31
26
9
14
14
18
24
9
19
11
17
24
24
24
24
24
24
24
24
24
24
11
11
21
FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Font Index =>
61
=
62
>
63
?
64
@
65
A
66
B
67
C
68
D
69
E
70
F
71
G
72
H
73
I
74
J
75
K
76
L
77
M
78
N
79
O
80
P
81
Q
82
R
83
S
84
T
85
U
86
V
87
W
88
X
89
Y
90
Z
91
[
92
\
93
]
94
^
95
_
96
`
97
a
98
b
99
c
100
d
101
e
102
f
103
g
104
h
105
i
106
j
107
k
108
l
109
m
110
n
111
o
112
p
113
q
114
r
115
s
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Copyright © Bridgetek Pte Ltd
20
5
6
6
11
7
7
8
8
7
6
8
8
3
5
7
6
9
8
8
7
8
7
7
5
8
7
9
7
7
7
3
3
3
6
6
3
5
6
5
6
5
4
6
6
2
2
5
2
8
6
6
6
6
4
5
21
9
8
8
13
9
9
10
10
9
8
11
10
4
7
9
8
12
10
11
9
11
10
9
9
10
9
13
9
9
9
4
4
4
7
8
5
8
7
7
8
8
4
8
8
3
3
7
3
11
8
8
8
8
5
7
22
10
10
9
17
11
11
12
12
11
10
13
12
4
8
11
9
13
12
13
11
13
12
11
10
12
11
15
11
11
10
5
5
5
8
9
6
9
9
8
9
9
5
9
9
3
4
8
3
14
9
9
9
9
5
8
23
11
10
10
18
13
13
14
14
13
12
15
14
6
10
13
11
16
14
15
13
15
14
13
12
14
13
18
13
13
12
5
5
5
9
11
4
11
11
10
11
10
6
11
10
4
4
9
4
16
10
11
11
11
6
9
24
15
15
12
25
17
17
18
18
16
14
19
18
8
13
18
14
21
18
18
16
18
17
16
16
18
17
22
17
16
15
7
7
7
12
14
7
13
14
12
14
13
8
14
13
6
6
12
6
20
14
13
14
14
9
12
25
19
19
18
34
22
22
24
24
22
20
25
24
9
16
22
18
27
24
25
22
26
24
22
20
24
22
31
22
22
20
9
9
9
16
18
11
18
18
16
18
18
9
18
18
7
7
16
7
27
18
18
18
18
11
16
26
8
7
7
13
9
9
9
9
8
8
9
10
4
8
9
8
12
10
10
9
10
9
9
9
9
12
9
9
8
4
6
4
6
7
4
8
8
7
8
7
5
8
8
4
4
8
4
12
8
8
8
8
5
7
5
27
10
9
8
15
11
11
11
12
9
9
12
12
5
9
11
9
15
12
12
11
12
11
10
10
12
11
15
11
11
10
5
7
5
7
8
5
9
10
9
10
9
6
10
10
4
4
9
4
15
10
10
10
10
6
9
Clearance No.: BRT#001
28
12
11
10
19
13
13
13
14
12
12
14
15
6
12
14
12
18
15
14
13
15
13
13
13
14
14
18
13
13
13
6
9
6
9
10
7
12
12
11
12
11
8
12
12
5
5
11
5
18
12
12
12
12
7
11
29
14
13
11
21
15
15
15
16
13
13
16
17
7
13
15
13
21
17
16
15
17
15
15
14
16
15
21
15
15
14
7
10
6
10
11
8
13
14
13
14
13
9
14
14
6
6
13
6
21
14
14
14
14
8
13
30
17
16
15
28
20
20
20
21
17
17
21
22
9
17
20
17
27
22
21
20
22
20
19
19
21
20
27
20
20
19
8
13
8
13
15
10
17
18
16
18
16
11
18
18
8
8
16
8
27
18
18
18
18
11
16
19
31
24
22
20
38
27
27
27
28
23
23
28
30
12
23
27
23
36
30
29
27
29
27
26
25
28
27
36
27
27
25
11
18
11
18
20
13
23
24
22
24
22
15
24
24
11
11
22
11
37
24
24
24
24
15
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FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Font Index =>
116
t
117
u
118
v
119
w
120
x
121
y
122
z
123
{
124
|
125
}
126
~
127
DEL
Clearance No.: BRT#001
16 18 20 21 22 23 24 25 26 27 28
8
8
4
4
5
6
8
9
8
6
7
8
8
5
7
9
10
14
18
7
10
12
8
8
6
7
8
10
13
16
11
9
11
8
8
8
10
12
14
18
23
7
13
16
8
8
6
7
8
10
12
16
7
9
11
8
8
5
7
8
10
13
16
7
9
11
8
8
5
7
8
9
12
16
5
9
11
8
8
3
5
6
6
8
11
3
6
7
8
8
3
3
4
5
6
9
5
4
5
8
8
3
5
6
6
8
11
10
6
7
8
8
7
8
10
10
14
19
3
12
14
8
8
0
0
0
0
0
0
2
4
5
Table 4-8 ROM font ASCII character width in pixels
29
8
14
12
18
12
12
12
8
6
8
16
6
30
10
18
16
23
16
16
16
11
8
11
21
8
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
Ç
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
É
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
á
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
░
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
└
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
ð
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
Ó
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
ü
é
â
ä
à
å
ç
ê
ë
è
ï
î
ì
æ
Æ
ô
ö
ò
û
ù
ÿ
Ö
Ü
ø
£
Ø
í
ó
ú
ñ
Ñ
ª
º
¿
®
¬
½
¼
¡
▒
▓
│
┤
Á
Â
À
©
╣
║
╗
╝
¢
┴
┬
├
─
┼
ã
Ã
╚
╔
╩
╦
╠
═
Ð
Ê
Ë
È
ı
Í
Î
Ï
┘
┌
█
▄
¦
ß
Ô
Ò
õ
Õ
µ
þ
Þ
Ú
Û
Ù
ý
Ý
Symbol
Decimal
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
31
13
24
21
32
21
21
21
14
10
14
29
10
±
‗
¾
¶
§
÷
¸
°
¨
·
¹
³
²
Ì
¯
╬
■
Å
ƒ
»
┐
¤
´
nbsp
▀
Table 4-9 ROM font Extended ASCII characters
Note 1: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters.
Ä
×
«
¥
Note 2: All fonts included in the FT800 ROM are widely available to the market-place for general usage.
See section nine for specific copyright data and links to the corresponding license agreements.
4.4 Parallel RGB Interface
The RGB parallel interface consists of 23 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 signals each for R,
G and B.
Several registers configure the LCD operation of these signals as follow:
REG_PCLK is the PCLK divisor the default is 0, and disables the PCLK output.
PCLK frequency = System Clock frequency / REG_PCLK
PCLK_POL define the clock polarity, =0 for positive active clock edge, and 1 for negative clock edge.
REG_CSPREAD controls the transition of RGB signals with respect to PCLK active clock edge. When
REG_CSPREAD=0, R[7:2], G[7:2] and B[7:2] signals change following the active edge of PCLK. When
Copyright © Bridgetek Pte Ltd
20
FT800 Embedded Video Engine Datasheet
Version 1.4
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Clearance No.: BRT#001
REG_CSPREAD=1, R[7:2] changes a PCLK clock early and B[7:2] a PCLK clock later, which helps reduce
the switching noise.
REG_DITHER enables colour dither; the default is enabled. This option improves the half-tone appearance
on displays. Internally, the graphics engine computes the colour values at an 8 bit precision; however,
the LCD colour at a lower precision is sufficient. The FT800 output is only 6 bits per colour in 6:6:6
formats and a 2X2 dither matrix allow the truncated bits to contribute to the final colour values.
REG_OUTBITS gives the bit width of each colour channel, the default is 6, 6, 6 bits for each RGB colour.
A lower value means fewer bits are output for each channel allowing dithering on lower precision LCD
displays.
REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD
panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed.
Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows
rotation to be enabled. If Bit 3 is set, then (R,G,B) is rotated right if bit 2 is one, or left if bit 2 is zero.
REG_SWIZZLE
b3 b2 b1 b0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
PINS
R7, R6, R5,
G7, G6, G5,
B7, B6, B5, B4,
R4, R3, R2
G4, G3, G2
B3, B2
R[7:2]
G[7:2]
B[7:2]
Power on Default
R[2:7]
G[2:7]
B[2:7]
B[7:2]
G[7:2]
R[7:2]
B[2:7]
G[2:7]
R[2:7]
G[7:2]
B[7:2]
R[7:2]
G[2:7]
B[2:7]
R[2:7]
G[7:2]
R[7:2]
B[7:2]
G[2:7]
R[2:7]
B[2:7]
B[7:2]
R[7:2]
G[7:2]
B[2:7]
R[2:7]
G[2:7]
R[7:2]
B[7:2]
G[7:2]
R[2:7]
B[2:7]
G[2:7]
Table 4-10 REG_SWIZZLE RGB Pins Mapping
4.5 Miscellaneous Control
4.5.1
Backlight Control Pin
The backlight control pin is a pulse width modulated (PWM) signal controlled by two registers:
REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output frequency, the range is
250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128. A value of 0 means that the
PWM is completely off and 128 means completely on.
4.5.2
DISP Control Pin
The DISP pin is a general purpose output that can be used to enable or as a reset control to LCD display
panel. The pin is controlled by writing to Bit 7 of REG_GPIO register.
4.5.3
General Purpose IO pins
The GPIO1 and GPIO0 pins are default inputs. Write '1' to Bit 1 and 0 of REG_GPIO_DIR to change to
output pins respectively. In I²C mode the GPIO0 is used as SA2 and is not available as GPIO.
GPIO1 and GPIO0 are read from or write to bit 1 and 0 of REG_GPIO register. GPIO1 is recommended to
be used as shutdown control for audio power amplifier.
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4.5.4
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Pins Drive Current Control
The output drive current of output pins can be changed as per the following table by writing to bit[6:2] of
REG_GPIO register:
REG_GPIO
Value
Drive
Current
Pins
00b#
4mA
Bit[6:5]
01b
10b
8mA
12mA
11b
16mA
GPIO1
GPIO0
Bit[4]
0b#
1b
4mA
8mA
00b#
4mA
Bit[3:2]
01b
10b
8mA
12mA
PCLK
DISP
VSYNC
HSYNC
DE
R7..R2
G7..G2
B7..B2
BACKLIGHT
11b
16mA
MISO
INT_N
Table 4-11 Output drive current selection
Note: #Default value
4.6 Audio Engine
FT800 provides mono audio output through a PWM output pin, AUDIO_L. It outputs the two audio
sources, the sound synthesizer and audio file playback.
4.6.1
Sound Synthesizer
A sound processor, AUDIO ENGINE, generates the sound effects from a small ROM library of waves table.
To play a sound effect listed in Table 4.3, load the REG_SOUND register with a code value and write 1 to
the REG_PLAY register. The REG_PLAY register reads 1 while the effect is playing and returns a ‘0’ when
the effects end. Some sound effects play continuously until it is interrupted or commanded to play the
next sound effect. To interrupt an effect, write a new value to REG_SOUND and REG_PLAY registers; e.g.
write 0 (Silence) to REG_SOUND and 1 to PEG_PLAY to stop the sound effect.
The sound volume is controlled by register REG_VOL_SOUND. The 16-bit REG_SOUND register takes an
8-bit sound in the low byte. For some sounds, marked "pitch adjust" in the table below, the high 8 bits
contain a MIDI note value. For these sounds, note value of zero indicates middle C. For other sounds the
high byte of REG_SOUND is ignored.
Value
Pitch adjust
Effect
Value
Pitch adjust
Effect
00h
01h
N
Y
Silence
square wave
32h
33h
N
N
DTMF 2
DTMF 3
02h
03h
Y
Y
sine wave
sawtooth wave
34h
35h
N
N
DTMF 4
DTMF 5
04h
05h
Y
Y
triangle wave
Beeping
36h
37h
N
N
DTMF 6
DTMF 7
06h
07h
Y
Y
Alarm
Warble
38h
39h
N
N
DTMF 8
DTMF 9
08h
10h
Y
Y
Carousel
1 short pip
40h
41h
Y
Y
harp
xylophone
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11h
Y
2 short pips
42h
Y
tuba
12h
13h
Y
Y
3 short pips
4 short pips
43h
44h
Y
Y
glockenspiel
organ
14h
Y
5 short pips
45h
Y
trumpet
15h
16h
Y
Y
6 short pips
7 short pips
46h
47h
Y
Y
piano
chimes
17h
18h
Y
Y
8 short pips
9 short pips
48h
49h
music box
bell
19h
1Ah
Y
Y
10 short pips
11 short pips
50h
51h
Y
Y
N
N
1Bh
1Ch
Y
Y
12 short pips
13 short pips
52h
53h
N
N
cowbell
notch
1Dh
1Eh
Y
Y
14 short pips
15 short pips
54h
55h
N
N
hihat
kickdrum
1Fh
Y
16 short pips
56h
pop
23h
N
DTMF #
57h
N
N
clack
58h
60h
N
N
chack
mute
N
unmute
2Ch
30h
N
N
DTMF *
DTMF 0
31h
N
DTMF 1
61h
Table 4-12 Sound Effect
MIDI
note
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
ANSI
note
A0
A#0
B0
C1
C#1
D1
D#1
E1
F1
F#1
G1
G#1
A1
A#1
B1
C2
C#2
D2
D#2
E2
F2
F#2
G2
G#2
A2
A#2
B2
C3
C#3
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Freq
(Hz)
27.5
29.1
30.9
32.7
34.6
36.7
38.9
41.2
43.7
46.2
49.0
51.9
55.0
58.3
61.7
65.4
69.3
73.4
77.8
82.4
87.3
92.5
98.0
103.8
110.0
116.5
123.5
130.8
138.6
MIDI
note
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
ANSI
note
F4
F#4
G4
G#4
A4
A#4
B4
C5
C#5
D5
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
click
switch
Freq (Hz)
349.2
370.0
392.0
415.3
440.0
466.2
493.9
523.3
554.4
587.3
622.3
659.3
698.5
740.0
784.0
830.6
880.0
932.3
987.8
1046.5
1108.7
1174.7
1244.5
1318.5
1396.9
1480.0
1568.0
1661.2
1760.0
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FT800 Embedded Video Engine Datasheet
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50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
4.6.2
D3
D#3
E3
F3
F#3
G3
G#3
A3
A#3
B3
C4
C#4
D4
D#4
E4
146.8
94
A#6
155.6
95
B6
164.8
96
C7
174.6
97
C#7
185.0
98
D7
196.0
99
D#7
207.7
100
E7
220.0
101
F7
233.1
102
F#7
246.9
103
G7
261.6
104
G#7
277.2
105
A7
293.7
106
A#7
311.1
107
B7
329.6
108
C8
Table 4-13 MIDI Note Effect
Clearance No.: BRT#001
1864.7
1975.5
2093.0
2217.5
2349.3
2489.0
2637.0
2793.8
2960.0
3136.0
3322.4
3520.0
3729.3
3951.1
4186.0
Audio Playback
The FT800 can play back recorded sound through its audio output. To do this, load the original sound
data into the FT800’s RAM, and set registers to start the playback.
The registers controlling audio playback are:
REG_PLAYBACK_START:
the start address of the audio data
REG_PLAYBACK_LENGTH:
the length of the audio data, in bytes
REG_PLAYBACK_FREQ:
the playback sampling frequency, in Hz
REG_PLAYBACK_FORMAT:
the playback format, one of LINEAR SAMPLES, uLAW
SAMPLES, or ADPCM SAMPLES
REG_PLAYBACK_LOOP:
if zero, sample is played once. If one, sample is repeated
indefinitely
REG_PLAYBACK_PLAY: a
write to this location triggers the start of audio playback,
regardless of writing ‘0’ or ‘1’. Read back ‘1’ when playback
is ongoing, and ‘0’ when playback finishes
REG_VOL_PB:
playback volume, 0-255
The mono audio format supported is 8-bits PCM, 8-bits uLAW and 4-bits IMA-ADPCM.
For
ADPCM_SAMPLES, each sample is 4 bits, so two samples are packed per byte, first sample is in bits 0-3
and the second is in bits 4-7.
The current audio playback read pointer can be queried by reading the REG_PLAYBACK_READPTR. Using
a large sample buffer, looping, and this read pointer, the host MPU/MCU can supply a continuous stream
of audio.
4.7 Touch-Screen Engine
The touch-screen consists of touch screen engine, ADC, Axis-switches, and ADC input multiplexer. The
touch screen engine reads commands from the memory map register and generates the required control
signals to the axis-switches and inputs mux and ADC. The ADC data are acquired and processed and
update in the respective register for the MPU/MCU to read.
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Y+
FT800
X+
Y+
XY-
X-
LCD Touch Screen
X+
Y-
Figure 4-7 Touch screen connection
The host controls the TOUCH SCREEN ENGINE operation mode by writing the REG_TOUCH_MODE.
REG_TOUCH_MODE
0
1
Mode
OFF
ONE-SHOT
Description
Acquisition stopped, only touch detection interrupt is still valid.
Perform acquisition once every time MPU write '1' to
REG_TOUCH_MODE.
2
FRAME-SYNC
Perform acquisition for every frame sync (~60 data
acquisition/second.
3
CONTINUOUS Perform acquisition continuously at approximately 1000 data
acquisition / second.
Table 4-14 Touch Controller Operating Mode
The Touch Screen Engine captures the raw X and Y coordinate and writes to register REG_TOUCH_RAW
XY. The range of these values is 0-1023. If the touch screen is not being pressed, both registers read
65535 (FFFFh).
These touch values are transformed into screen coordinates using the matrix in registers
REG_TOUCH_TRANSFORM_A-F.
The
post-transform
coordinates
are
available
in
register
REG_TOUCH_SCREEN_XY. If the touch screen is not being pressed, both registers read -32768 (8000h).
The values for REG TOUCH TRANSFORM A-F may be computed using an on-screen calibration process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer, delivering
a final 8-bit tag value, in REG TOUCH TAG. Because the tag lookup takes a full frame, and touch
coordinates change continuously, the original (x; y) used for the tag lookup is also available in
REG_TOUCH_TAG_XY.
Screen touch pressure is available in REG_TOUCH_RZ. The value is relative to the resistance of the touch
contact, a lower value indicates more pressure. The register defaults to 32767 when touch is not
detected. The REG_TOUCH_THRESHOLD can be set to accept a touch only when the force threshold is
exceeded.
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4.8 Power Management
4.8.1
Power supply
The FT800 may be operated with a single supply of 3.3V apply to VCC and VCCIO pins. For operation with
host MPU/MCU at lower supply, connect the VCCIO to MPU power to match the interface power.
Symbol
VCCIO
Typical
1.8V, or 2.5V, or 3.3V
VCC
3.3V
4.8.2
Description
Supply for Host interface digital I/O pad only, LCD RGB
interface supply from VCC.
Supply for chip
Table 4-15 Power supply
Internal Regulator and POR
The 1.2V internal regulator provides power to the core circuit. The regulator is disabled when device is in
POWERDOWN state. Power down is activated either by the SCU command write or by holding down the
PD_N pin for at least 5mS to allow the 1.2V decoupling capacitor to discharge fully. The regulator is
enabled only by releasing the PD_N pin. A 47kΩ resistor is recommended to pull the PD_N pin up to
VCCIO, together with a 100nF capacitor to ground in order to delay the 1.2V regulator powering up after
the VCC and VCCIO are stable.
The 1.2V internal regulator requires a compensation capacitor to be stable. A typical design puts a 4.7uF
capacitor with ESR >0.5Ω is required between VCC1V2 to GND pins. Do not connect any load to this pin.
The 1.2V regulator will generate Power-On-Reset (POR) pulse when the output voltage rises above the
POR threshold. The POR will reset all the core digital circuits.
It is possible to use PD_N pin as an asynchronous hardware reset input. Drive PD_N low for at least 5ms
and then drive it high will reset the FT800 chip.
VCC
R
VCC
47k
Cin
C
10uF
100nF
GND
1.2V
VCC1V2
Ccomp
FT800
4.7uF
GND
GND
PD_N
GND
VCCIO
GND
Figure 4-8 1.2V regulator
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Power Modes
When supply to VCCIO and VCC is applied, internal 1.2V regulator is powered by VCC. An internal POR
pulse will be generated during the regulator power up until it is stable. After the initial power up, the
FT800 will stay in STANDBY state. When needed, host can set FT800 to ACTIVE state by performing a
dummy read to address 0. The graphics engine, the audio engine and the touch engine are only
functional in ACTIVE state. To save power host can send command to put FT800 into any of the low
power mode: STANDBY, SLEEP and POWERDOWN. In addition, host is allowed to put FT800 in
POWERDOWN mode by drive PD_N pin to low, regardless what current state it is in. Refer to Figure 4-9
Power State Transition for the power state transitions.
Toggle PD_N from high
to low
VCC/VCCIO
Power ON
Toggle PD_N from low
to high
POWERDOWN
STANDBY
Dummy Read “0”
Write command “POWERDOWN”
Toggle PD_N from high to low or
Toggle PD_N from high
to low
Write command
“STANDBY”
Dummy Read “0”
SLEEP
ACTIVE
Write command “SLEEP”
Figure 4-9 Power State Transition
4.8.3.1 ACTIVE state
In ACTIVE state, the FT800 is in normal operation. The crystal oscillator and PLL are functioning. The
system clock applied to the FT800 core engines is enabled.
4.8.3.2 STANDBY state
In STANDBY state, the crystal oscillator and PLL remain functioning; the system clock applied to the
FT800 core engines is disabled. All register contents are retained.
4.8.3.3 SLEEP state
In SLEEP state, the crystal oscillator, PLL and system clock applied to the FT800 core engines are
disabled. All register contents are retained.
4.8.3.4 POWERDOWN state
In POWERDOWN state, the internal 1.2V regulator supplying the core digital logic, the crystal oscillator,
the PLL and the system clock applied to the FT800 core is disabled. All register contents are lost and
reset to default when the chip is next switched on.
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4.8.3.5 Wake up to ACTIVE from other power states
Wake up from POWERDOWN state requires the host to pull the PD_N pin down and release, a low to high
transition enables the 1.2V regulator. POR generated when 1.2V is stable and FT800 will switch to
STANDBY mode after internal oscillator and PLL are up (maximum 20ms from PD_N rising edge). The
clock enable sequence mentioned in section 4.2.3 shall be executed to proper enable the system clock.
From SLEEP state, host MPU reads at memory address 0 to wake the FT800 into ACTIVE state. Host
needs to wait for at least 20ms before accessing any registers or commands. This is to guarantee the
crystal oscillator and PLL are up and stable.
From STANDBY state, host MPU reads at memory address 0 to wake the FT800 into ACTIVE state. Host
can immediately access any register or command.
4.8.3.6 Pin Status at Different Power States
The FT800 pin status depends on the power state of the chip. See the following table for more details. At
power transition from ACTIVE to STANDBY or ACTIVE to SLEEP, all pins retains their previous status. The
software needs to set AUDIO_L, BACKLIGHT and PCLK to a known state before issuing power transition
commands.
Pin
Reset State
Reset State
Active/Sta
Power down
Hybrid Mode
Name
(VCC / VCCIO
(VCC / VCCIO ON)
ndby/Sleep
state (VCC
(VCC OFF /
ON)
Default Output Drive
state (VCC
ON / VCC1.2
VCCIO ON)
Strength
/ VCCIO
OFF)
ON)
AUDIO_L
Tristate Output
16mA
Output
Retain
(hi-Z)
previous state
SPI_SCL
Input (floating)
Input
Input (floating)
K/I2C_S
CL
MISO/I2
Tristate Output
4mA
Input/output
Tristate Output
C_SDA
(hi-Z)
(hi-Z)
MOSI/I2
Input (floating)
Input
Input (floating)
C_SA0
CS_N/I2
Input (floating)
Input
Input (floating)
C_SA1
GPIO0/I2 Input (floating)
Input/output
Tristate Output
C_SA2
(hi-Z)
GPIO1
Tristate Output
4mA
Input/output
Tristate Output
(hi-Z)
(hi-Z)
MODE
Input
Input
Input (floating)
INT_N
Open Drain
4mA
Open Drain
Tristate Output
Output (hi-Z)
Output
(hi-Z)
PD_N
Input
Input
Input (floating)
X1/CLK
Input (floating)
Crystal
Note: If
Oscillator
applicable,
Input CLK
external clock
Input
on X1/CLK pin
should be
removed
X2
Output (hi-Z)
Crystal
Oscillator
Output
X+
Tristate Output
Input/output Retain
(hi-Z)
Previous State
Y+
Tristate Output
Input/output Retain
(hi-Z)
Previous State
XTristate Output
Input/output Retain
(hi-Z)
Previous State
YTristate Output
Input/output Retain
(hi-Z)
Previous State
BACKLIG
Output
4mA
Output
Retain
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FT800 Embedded Video Engine Datasheet
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Pin
Name
HT
DE
VSYNC
HSYNC
DISP
PCLK
R(7:2),
G(7:2),
B(7:2)
Reset State
(VCC / VCCIO
ON)
Reset State
(VCC / VCCIO ON)
Default Output Drive
Strength
Active/Sta
ndby/Sleep
state (VCC
/ VCCIO
ON)
Output
Output
Output
Output
Output
Output
4mA
4mA
4mA
4mA
4mA
4mA
Output
Output
Output
Output
Output
Output
Clearance No.: BRT#001
Power down
state (VCC
ON / VCC1.2
OFF)
Hybrid Mode
(VCC OFF /
VCCIO ON)
Previous State
Output Low
Output Low
Output Low
Output Low
Output Low
Output Low
Table 4-16 Pin Status
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5 FT800 Memory Map
All memory and registers in the FT800 core are memory mapped in 22-bits address space with 2-bits
SPI/I2C command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 reserved
for Host Commands and 0'b11 undefined. The following are the memory space defined.
Start
Address
00 0000h
0C 0000h
End
Address
03 FFFFh
0C 0003h
Size
256 kB
4B
NAME
Description
RAM_G
ROM_CHIPID
Main graphics RAM
FT800 chip identification and revision
information:
Byte [0:1] Chip ID: “0800”
Byte [2:3] Version ID: “0100”
0B B23Ch
0F FFFBh
275 kB ROM_FONT
Font table and bitmap
0F FFFCh
0F FFFFh
4B
ROM_FONT_ADDR
Font table pointer address
10 0000h
10 1FFFh
8 kB
RAM_DL
Display List RAM
10 2000h
10 23FFh
1 kB
RAM_PAL
Palette RAM
10 2400h
10 257Fh
380 B
REG_*
Registers
10 8000 h
10 8FFFh
4 kB
RAM_CMD
Command buffer
1C 2000 h
1C 27FFh
2 kB
RAM_SCREENSHOT Screenshot readout buffer
Table 5-1 FT800 Memory Map
Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise
specified.
Note 2: The ROM_CHIPID utilizes a part of shadow address from ROM_FONT address space.
5.1 FT800 Registers
Table 5.1 shows the complete list of the FT800 registers. Refer to FT800 Series Programmers Guide ,
Chapter 2 for details of the register function.
Address
102400h
Register Name
REG_ID
Bits
Access
8
r/o
Reset
value
7Ch
102404h
REG_FRAMES
32
r/o
102408h
REG_CLOCK
32
r/o
10240Ch
REG_FREQUENCY
27
r/w
102410h
REG_RENDERMODE
1
r/w
000000
00h
000000
00h
02DC6C
00h
00h
102414h
102418h
10241Ch
REG_SNAPY
REG_SNAPSHOT
REG_CPURESET
9
1
1
r/w
r/o
r/w
00h
00h
102420h
REG_TAP_CRC
32
r/o
-
102424h
REG_TAP_MASK
32
r/w
102428h
10242Ch
102430h
102434h
102438h
10243Ch
102440h
102444h
102448h
REG_HCYCLE
REG_HOFFSET
REG_HSIZE
REG_HSYNC0
REG_HSYNC1
REG_VCYCLE
REG_VOFFSET
REG_VSIZE
REG_VSYNC0
10
10
10
10
10
10
10
10
10
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
FFFFFFF
Fh
224h
02Bh
1E0h
000h
029h
124h
00Ch
110h
000h
Copyright © Bridgetek Pte Ltd
Description
Identification register, always reads as
7Ch
Frame counter, since reset
Clock cycles, since reset
Main clock frequency
Rendering mode:
0 = normal, 1 = single-line
Scan line select for RENDERMODE 1
trigger for RENDERMODE 1
Graphics, audio and touch engines
reset control
Live video tape crc. Frame CRC is
computed every DL SWAP.
Live video tape mask
Horizontal total cycle count
Horizontal display start offset
Horizontal display pixel count
Horizontal sync fall offset
Horizontal sync rise offset
Vertical total cycle count
Vertical display start offset
Vertical display line count
Vertical sync fall offset
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FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Address
Register Name
10244Ch
102450h
102454h
102458h
10245Ch
102460h
102464h
102468h
REG_VSYNC1
REG_DLSWAP
REG_ROTATE
REG_OUTBITS
REG_DITHER
REG_SWIZZLE
REG_CSPREAD
REG_PCLK_POL
10
2
1
9
1
4
1
1
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Reset
value
00Ah
00h
00h
1B6h
1
00h
1
0
10246Ch
102470h
102474h
102478h
10247Ch
102480h
102484h
102488h
10248Ch
REG_PCLK
REG_TAG_X
REG_TAG_Y
REG_TAG
REG_VOL_PB
REG_VOL_SOUND
REG_SOUND
REG_PLAY
REG_GPIO_DIR
8
9
9
8
8
8
16
1
8
r/w
r/w
r/w
r/o
r/w
r/w
r/w
r/w
r/w
00h
000h
000h
00h
FFh
FFh
0000h
0h
80h
102490h
REG_GPIO
8
r/w
00h
102494h
102498h
10249Ch
1024A0h
1024A4h
1024A8h
Reserved
REG_INT_FLAGS
REG_INT_EN
REG_INT_MASK
REG_PLAYBACK_START
REG_PLAYBACK_LENGT
H
REG_PLAYBACK_READPT
R
REG_PLAYBACK_FREQ
8
1
8
20
20
r/o
r/w
r/w
r/w
r/w
00h
0h
FFh
00000h
00000h
20
r/o
-
16
r/w
1F40h
2
r/w
0h
1
1
14
r/w
r/o
r/w
0h
0h
00FAh
8
r/w
80h
000000
00h
000000
00h
-
1024ACh
1024B0h
1024B4h
Bits
Access
1024B8h
1024BCh
1024C0h
REG_PLAYBACK_FORMA
T
REG_PLAYBACK_LOOP
REG_PLAYBACK_PLAY
REG_PWM_HZ
1024C4h
REG_PWM_DUTY
1024C8h
REG_MACRO_0
32
r/w
1024CCh
REG_MACRO_1
32
r/w
1024D0h
–
1024E0h
1024E4h
1024E8h
1024ECh
1024F0h
1024F4h
Reserved
-
-
1024F8h
REG_CMD_READ
REG_CMD_WRITE
REG_CMD_DL
REG_TOUCH_MODE
REG_TOUCH_ADC_MOD
E
REG_TOUCH_CHARGE
1024FCh
REG_TOUCH_SETTLE
4
r/w
3h
102500h
REG_TOUCH_OVERSAMP
4
r/w
7h
Copyright © Bridgetek Pte Ltd
12
12
13
2
1
r/w
r/w
r/w
r/w
r/w
000h
000h
0000h
3h
1h
16
r/w
1770h
Clearance No.: BRT#001
Description
Vertical sync rise offset
Display list swap control
Screen 180 degree rotate
Output bit resolution, 3x3x3 bits
Output dither enable
Output RGB signal swizzle
Output clock spreading enable
PCLK polarity:
0 = output on PCLK rising edge,
1 = output on PCLK falling edge
PCLK frequency divider, 0 = disable
Tag query X coordinate
Tag query Y coordinate
Tag query result
Volume for playback
Volume for synthesizer sound
Sound effect select
Start effect playback
GPIO pin direction,
0 = input , 1 = output
GPIO pin value (bit 0,1,7);
output pin drive strength(bit 2-6)
Reserved
Interrupt flags, clear by read
Global interrupt enable
Interrupt enable mask
Audio playback RAM start address
Audio playback sample length (bytes)
Audio playback current read pointer
Audio playback sampling frequency
(Hz)
Audio playback format
Audio playback loop enable
Start audio playback
BACKLIGHT PWM output frequency
(Hz)
BACKLIGHT PWM output duty cycle
0=0%, 128=100%
Display list macro command 0
Display list macro command 1
Reserved
Command buffer read pointer
Command buffer write pointer
Command display list offset
Touch-screen sampling mode
Select single ended (low power) or
differential (accurate) sampling
Touch-screen charge time, units of 6
clocks
Touch-screen settle time, units of 6
clocks
Touch-screen oversample factor
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FT800 Embedded Video Engine Datasheet
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Address
102504h
102508h
10250Ch
102510h
102514h
102518h
10251Ch
102520h
102524h
102528h
10252Ch
102530h
102534h
–
102470h
102574h
102578h
109000h
Register Name
Bits
LE
REG_TOUCH_
RZTHRESH
REG_TOUCH_
RAW_XY
REG_TOUCH_RZ
REG_TOUCH_
SCREEN_XY
REG_TOUCH_
TAG_XY
REG_TOUCH_TAG
REG_TOUCH_TRANSFOR
M_A
REG_TOUCH_TRANSFOR
M_B
REG_TOUCH_TRANSFOR
M_C
REG_TOUCH_TRANSFOR
M_D
REG_TOUCH_TRANSFOR
M_E
REG_TOUCH_TRANSFOR
M_F
Reserved
REG_TOUCH_DIRECT_X
Y
REG_TOUCH_DIRECT_Z
1Z2
REG_TRACKER
Access
Reset
value
Clearance No.: BRT#001
Description
16
r/w
FFFFh
32
r/o
-
Touch-screen raw (x-MSB16; y-LSB16)
16
32
r/o
r/o
-
32
r/o
-
8
32
r/o
r/w
32
r/w
32
r/w
32
r/w
32
r/w
32
r/w
000100
00h
000000
00h
000000
00h
000000
00h
000100
00h
000000
00h
-
Touch-screen resistance
Touch-screen screen (x-MSB16; yLSB16)
Touch-screen screen (x-MSB16; yLSB16) used for tag lookup
Touch-screen tag result
Touch-screen transform coefficient
(s15.16)
Touch-screen transform coefficient
(s15.16)
Touch-screen transform coefficient
(s15.16)
Touch-screen transform coefficient
(s15.16)
Touch-screen transform coefficient
(s15.16)
Touch-screen transform coefficient
(s15.16)
Reserved
32
r/o
Touch-screen resistance threshold
-
Touch screen direct (x-MSB16; yLSB16) conversions
32 r/o
- Touch screen direct (z1-MSB16; z2LSB16) conversions
32 r/w
000000 Track register (Track value – MSB16;
00h Tag value - LSB8)
Table 5-2 Overview of FT800 Registers
Note: All register addresses are 4-byte aligned. The value in “Bits” column refers to the number of valid
bits from bit 0 unless otherwise specified; other bits are reserved.
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Document No.: BRT_000039
Clearance No.: BRT#001
6 Devices Characteristics and Ratings
6.1 Absolute Maximum Ratings
The absolute maximum ratings for the FT800 device are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the
device.
Parameter
Value
Unit
Storage Temperature
Floor Life (Out of Bag) At Factory Ambient
(30°C / 60% Relative Humidity)
-65 to +150
168
(IPC/JEDEC J-STD-033A MSL Level 3
Compliant)*
Ambient Temperature (Power Applied)
-40 to +85
VCC Supply Voltage
0 to +4
VCCIO Supply Voltage
0 to +4
DC Input Voltage
-0.5 to + (VCCIO + 0.3)
Table 6-1 Absolute Maximum Ratings
°C
Hours
°C
V
V
V
* If the devices are stored out of the packaging, beyond this time limit, the devices should be baked
before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.
6.2 DC Characteristics
(Ambient Temperature = -40°C to +85°C)
Parameter
Description
Minimum
Typical
Maximum
VCCIO
VCCIO operating
1.62
1.80
1.98
supply voltage
2.25
2.50
2.75
2.97
3.30
3.63
VCC
VCC operating supply
2.97
3.30
3.63
voltage
Icc1
Power Down current
1.0
Icc2
Sleep current
250
Icc3
Standby current
1.5
Icc4
Operating current
24
VCC1V2
Regulator Output
1.20
voltage
Table 6-2 Operating Voltage and Current
Parameter
Voh
Vol
Vih
Vil
Vth
Iin
Ioz
Description
Minimum
Typical
Maximum
Units
V
V
V
V
Conditions
Normal Operation
µA
µA
mA
mA
V
Power down mode
Sleep Mode
Standby Mode
Normal Operation
Normal Operation
Units
Normal Operation
Conditions
Output Voltage High 2.4
V
Ioh=4mA
Output Voltage Low
0.4
V
Iol=4mA
Input High Voltage
2.0
V
Input Low Voltage
0.8
V
Schmitt Hysteresis
0.3
0.45
0.5
V
Voltage
Input leakage
-10
10
uA
Vin = VCCIO or 0
current
Tristate output
-10
10
uA
Vin = VCCIO or 0
leakage current
Table 6-3 Digital I/O Pin Characteristics (VCC/VCCIO = +3.3V, Standard Drive Level)
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Parameter
Description
Minimum
Voh
Vol
Vih
Output Voltage High
Output Voltage Low
Input High Voltage
Vil
Input Low Voltage
VCCIO-0.4
0.7 X
VCCIO
-
Vth
Iin
Ioz
Typical
Maximum
Clearance No.: BRT#001
Units
Conditions
-
0.4
-
V
V
V
Ioh=4mA
Iol=4mA
-
-
0.3 X
VCCIO
0.5
V
-
Schmitt Hysteresis
0.28
0.39
V
Voltage
Input leakage
-10
10
uA
Vin = VCCIO or 0
current
Tristate output
-10
10
uA
Vin = VCCIO or 0
leakage current
Table 6-4 Digital I/O Pin Characteristics (VCCIO = +2.5V, Standard Drive Level)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Vol
Vih
Output Voltage High
Output Voltage Low
Input High Voltage
-
0.4
-
V
V
V
Ioh=4mA
Iol=4mA
-
Vil
Input Low Voltage
VCCIO-0.4
0.7 X
VCCIO
-
-
0.3 X
VCCIO
0.5
V
-
Vth
Iin
Ioz
Schmitt Hysteresis
0.25
0.35
V
Voltage
Input leakage
-10
10
uA
Vin = VCCIO or 0
current
Tristate output
-10
10
uA
Vin = VCCIO or 0
leakage current
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level)
6.3 Touch Sense Characteristics
Parameter
Rsw-on
Rsw-off
Rpu
Vth+
VthVhys
Rl
Description
Minimum
Typical
X-,X+,Y- and Y+
Drive On resistance
X-,X+,Y- and Y+
10M
Drive Off resistance
Touch sense pull up
72k
resistance
Touch Detection
1.53
rising-edge threshold
level
Touch Detection
1.17
falling-edge threshold
level
Touch Detection
0.36
Hysteresis
X-axis and Y-axis
200
drive load resistance
Table 6-6 Touch Sense
Description
ADC Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Minimum
Maximum
Units
5
10
Ω
-
-
Ω
100k
128k
Ω
1.7
1.87
V
1.3
-1.47
V
0.39
0.4
V
-
-
Ω
Conditions
Characteristics (VCC=3.3V)
Typical
Maximum
Units
Conditions
10
bits
+/-1
LSB
+/-0.5
LSB
+/-2
LSB
Table 6-7 ADC Characteristics (VCC=3.3V)
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Clearance No.: BRT#001
6.4 AC Characteristics
6.4.1
System clock
Parameter
Value
Typical
Minimum
Unit
Maximum
Crystal
Frequency
12.000
MHz
X1/X2
5
10
pF
Capacitance
External clock input
Frequency
12.000
MHz
Duty cycle
45
50
55
%
Input voltage on
3.3
Vp-p
X1/CLKIN
Table 6-8 System clock characteristics (Ambient Temperature = -40°C to +85°C)
6.4.2
Host Interface SPI Mode 0
Figure 6-1 SPI Interface Timing
Parameter
Fsclk
Tsclk
Tsclkl
Tsclkh
Tsac
Tisu
Tih
Tzo
Toz
Description
SPI Clock
frequency
SPI clock period
SPI clock low
duration
SPI clock high
duration
SPI access time
Input Setup
Input Hold
Output enable
delay
Output disable
delay
Copyright © Bridgetek Pte Ltd
VCC(I/O)=1.8
VCC(I/O)=2.5
VCC(I/O)=3.3
V
V
V
Unit
Min
Max
Min
Max
Min
Max
0
25
0
30
0
30
Mhz
40
16
-
33
13
-
33
13
-
ns
ns
16
-
13
-
13
-
ns
10
5
10
5
10
10
5
10
5
10
10
5
10
5
10
ns
ns
ns
ns
5
10
5
10
5
10
ns
35
FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Tosu
Tod
Tcsnh
6.4.3
Output setup time
Tsclkl-5
Tsclkl-5
Tsclkl-5
Output data delay
5
10
5
10
5
CSN hold time
15
15
15
Table 6-9 SPI Interface Timing Specification
Parameter
Tscll
Tsclh
Tsu
Thd
Tr
Tf
6.4.4
Description
I2C SCL clock
frequency
clock low period
clock high
period
Data setup time
Data hold time
Rise time
Fall time
Fast-mode
mode
Fast-plus
High speed
mode
mode
Th
Tvsu
Tvhd
Thsu
Thhd
Tdsu
Tdhd
Tesu
Tehd
Unit
Min
Max
Min
Max
Min
Max
Min
Max
0
100
0
400
0
1000
0
3400
kHz
4.7
4.0
-
1.3
0.6
-
0.5
0.26
-
0.16
0.06
-
µs
µs
120
120
10
0
10
10
70
40
40
ns
ns
ns
ns
250
100
50
0
0
0
1000 300
300
300
Table 6-10 I2C Interface Timing
Description
VCC=3.3V
Min
Tvwh
ns
ns
ns
RGB Video Timing
Parameter
Tpclk
Tpclkdc
Thc
Thwh
10
-
Host Interface I2C Mode Timing
Standard-
Fscl
Clearance No.: BRT#001
Typ
Pixel Clock period
78
104
Pixel Clock duty cycle
40
Hsync to Clock
30
HSYNC width
1
41
(REG_HSYNC1-REG_HSYNC0)
VSYNC width
1
10
(REG_VSYNC1-REG_VSYNC0)
HSYNC Cycle
525
(REG_HCYCLE)
VSYNC setup
30
VSYNC hold
10
HSYNC setup
30
HSYNC hold
10
DATA setup
20
DATA hold
10
DE setup
30
DE hold
10
Table 6-11 RGB Video timing characteristics
Copyright © Bridgetek Pte Ltd
Unit
Max
60
-
ns
%
ns
Tpclk
-
Th
-
Tpclk
-
ns
ns
ns
ns
ns
ns
ns
ns
36
FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Clearance No.: BRT#001
Figure 6-2 RGB Video Signal Timing
Copyright © Bridgetek Pte Ltd
37
FT800 Embedded Video Engine Datasheet
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Clearance No.: BRT#001
7 Application Examples
7.1 Examples of LCD Interface connection
Figure 7-1 FT800 Reference Design Schematic (LCD)
7.2 Examples of PWM Audio Circuits
Figure 7-2 FT800 Reference Design Schematic (audio)
Copyright © Bridgetek Pte Ltd
38
FT800 Embedded Video Engine Datasheet
Version 1.4
Document No.: BRT_000039
Clearance No.: BRT#001
8 Package Parameters
The FT800 is available in VQFN-48 package. The solder reflow profile for all packages is described in
following sections.
8.1 VQFN-48 Package Dimensions
8.1.1 Top Side
Notes:
1.
2.
3.
4.
YYWW = Date Code, where YY is year and WW is week number
Pre-date code 1727 company logo was FTDI
Marking alignment should be centre justified
Laser Marking should be used
8.1.2 Bottom Side
No markings should be placed on the bottom side.
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Document No.: BRT_000039
Clearance No.: BRT#001
8.2 VQFN-48 Package Dimensions
Figure 8-1 VQFN-48 Package Dimensions
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Document No.: BRT_000039
Clearance No.: BRT#001
8.3 Solder Reflow Profile
The FT800 is supplied in a Pb free VQFN-48 package. The recommended solder reflow profile for the
package is shown in Figure 8-2.
Temperature, T (Degrees C)
tp
Tp
Critical Zone: when
T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25º C to TP
Time, t (seconds)
Figure 8-2 FT800 Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Table 8-1. Values are shown for
both a completely Pb free solder process (i.e. the FT800 is used with Pb free solder), and for a non-Pb
free solder process (i.e. the FT800 is used with non-Pb free solder).
Profile Feature
Pb Free Solder
Non-Pb Free Solder Process
Process
Average Ramp Up Rate (Ts to Tp)
3°C / second Max.
3°C / Second Max.
Preheat
- Temperature Min (Ts Min.)
150°C
- Temperature Max (Ts Max.)
200°C
- Time (ts Min to ts Max)
60 to 120 seconds
100°C
150°C
60 to 120 seconds
Time Maintained Above Critical
Temperature TL:
217°C
- Temperature (TL)
60 to 150 seconds
183°C 60 to 150 seconds
- Time (tL)
Peak Temperature (Tp)
260°C
240°C
Time within 5°C of actual Peak
20 to 40 seconds
20 to 40 seconds
6°C / second Max.
6°C / second Max.
8 minutes Max.
6 minutes Max.
Temperature (tp)
Ramp Down Rate
Time for T= 25°C to Peak Temperature,
Tp
Table 8-1 Reflow Profile Parameter Values
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Clearance No.: BRT#001
9 Contact Information
Head Quarters – Singapore
Branch Office – Taipei, Taiwan
Bridgetek Pte Ltd
178 Paya Lebar Road, #07-03
Singapore 409030
Tel: +65 6547 4827
Fax: +65 6841 6071
Bridgetek Pte Ltd, Taiwan Branch
2 Floor, No. 516, Sec. 1, Nei Hu Road, Nei Hu District
Taipei 114
Taiwan, R.O.C.
Tel: +886 (2) 8797 5691
Fax: +886 (2) 8751 9737
E-mail (Sales)
E-mail (Support)
E-mail (Sales)
E-mail (Support)
sales.apac@brtchip.com
support.apac@brtchip.com
sales.apac@brtchip.com
support.apac@brtchip.com
Branch Office - Glasgow, United Kingdom
Branch Office – Vietnam
Bridgetek Pte. Ltd.
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
Bridgetek VietNam Company Limited
Lutaco Tower Building, 5th Floor, 173A Nguyen Van
Troi,
Ward 11, Phu Nhuan District,
Ho Chi Minh City, Vietnam
Tel : 08 38453222
Fax : 08 38455222
E-mail (Sales)
E-mail (Support)
E-mail (Sales)
E-mail (Support)
sales.emea@brtichip.com
support.emea@brtchip.com
sales.apac@brtchip.com
support.apac@brtchip.com
Web Site
http://brtchip.com/
Distributor and Sales Representatives
Please visit the Sales Network page of the Bridgetek Web site for the contact details of our distributor(s) and sales
representative(s) in your country.
System and equipment manufacturers and designers are responsible to ensure that their systems, and any Bridgetek Pte Ltd (BRT
Chip) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All
application-related information in this document (including application descriptions, suggested Bridgetek devices and other materials) is
provided for reference only. While Bridgetek has taken care to assure it is accurate, this information is subject to customer
confirmation, and Bridgetek disclaims all liability for system designs and for any applications assistance provided by Bridgetek. Use of
Bridgetek devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and
hold harmless Bridgetek from any and all damages, claims, suits or expense resulting from such use. This document is subject to
change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of t his document.
Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. Bridgetek Pte Ltd, 178 Paya
Lebar Road, #07-03, Singapore 409030. Singapore Registered Company Number: 201542387H.
Copyright © Bridgetek Pte Ltd
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FT800 Embedded Video Engine Datasheet
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Document No.: BRT_000039
Clearance No.: BRT#001
Appendix A – References
Document References
FT800 Series Programmers Guide
AN_240 FT800 From the Ground Up
AN_245 Sample Application Introduction for VM800B & VM800C Development Kits & Windows PC
AN_246 VM800 Series ‘Sample App’
AN_252 FT800 Audio Primer
AN_299 FT800_FT801 Internal Clock Trimming
Acronyms and Abbreviations
Terms
Description
ADPCM
Adaptive Differential Pulse Code Modulation
ASCII
American Standard Code for Information Interchange
EVE
Embedded Video Engine
HMI
Human Machine Interfaces
I2C
Inter-Integrated Circuit
LCD
Liquid Crystal Display
LED
Light Emitting Diode
MCU
Micro Controller Unit
MPU
Micro Processor Unit
PCM
Pulse Code Modulation
PLL
Phased Locked Loop
PWM
Pulse Width Modulation
QVGA
Quarter Video Graphics Array
ROM
SPI
VQFN
Read Only Memory
Serial Peripheral Interface
Very Thin Quad Flat Non-Leaded Package
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FT800 Embedded Video Engine Datasheet
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Appendix B - List of Figures and Tables
List of Figures
Figure 2-1 FT800 Block Diagram ..................................................................................................... 3
Figure 2-2 FT800 System Design Diagram ....................................................................................... 3
Figure 3-1 Pin Configuration VQFN-48 (top view) .............................................................................. 6
Figure 4-1 Host Interface Options ................................................................................................. 10
Figure 4-2 SPI Interface 1.8-3.3V connection ................................................................................. 11
Figure 4-3 SPI Interface 5V connection .......................................................................................... 11
Figure 4-4 Internal Relaxation Oscillator Connection ....................................................................... 15
Figure 4-5 Crystal oscillator connection ......................................................................................... 15
Figure 4-6 External clock input ..................................................................................................... 15
Figure 4-7 Touch screen connection .............................................................................................. 25
Figure 4-8 1.2V regulator ............................................................................................................ 26
Figure 4-9 Power State Transition ................................................................................................. 27
Figure 6-1 SPI Interface Timing .................................................................................................... 35
Figure 6-2 RGB Video Signal Timing .............................................................................................. 37
Figure 7-1 FT800 Reference Design Schematic (LCD) ...................................................................... 38
Figure 7-2 FT800 Reference Design Schematic (audio) .................................................................... 38
Figure 8-1 VQFN-48 Package Dimensions ...................................................................................... 40
Figure 8-2 FT800 Solder Reflow Profile .......................................................................................... 41
List of Tables
Table 3-1 FT800Q pin description.................................................................................................... 9
Table 4-1 Host memory read transaction (SPI) ............................................................................... 12
Table 4-2 Host memory write transaction (SPI) .............................................................................. 13
Table 4-3 Host command transaction (SPI) .................................................................................... 13
Table 4-4 Host Command Table .................................................................................................... 14
Table 4-5 Interrupt Flags bit assignment ....................................................................................... 14
Table 4-6 Font table format ......................................................................................................... 17
Table 4-7 ROM font table ............................................................................................................. 17
Table 4-8 ROM font ASCII character width in pixels ......................................................................... 20
Table 4-9 ROM font Extended ASCII characters .............................................................................. 20
Table 4-10 REG_SWIZZLE RGB Pins Mapping ................................................................................. 21
Table 4-11 Output drive current selection ...................................................................................... 22
Table 4-12 Sound Effect .............................................................................................................. 23
Table 4-13 MIDI Note Effect ......................................................................................................... 24
Table 4-14 Touch Controller Operating Mode .................................................................................. 25
Table 4-15 Power supply ............................................................................................................. 26
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FT800 Embedded Video Engine Datasheet
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Clearance No.: BRT#001
Table 4-16 Pin Status .................................................................................................................. 29
Table 5-1 FT800 Memory Map ...................................................................................................... 30
Table 5-2 Overview of FT800 Registers .......................................................................................... 32
Table 6-1 Absolute Maximum Ratings ............................................................................................ 33
Table 6-2 Operating Voltage and Current ....................................................................................... 33
Table 6-3 Digital I/O Pin Characteristics (VCC/VCCIO = +3.3V, Standard Drive Level) ......................... 33
Table 6-4 Digital I/O Pin Characteristics (VCCIO = +2.5V, Standard Drive Level) ................................ 34
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) ................................ 34
Table 6-6 Touch Sense Characteristics (VCC=3.3V) ........................................................................ 34
Table 6-7 ADC Characteristics (VCC=3.3V) .................................................................................... 34
Table 6-8 System clock characteristics (Ambient Temperature = -40°C to +85°C) .............................. 35
Table 6-9 SPI Interface Timing Specification .................................................................................. 36
Table 6-10 I2C Interface Timing ................................................................................................... 36
Table 6-11 RGB Video timing characteristics .................................................................................. 36
Table 8-1 Reflow Profile Parameter Values ..................................................................................... 41
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FT800 Embedded Video Engine Datasheet
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Document No.: BRT_000039
Clearance No.: BRT#001
Appendix C - Revision History
Document Title:
FT800 Embedded Video Engine Datasheet
Document Reference No.:
BRT_000039
Clearance No.:
BRT#001
Product Page:
http://brtchip.com/product
Document Feedback:
Send Feedback
Revision
Changes
Date
Version 1.0
Initial Release
2013-07-18
Version 1.1
Updated Release
2013-08-28
Version 1.2
Version 1.3
Version 1.4
Copyright © Bridgetek Pte Ltd
Dual branding to reflect the migration of
the product to the Bridgetek name –
logo changed, copyright changed,
contact information changed
Document Migrated from Dual branding
(FTDI/BRT) to Bridgetek – Dual
branding logo replaced with BRT Logo;
All document reference hyperlinks
updated to point BRT wesbite as
required; Updated the chip markings
from FTDI to BRT in Figure 3-1 Pin
Configuration VQFN-48 (top view)
Updated section 1.1 Packaging
Quantities
Updated Figure 8.1
2106-09-13
2017-06-30
2019-04-24
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