74HC4052M/TR

74HC4052/ 74HCT4052 Dual 4-channel analog multiplexer/demultiplexer 1. General description The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A. The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1. VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E). The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the 74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). 2. Features „ Wide analog input voltage range from −5 V to +5 V „ Low ON resistance: 80 Ω (typical) at VCC − VEE = 4.5 V 70 Ω (typical) at VCC − VEE = 6.0 V 60 Ω (typical) at VCC − VEE = 9.0 V „ Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals „ Typical ‘break before make’ built-in „ Complies with JEDEC standard no. 7A „ ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V „ Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Applications „ Analog multiplexing and demultiplexing „ Digital multiplexing and demultiplexing „ Signal gating http://www.hgsemi.com.cn 1 2018 AUG 74HC4052/ 74HCT4052 4. Functional diagram 13 1Z 1Y0 12 10 S0 1Y1 14 9 S1 1Y2 15 6 E 1Y3 11 2Y0 1 2Y1 5 2Y2 2 2Y3 4 10 0 9 1 6 G4 4× 0 3 MDX 3 0 1 1 5 2 2 3 4 12 14 13 15 2Z 11 001aah824 3 Fig 1. Logic symbol 001aah825 Fig 2. IEC logic symbol nYn VEE VCC VCC VCC VCC VEE from logic VEE nZ mnb043 Fig 3. Schematic diagram (one switch) http://www.hgsemi.com.cn 2 2018 AUG 74HC4052/ 74HCT4052 VDD 16 13 12 14 15 S0 10 11 S1 E 9 LOGIC LEVEL CONVERSION 1Y0 1Y1 1Y2 1Y3 1-OF-4 DECODER 1 2Y0 6 5 2 4 3 Fig 4. 1Z 8 7 VSS VEE 2Y1 2Y2 2Y3 2Z 001aah872 Functional diagram http://www.hgsemi.com.cn 3 2018 AUG 74HC4052/ 74HCT4052 5. Pinning information 5.1 Pinning 74HC4052 74HCT4052 terminal 1 index area 1 16 VCC 2Y2 2 15 1Y2 2Z 3 14 1Y1 2Y3 4 13 1Z 2Y1 5 12 1Y0 2Y1 5 E 6 VEE 7 3 14 1Y1 4 13 1Z 10 S0 9 S1 12 1Y0 VCC (1) 11 1Y3 10 S0 9 8 2Z 2Y3 S1 GND 15 1Y2 8 7 2 11 1Y3 6 VEE 2Y2 GND E 1 2Y0 16 VCC 2Y0 74HC4052 74HCT4052 001aah823 Transparent top view 001aah822 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration for DIP16, SO16 and (T)SSOP16 Fig 6. Pin configuration for DHVQFN16 5.2 Pin description Table 2. Symbol Pin description Pin Description 2Y0 1 independent input or output 2Y0 2Y2 2 independent input or output 2Y2 2Z 3 common input or output 2 2Y3 4 independent input or output 2Y3 2Y1 5 independent input or output 2Y1 E 6 enable input (active LOW) VEE 7 negative supply voltage GND 8 ground (0 V) S1 9 select logic input 1 S0 10 select logic input 0 1Y3 11 independent input or output 1Y3 1Y0 12 independent input or output 1Y0 1Z 13 common input or output 1 1Y1 14 independent input or output 1Y1 1Y2 15 independent input or output 1Y2 VCC 16 positive supply voltage http://www.hgsemi.com.cn 4 2018 AUG 74HC4052/ 74HCT4052 6. Functional description 6.1 Function table Table 3. Function table[1] Channel on Input E S1 S0 L L L nY0 and nZ L L H nY1 and nZ L H L nY2 and nZ L H H nY3 and nZ H X X none [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VEE = GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +11.0 V IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA ISK switch clamping current VSW < −0.5 V or VSW > VCC + 0.5 V - ±20 mA ISW switch current −0.5 V < VSW < VCC + 0.5 V - ±25 mA [1] IEE supply current - ±20 mA ICC supply current - 50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C - 500 mW - 100 mW Ptot total power dissipation Tamb = −40 °C to +125 °C P power dissipation per switch [1] [2] [2] To avoid drawing VCC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no VCC current will flow out of pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed VCC or VEE. For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. http://www.hgsemi.com.cn 5 2018 AUG 74HC4052/ 74HCT4052 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions supply voltage 74HC4052 74HCT4052 Unit Min Typ Max Min Typ Max VCC − GND 2.0 5.0 10.0 4.5 5.0 5.5 V VCC − VEE 2.0 5.0 10.0 2.0 5.0 10.0 V see Figure 7 and Figure 8 VI input voltage GND - VCC GND - VCC V VSW switch voltage VEE - VCC VEE - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - 1.67 625 - 1.67 139 ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - 1.67 83 - 1.67 139 ns/V VCC = 10.0 V - 1.67 31 - 1.67 139 ns/V mnb044 12 mnb045 12 VCC − GND (V) 10 VCC − GND (V) 8 8 operating area 6 operating area 4 4 2 0 0 4 8 0 12 0 VCC − VEE (V) Fig 7. Guaranteed operating area as a function of the supply voltages for 74HC4052 http://www.hgsemi.com.cn Fig 8. 6 4 8 VCC − VEE (V) 12 Guaranteed operating area as a function of the supply voltages for 74HCT4052 2018 AUG 74HC4052/ 74HCT4052 9. Static characteristics Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4052: VCC − GND or VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4052: VCC − GND = 4.5 V and 5.5 V, VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter Tamb = −40 °C to +85 Conditions RON(peak) ON resistance (peak) Typ Max Unit - - - Ω - 100 225 Ω Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA [2] VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA RON(rail) Min °C[1] ON resistance (rail) VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - 90 200 Ω VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - 70 165 Ω - 150 - Ω Vis = VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA [2] VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - 80 175 Ω VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - 70 150 Ω VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - 60 130 Ω Vis = VCC ΔRON ON resistance mismatch between channels VCC = 2.0 V; VEE = 0 V; ISW = 100 μA - 150 - Ω VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - 90 200 Ω VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - 80 175 Ω VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - 65 150 Ω - - - Ω VCC = 4.5 V; VEE = 0 V - 9 - Ω VCC = 6.0 V; VEE = 0 V - 8 - Ω VCC = 4.5 V; VEE = −4.5 V - 6 - Ω - - - Ω Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V [2] Tamb = −40 °C to +125 °C RON(peak) ON resistance (peak) Vis = VCC to VEE VCC = 2.0 V; VEE = 0 V; ISW = 100 μA http://www.hgsemi.com.cn [2] VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - - 270 Ω VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - - 240 Ω VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - - 195 Ω 7 2018 AUG 74HC4052/ 74HCT4052 Table 6. RON resistance per switch for 74HC4052 and 74HCT4052 …continued VI = VIH or VIL; for test circuit see Figure 9. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. For 74HC4052: VCC − GND or VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. For 74HCT4052: VCC − GND = 4.5 V and 5.5 V, VCC − VEE = 2.0 V, 4.5 V, 6.0 V and 9.0 V. Symbol Parameter Conditions RON(rail) ON resistance (rail) Vis = VEE Min VCC = 2.0 V; VEE = 0 V; ISW = 100 μA Typ Max Unit - - - Ω VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - - 210 Ω VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - - 180 Ω VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - - 160 Ω - - - Ω VCC = 4.5 V; VEE = 0 V; ISW = 1 000 μA - - 240 Ω VCC = 6.0 V; VEE = 0 V; ISW = 1 000 μA - - 210 Ω VCC = 4.5 V; VEE = −4.5 V; ISW = 1 000 μA - - 180 Ω [2] Vis = VCC VCC = 2.0 V; VEE = 0 V; ISW = 100 μA [2] [1] All typical values are measured at Tamb = 25 °C. [2] When supply voltages (VCC − VEE) near 2.0 V the analog switch ON resistance becomes extremely non-linear. When using a supply of 2 V, it is recommended to use these devices only for transmitting digital signals. 001aai068 100 (1) RON (Ω) 80 60 (2) Vsw V (3) 40 VCC Sn from select input nYn Vis 20 nZ GND VEE Isw 0 0 1.8 3.6 5.4 7.2 9.0 Vis (V) 001aah826 Vis = 0 V to (VCC − VEE). Vis = 0 V to (VCC − VEE). (1) VCC = 4.5 V V sw R ON = --------I sw (2) VCC = 6 V (3) VCC = 9 V Fig 9. Test circuit for measuring RON http://www.hgsemi.com.cn Fig 10. Typical RON as a function of input voltage Vis 8 2018 AUG 74HC4052/ 74HCT4052 Table 7. Static characteristics for 74HC4052 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 9.0 V 6.3 4.7 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V VCC = 9.0 V - 4.3 2.7 V VCC = 6.0 V - - ±1.0 μA VCC = 10.0 V - - ±2.0 μA per channel - - ±1.0 μA all channels - - ±2.0 μA - - ±2.0 μA VCC = 6.0 V - - 80.0 μA VCC = 10.0 V - - 160.0 μA - 3.5 - pF Tamb = −40 °C to +85 °C[1] VIH VIL HIGH-level input voltage LOW-level input voltage input leakage current II IS(OFF) OFF-state leakage current VEE = 0 V; VI = VCC or GND VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 IS(ON) ON-state leakage current VI = VIH or VIL; |VSW| = VCC − VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE CI input capacitance Csw switch capacitance independent pins nYn - 5 - pF common pins nZ - 12 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 9.0 V 6.3 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VCC = 9.0 V - - 2.7 V VCC = 6.0 V - - ±1.0 μA VCC = 10.0 V - - ±2.0 μA Tamb = −40 °C to +125 °C VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current http://www.hgsemi.com.cn VEE = 0 V; VI = VCC or GND 9 2018 AUG 74HC4052/ 74HCT4052 Table 7. Static characteristics for 74HC4052 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 Min Typ Max Unit per channel - - ±1.0 μA all channels - - ±2.0 μA - - ±2.0 μA VCC = 6.0 V - - 160.0 μA VCC = 10.0 V - - 320.0 μA Conditions Min Typ Max Unit IS(ON) ON-state leakage current VI = VIH or VIL; |VSW| = VCC − VEE; VCC = 10.0 V; VEE = 0 V; see Figure 12 ICC supply current VEE = 0 V; VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE [1] All typical values are measured at Tamb = 25 °C. Table 8. Static characteristics for 74HCT4052 Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Tamb = −40 °C to +85 °C[1] VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V II input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - ±1.0 μA IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 per channel - - ±1.0 μA all channels - - ±2.0 μA - - ±2.0 μA VCC = 5.5 V; VEE = 0 V - - 80.0 μA VCC = 5.0 V; VEE = −5.0 V - - 160.0 μA per input; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V - 45 202.5 μA - 3.5 - pF independent pins nYn - 5 - pF common pins nZ - 12 - pF VCC = 4.5 V to 5.5 V 2.0 - - V IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ΔICC additional supply current CI input capacitance Csw switch capacitance Tamb = −40 °C to +125 °C VIH HIGH-level input voltage http://www.hgsemi.com.cn 10 2018 AUG 74HC4052/ 74HCT4052 Table 8. Static characteristics for 74HCT4052 …continued Voltages are referenced to GND (ground = 0 V). Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V ILI input leakage current VI = VCC or GND; VCC = 5.5 V; VEE = 0 V - - ±1.0 μA IS(OFF) OFF-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 11 per channel - - ±1.0 μA all channels - - ±2.0 μA - - ±2.0 μA VCC = 5.5 V; VEE = 0 V - - 160.0 μA VCC = 5.0 V; VEE = −5.0 V - - 320.0 μA - - 220.5 μA IS(ON) ON-state leakage current VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL; |VSW| = VCC − VEE; see Figure 12 ICC supply current VI = VCC or GND; Vis = VEE or VCC; Vos = VCC or VEE ΔICC [1] additional supply current per input; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V All typical values are measured at Tamb = 25 °C. VCC Sn from select input Isw A Isw nYn nZ GND Vis A VEE Vos 001aah827 Vis = VCC and Vos = VEE. Vis = VEE and Vos = VCC. Fig 11. Test circuit for measuring OFF-state current VCC HIGH from select input Sn Isw A nYn nZ GND Vis Vos VEE 001aah828 Vis = VCC and Vos = open-circuit. Vis = VEE and Vos = open-circuit. Fig 12. Test circuit for measuring ON-state current http://www.hgsemi.com.cn 11 2018 AUG 74HC4052/ 74HCT4052 10. Dynamic characteristics Table 9. Dynamic characteristics for 74HC4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V; VEE = 0 V - 14 75 ns VCC = 4.5 V; VEE = 0 V - 5 15 ns VCC = 6.0 V; VEE = 0 V - 4 13 ns - 4 10 ns VCC = 2.0 V; VEE = 0 V - 105 405 ns VCC = 4.5 V; VEE = 0 V - 38 81 ns VCC = 6.0 V; VEE = 0 V - 30 69 ns - 26 58 ns VCC = 2.0 V; VEE = 0 V - 74 315 ns VCC = 4.5 V; VEE = 0 V - 27 63 ns VCC = 6.0 V; VEE = 0 V - 22 54 ns VCC = 4.5 V; VEE = −4.5 V - 22 48 ns - 57 - pF VCC = 2.0 V; VEE = 0 V - - 90 ns VCC = 4.5 V; VEE = 0 V - - 18 ns VCC = 6.0 V; VEE = 0 V - - 15 ns VCC = 4.5 V; VEE = −4.5 V - - 12 ns VCC = 2.0 V; VEE = 0 V - - 490 ns VCC = 4.5 V; VEE = 0 V - - 98 ns VCC = 6.0 V; VEE = 0 V - - 83 ns VCC = 4.5 V; VEE = −4.5 V - - 69 ns Tamb = −40 °C to +85 °C[1] tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 [2] VCC = 4.5 V; VEE = −4.5 V ton turn-on time E, Sn to Vos; RL = ∞ Ω; see Figure 14 [3] VCC = 4.5 V; VEE = −4.5 V toff CPD turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [4] [5] power dissipation per switch; VI = GND to VCC capacitance Tamb = −40 °C to +125 °C tpd ton propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 turn-on time http://www.hgsemi.com.cn E, Sn to Vos; RL = ∞ Ω; see Figure 14 12 [2] [3] 2018 AUG 74HC4052/ 74HCT4052 Table 9. Dynamic characteristics for 74HC4052 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol toff Parameter turn-off time Conditions Min Typ Max Unit VCC = 2.0 V; VEE = 0 V - - 375 ns VCC = 4.5 V; VEE = 0 V - - 75 ns VCC = 6.0 V; VEE = 0 V - - 64 ns VCC = 4.5 V; VEE = −4.5 V - - 57 ns Min Typ Max Unit - 5 15 ns - 4 10 ns VCC = 4.5 V; VEE = 0 V - 41 88 ns VCC = 4.5 V; VEE = −4.5 V - 28 60 ns - 26 63 ns E, Sn to Vos; RL = 1 kΩ; see Figure 14 [1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPHL and tPLH. [3] ton is the same as tPZH and tPZL. [4] toff is the same as tPHZ and tPLZ. [5] [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; Σ{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Table 10. Dynamic characteristics for 74HCT4052 GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Tamb = −40 °C to +85 tpd Conditions °C[1] propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 [2] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V ton toff turn-on time turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 E, Sn to Vos; RL = 1 kΩ; see Figure 14 [3] [4] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V CPD - 21 48 ns - 57 - pF VCC = 4.5 V; VEE = 0 V - - 18 ns VCC = 4.5 V; VEE = −4.5 V - - 12 ns power dissipation per switch; VI = GND to VCC − 1.5 V capacitance [5] Tamb = −40 °C to +125 °C tpd propagation delay Vis to Vos; RL = ∞ Ω; see Figure 13 http://www.hgsemi.com.cn 13 [2] 2018 AUG 74HC4052/ 74HCT4052 Table 10. Dynamic characteristics for 74HCT4052 …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; for test circuit see Figure 15. Vis is the input voltage at a nYn or nZ terminal, whichever is assigned as an input. Vos is the output voltage at a nYn or nZ terminal, whichever is assigned as an output. Symbol Parameter Conditions ton turn-on time E, Sn to Vos; RL = 1 kΩ; see Figure 14 Min Typ Max Unit - - 105 ns - - 72 ns VCC = 4.5 V; VEE = 0 V - - 75 ns VCC = 4.5 V; VEE = −4.5 V - - 57 ns [3] VCC = 4.5 V; VEE = 0 V VCC = 4.5 V; VEE = −4.5 V toff turn-off time E, Sn to Vos; RL = 1 kΩ; see Figure 14 [1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPHL and tPLH. [3] ton is the same as tPZH and tPZL. [4] toff is the same as tPHZ and tPLZ. [5] [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ{(CL + Csw) × VCC2 × fo} where: fi = input frequency in MHz; fo = output frequency in MHz; N = number of inputs switching; Σ{(CL + Csw) × VCC2 × fo} = sum of outputs; CL = output load capacitance in pF; Csw = switch capacitance in pF; VCC = supply voltage in V. Vis input 50 % tPLH Vos output tPHL 50 % 001aad555 Fig 13. Input (Vis) to output (Vos) propagation delays http://www.hgsemi.com.cn 14 2018 AUG 74HC4052/ 74HCT4052 VI VM E, Sn inputs 0V tPZL tPLZ 50 % Vos output 10 % tPHZ tPZH 90 % 50 % Vos output switch ON switch ON switch OFF 001aae330 For 74HC4052: VM = 0.5 × VCC. For 74HCT4052: VM = 1.3 V. Fig 14. Turn-on and turn-off times VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC Vis PULSE GENERATOR VI VCC Vos RL S1 open DUT RT CL GND VEE 001aae382 Definitions for test circuit; see Table 11: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = Test selection switch. Fig 15. Test circuit for measuring AC performance http://www.hgsemi.com.cn 15 2018 AUG 74HC4052/ 74HCT4052 Table 11. Test data Test Input VI tPHL, tPLH [2] tPZH, tPHZ [2] tPZL, tPLZ [2] Load Vis tr, tf S1 position CL RL at fmax other[1] pulse < 2 ns 6 ns 50 pF 1 kΩ open VCC < 2 ns 6 ns 50 pF 1 kΩ VEE VEE < 2 ns 6 ns 50 pF 1 kΩ VCC [1] tr = tf = 6 ns; when measuring fmax, there is no constraint to tr and tf with 50 % duty factor. [2] VI values: a) For 74HC4052: VI = VCC b) For 74HCT4052: VI = 3 V 11. Additional dynamic characteristics Table 12. Additional dynamic characteristics Recommended conditions and typical values; GND = 0 V; Tamb = 25 °C; CL = 50 pF. Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input. Vos is the output voltage at pins nYn or nZ, whichever is assigned as an output. Symbol Parameter Conditions Min Typ Max Unit dsin sine-wave distortion fi = 1 kHz; RL = 10 kΩ; see Figure 16 Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = −2.25 V - 0.04 - % Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V - 0.02 - % Vis = 4.0 V (p-p); VCC = 2.25 V; VEE = −2.25 V - 0.12 - % Vis = 8.0 V (p-p); VCC = 4.5 V; VEE = −4.5 V - 0.06 - % fi = 10 kHz; RL = 10 kΩ; see Figure 16 αiso isolation (OFF-state) Xtalk crosstalk crosstalk voltage Vct f(−3dB) −3 dB frequency response RL = 600 Ω; fi = 1 MHz; see Figure 17 VCC = 2.25 V; VEE = −2.25 V [1] - −50 - dB VCC = 4.5 V; VEE = −4.5 V [1] - −50 - dB VCC = 2.25 V; VEE = −2.25 V [1] - −60 - dB VCC = 4.5 V; VEE = −4.5 V [1] - −60 - dB VCC = 4.5 V; VEE = 0 V - 110 - mV VCC = 4.5 V; VEE = −4.5 V - 220 - mV between two switches/multiplexers; RL = 600 Ω; fi = 1 MHz; see Figure 18 peak-to-peak value; between control and any switch; RL = 600 Ω; fi = 1 MHz; E or Sn square wave between VCC and GND; tr = tf = 6 ns; see Figure 19 RL = 50 Ω; see Figure 20 VCC = 2.25 V; VEE = −2.25 V [2] - 170 - MHz VCC = 4.5 V; VEE = −4.5 V [2] - 180 - MHz [1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω). [2] Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω). http://www.hgsemi.com.cn 16 2018 AUG 74HC4052/ 74HCT4052 VCC Sn 10 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah829 Fig 16. Test circuit for measuring sine-wave distortion VCC Sn 0.1 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah871 VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ. a. Test circuit 001aae332 0 αiso (dB) −20 −40 −60 −80 −100 10 102 103 104 105 106 fi (kHz) b. Isolation (OFF-state) as a function of frequency Fig 17. Test circuit for measuring isolation (OFF-state) http://www.hgsemi.com.cn 17 2018 AUG 74HC4052/ 74HCT4052 VCC Sn 0.1 μF Vis RL nYn/nZ nZ/nYn VEE GND RL CL VCC Sn nYn/nZ nZ/nYn VEE RL GND RL Vos CL dB 001aah873 Fig 18. Test circuits for measuring crosstalk between any two switches/multiplexers 2RL 2RL VCC Sn, E Vct nYn G 2RL nZ VEE GND 2RL oscilloscope 001aah913 Fig 19. Test circuit for measuring crosstalk between control input and any switch http://www.hgsemi.com.cn 18 2018 AUG 74HC4052/ 74HCT4052 VCC Sn 10 μF Vis nYn/nZ nZ/nYn VEE GND RL Vos CL dB 001aah829 VCC = 4.5 V; GND = 0 V; VEE = −4.5 V; RL = 50 Ω; RS = 1 kΩ. a. Test circuit 001aad551 5 Vos (dB) 3 1 −1 −3 −5 10 102 103 104 105 106 f (kHz) b. Typical frequency response Fig 20. Test circuit for frequency response http://www.hgsemi.com.cn 19 2018 AUG