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π142M31

π142M31

  • 厂商:

    2PAISEMI(荣湃)

  • 封装:

    SOIC16N

  • 描述:

    -

  • 数据手册
  • 价格&库存
π142M31 数据手册
2Pai Semi Enhanced ESD, 3.0 kV rms/6.0 kV rms 10Mbps Quad-Channel Digital Isolators Data Sheet FEATURES Ultra low power consumption (1Mbps): 0.58mA/Channel High data rate: π14xAxx: 600Mbps π14xExx: 200Mbps π14xMxx: 10Mbps π14xUxx: 150kbps High common-mode transient immunity: 75 kV/µs typical High robustness to radiated and conducted noise Low propagation delay: 8 ns typical for 5 V operation 9 ns typical for 3.3 V operation Isolation voltages: π14xx3x: AC 3000Vrms π14xx6x: AC 6000Vrms High ESD rating: ESDA/JEDEC JS-001-2017 Human body model (HBM) ±8kV, all pins Safety and regulatory approvals (Pending): UL certificate number: E494497 3000Vrms/6000Vrms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate number: 40047929 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 707V peak/1200V peak CQC certification per GB4943.1-2011 3 V to 5.5 V level translation AEC-Q100 qualification Wide temperature range: -40°C to 125°C 16-lead, RoHS-compliant, SOIC_N, SOIC_W and SSOP package APPLICATIONS General-purpose multichannel isolation Industrial field bus isolation π140M/π141M/π142M The π1xxxxx isolator data channels are independent and are available in a variety of configurations with a withstand voltage rating of 1.5 kV rms to 6.0 kV rms and the data rate from DC up to 600Mbps (see the Ordering Guide). The devices operate with the supply voltage on either side ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. The fail-safe state is available in which the outputs transition to a preset state when the input power supply is not applied. FUNCTIONAL BLOCK DIAGRAMS π140X3X 1 16 VDD2 2 15 GND 2 VOA VIA 3 14 VOA VOB VIB 4 13 VOB 12 VOC VIC 5 12 VOC 11 VOD VID 6 11 VOD 10 NC NC 7 10 EN2 9 GND2 GND1 8 9 GND 2 1 16 VDD2 2 15 GND2 VIA 3 14 VIB 4 13 VIC 5 VID 6 NC 7 GND1 8 π141X3X π140X6X VDD1 GND1 VDD1 GND1 π141X6X VDD 1 1 GND1 2 15 GND 2 VOA VIA 3 14 VOA VDD1 1 16 VDD2 GND1 2 15 GND2 VIA 3 14 16 VDD2 VIB 4 13 VOB VIB 4 13 VOB V IC 5 12 VOC VIC 5 12 VOC VOD 6 11 VID VOD 6 11 V ID NC 7 10 NC EN1 7 10 EN2 GND1 8 9 GND2 GND1 8 9 GND2 π142X3X VDD1 1 16 VDD2 GND1 2 15 GND2 VIA 3 14 VIB 4 13 π142X6X VDD1 1 16 VDD2 GND 1 2 15 GND 2 VOA VIA 3 14 VOA VOB VIB 4 13 VOB VOC 5 12 V IC VOC 5 12 VIC VOD 6 11 V ID VOD 6 11 VID NC 7 10 NC EN1 7 10 EN2 GND1 8 9 GND2 9 GND2 GND1 8 Figure1. π140xxx/π141xxx/π142xxx functional Block Diagram VDD1 VDD2 GENERAL DESCRIPTION The π1xxxxx is a 2PaiSemi digital isolators product family that includes over hundreds of digital isolator products. By using maturated standard semiconductor CMOS technology and 2PaiSEMI iDivider technology, these isolation components provide outstanding performance characteristics and reliability superior to alternatives such as optocoupler devices and other integrated isolators. Intelligent voltage divider technology (iDivider technology) is a new generation digital isolator technology invented by 2PaiSEMI. It uses the principle of capacitor voltage divider to transmit voltage signal directly cross the isolator capacitor without signal modulation and demodulation. COUT CIN 0.1uF 0.1uF 1 2 3 4 5 6 7 8 VIN_A VIN_B VIN_C VIN_D GND1 VDD1 GND1 VIA VIB VIC VID NC GND1 VDD2 GND2 VOA VOB VOC VOD NC GND2 16 15 14 13 12 11 10 9 VOUT_A VOUT_B VOUT_C VOUT_D GND2 Figure2. π140x3x Typical Application Circuit Rev.1 Information furnished by 2Pai semi is believed to be accurate and reliable. However, no responsibility is assumed by 2Pai semi for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of 2Pai semi. Trademarks and registered trademarks are the property of their respective owners. Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China 021-50850681 2Pai Semiconductor Co., Limited. All rights reserved. http://www.rpsemi.com/ π140M/π141M/π142M Data Sheet PIN CONFIGURATIONS AND FUNCTIONS π140Mxx Pin Function Descriptions Pin No. Name Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. This pin is the ground reference for Isolator Side 1. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VIC 6 7 DD1 DD2 1 2 IA OA IB OB Logic Input C. IC OC VID Logic Input D. ID OD NC No connect. 8 GND1 Ground 1. This pin is the ground reference for Isolator Side 1. 9 GND2 Ground 2. This pin is the ground reference for Isolator Side 2. 10 NC /EN2 11 VOD No connect for π140M3X. Output enable for π140M6X. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low. Logic Output D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. This pin is the ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. /EN2 1 2 Figure3 π140Mxx Pin Configuration π141Mxx Pin Function Descriptions Pin No. Name Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. This pin is the ground reference for Isolator Side 1. 3 VIA Logic Input A. IA OA 4 VIB Logic Input B. IB OB 5 VIC Logic Input C. IC OC 6 VOD Logic Output D. 7 NC/EN1 OD ID DD1 8 GND1 No connect for π141M3X. Output enable 1 for π141M6X. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low. Ground 1. This pin is the ground reference for Isolator Side 1. 9 GND2 Ground 2. This pin is the ground reference for Isolator Side 2. 10 NC/EN2 11 VID No connect for π141M3X. Output enable 2 for π141M6X. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low. Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. This pin is the ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. Rev. 1 | Page 2 of 17 DD2 1 2 /EN1 /EN2 1 2 Figure4. π141Mxx Pin Configuration π140M/π141M/π142M Data Sheet π142Mxx Pin Function Descriptions Pin No. Name Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. This pin is the ground reference for Isolator Side 1. 3 VIA Logic Input A. IA OA 4 VIB Logic Input B. IB OB 5 VOC Logic Output C. OC IC 6 VOD Logic Output D. OD ID 7 NC/EN1 DD1 8 GND1 No connect for π142M3X. Output enable 1 for π142M6X. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low. Ground 1. This pin is the ground reference for Isolator Side 1. 9 GND2 Ground 2. This pin is the ground reference for Isolator Side 2. 10 NC/EN2 11 VID No connect for π142M3X. Output enable 2 for π142M6X. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low. Logic Input D. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 15 GND2 Ground 2. This pin is the ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. DD2 2 1 /EN1 /EN2 1 2 Figure5. π142Mxx Pin Configuration ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 1. Absolute Maximum Ratings4 Parameter Rating Supply Voltages (VDD1-GND1, VDD2-GND2) −0.5 V to +7.0 V Input Voltages (VIA, VIB)1 −0.5 V to VDDx + 0.5 V Output Voltages (VOA, VOB )1 −0.5 V to VDDx + 0.5 V Average Output Current per Pin2 Side 1 Output Current (IO1) −10 mA to +10 mA Average Output Current per Pin2 Side 2 Output Current (IO2) −10 mA to +10 mA Common-Mode Transients Immunity 3 −150 kV/µs to +150 kV/µs Storage Temperature (TST) Range −65°C to +150°C Ambient Operating Temperature (TA) Range −40°C to +125°C Notes: 1 VDDx is the side voltage power supply VDD, where x = 1 or 2. 2 See Figure 6 for the maximum rated current values for various temperatures. 3 See Figure 19 for Common-mode transient immunity (CMTI) measurement. 4 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 1 | Page 3 of 17 π140M/π141M/π142M Data Sheet RECOMMENDED OPERATING CONDITIONS Table 2. Recommended Operating Conditions Parameter Supply Voltage Symbol VDDx Min 1 Typ Max Unit 5.5 V 3 High Level Input Signal Voltage VIH 0.7*VDDx Low Level Input Signal Voltage VIL 0 High Level Output Current IOH -6 Low Level Output Current IOL Maximum Data Rate 1 VDDx 1 0.3*VDDx1 V V mA 6 mA 0 10 Mbps Junction Temperature TJ -40 150 °C Ambient Operating Temperature TA -40 125 °C Notes: 1 VDDx is the side voltage power supply VDD, where x = 1 or 2. Truth Tables Table 3. π140M3x/π141M3x/π142M3x Truth Table Default Low Default High VOx Output1 VOx Output1 Test Conditions /Comments Powered2 Low Low Normal operation Powered2 High High Normal operation Powered2 Powered2 Low High Default output Unpowered3 Powered2 Low High Default output5 Powered2 Unpowered3 High Impedance High Impedance VIx Input1 VDDI State1 VDDO State1 Low Powered2 High Powered2 Open Don’t Care4 Don’t Care4 Notes: 1 VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel. 2 Powered means VDDx≥ 2.9 V 3 Unpowered means VDDx < 2.3V 4 Input signal (VIx) must be in a low state to avoid powering the given VDDI1 through its ESD protection circuitry. 5 If the VDDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input status logic signal after around 1us. Table 4. π140M6x/π141M6x/π142M6x Truth Table Default Low Default High VOx Output1 VOx Output1 Test Conditions /Comments Powered2 Low Low Normal operation Powered2 High High Normal operation Powered2 Powered2 High Impedance High Impedance Disabled High or NC Powered2 Powered2 Low High Default output5 High or NC Unpowered3 Powered2 Low High Default output5 L Unpowered3 Powered2 High Impedance High Impedance Powered2 Unpowered3 High Impedance High Impedance VIx Input1 EN1/2 State VDDI State1 VDDO State1 Low High or NC Powered2 High High or NC Powered2 Don’t Care4 L Open Don’t Care4 Don’t Care4 Don’t Care4 Don’t Care4 Notes: 1VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel. 2Powered means V DDx≥ 2.9 V 3Unpowered means V DDx < 2.3V 4Input signal (VIx) must be in a low state to avoid powering the given VDDI1 through its ESD protection circuitry. 5If the V DDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input status logic signal after around 1us. Rev. 1 | Page 4 of 17 π140M/π141M/π142M Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS Table 5. Switching Specifications VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted. Parameter Minimum Pulse Width Symbol Pulse Width Distortion4 Part to Part Propagation Delay Skew4 Channel to Channel Propagation Delay Skew4 Typ Max PW Maximum Data Rate Propagation Delay Time1,4 Min 100 10 tpHL, tpLH PWD Unit Test Conditions/Comments ns Within pulse width distortion (PWD) limit Mbps Within PWD limit 5.5 8 12.5 ns The different time between 50% input signal to 50% output signal 50% @ 5VDC supply 6.5 9 13.5 ns @ 3.3VDC supply 0 0.3 0.8 ns The max different time between tpHL and tpLH@ 5VDC supply. And The value is | tpHL - tpLH | 0 0.3 0.8 ns @ 3.3VDC supply 1 ns The max different propagation delay time between any two devices at the same temperature, load and voltage @ 5VDC supply 1 ns 0 1 ns 0 0.8 ns tPSK tCSK @ 3.3VDC supply The max amount propagation delay time differs between any two output channels in the single device @ 5VDC supply. @ 3.3VDC supply Output Signal Rise/Fall Time4 tr/tf 1.5 Dynamic Input Supply Current per Channel IDDI (D) 9 µA /Mbps 10% to 90% signal terminated 50,See figure15. Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply Dynamic Output Supply Current per Channel IDDO (D) 38 µA /Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 5VDC Supply Dynamic Input Supply Current per Channel IDDI (D) 5 µA /Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply Dynamic Output Supply Current per Channel IDDO (D) 23 µA /Mbps Inputs switching, 50% duty cycle square wave, CL = 0 pF @ 3.3VDC Supply Common-Mode Transient Immunity3 CMTI 75 kV/µs VIN = VDDx2 or 0V, VCM = 1000 V 120 ps p-p See the Jitter Measurement section 20 ps rms See the Jitter Measurement section ±8 kV All pins Jitter ESD(HBM - Human body model) ESD ns Notes: 1 tpLH = low-to-high propagation delay time, tpHL = high-to-low propagation delay time. See figure 16. 2V DDx is the side voltage power supply VDD, where x = 1 or 2. 3 See Figure19 for Common-mode transient immunity (CMTI) measurement. 4 Output Signal Terminated 50 Table 6. DC Specifications VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted. Symbol Rising Input Signal Voltage Threshold VIT+ Min Typ Max 0.6*VDDx1 0.7*VDDx1 Rev. 1 | Page 5 of 17 Unit V Test Conditions/Comments π140M/π141M/π142M Data Sheet Falling Input Signal Voltage Threshold High Level Output Voltage Low Level Output Voltage Input Current per Signal Channel VDDx1 Undervoltage Rising Threshold VDDx1 Undervoltage Falling Threshold VDDx1 Hysteresis VIT- 0.3* VDDX1 0.4* VDDX1 V VOH 1 VDDx − 0.1 VDDx V −20 µA output current VDDx − 0.2 VDDx − 0.1 V −2 mA output current VOL 0 0.1 V 20 µA output current 0.1 0.2 V 2 mA output current 0 V ≤ Signal voltage ≤ VDDX1 IIN −10 0.5 10 µA VDDxUV+ 2.45 2.65 2.9 V VDDxUV− 2.3 2.5 2.75 V VDDxUVH 0.15 V Notes: 1 VDDx is the side voltage power supply VDD, where x = 1 or 2. Table 7. Quiescent Supply Current VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted. Parameter π140Mxx Quiescent Supply Current @ 5VDC Supply @ 3.3VDC Supply π141Mxx Quiescent Supply Current @ 5VDC Supply @ 3.3VDC Supply π142Mxx Quiescent Supply Current @ 5VDC Supply @ 3.3VDC Supply Symbol Min Typ Max Unit Test Conditions IDD1 (Q) 128 160 208 µA 0V Input signal IDD2 (Q) 1562 1952 2538 µA 0V Input signal IDD1 (Q) 315 394 512 µA 5V Input signal IDD2 (Q) 1477 1846 2400 µA 5V Input signal IDD1 (Q) 126 158 205 µA 0V Input signal IDD2 (Q) 1544 1930 2509 µA 0V Input signal IDD1 (Q) 232 290 377 µA 3.3V Input signal IDD2 (Q) 1418 1772 2304 µA 3.3V Input signal IDD1 (Q) 483 604 785 µA 0V Input signal IDD2 (Q) 1200 1500 1950 µA 0V Input signal IDD1 (Q) 594 742 965 µA 5V Input signal IDD2 (Q) 1174 1468 1908 µA 5V Input signal IDD1 (Q) 478 597 776 µA 0V Input signal IDD2 (Q) 1186 1483 1928 µA 0V Input signal IDD1 (Q) 524 655 852 µA 3.3V Input signal IDD2 (Q) 1117 1396 1815 µA 3.3V Input signal IDD1 (Q) 838 1048 1362 µA 0V Input signal IDD2 (Q) 838 1048 1362 µA 0V Input signal IDD1 (Q) IDD2 (Q) 872 872 1090 1090 1417 1417 µA µA 5V Input signal 5V Input signal IDD1 (Q) 829 1036 1347 µA 0V Input signal IDD2 (Q) 829 1036 1347 µA 0V Input signal IDD1 (Q) 816 1020 1326 µA 3.3V Input signal IDD2 (Q) 816 1020 1326 µA 3.3V Input signal Table 8. Total Supply Current vs. Data Throughput (CL = 0 pF) VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted. Rev. 1 | Page 6 of 17 π140M/π141M/π142M Data Sheet Parameter Symbol π140Mxx Supply Current @5VDC @ 3.3VDC π141Mxx Supply Current @5VDC @ 3.3VDC π142Mxx Supply Current @5VDC @ 3.3VDC 150 Kbps Min 1 Mbps Typ Max IDD1 0.28 IDD2 Min 10 Mbps Typ Max 0.42 0.30 1.90 2.85 IDD1 0.22 IDD2 Min Typ Max Unit 0.45 0.48 0.72 mA 2.04 3.06 3.52 5.28 mA 0.33 0.24 0.36 0.36 0.54 mA 1.86 2.79 1.94 2.91 2.86 4.29 mA IDD1 0.68 1.02 0.73 1.10 1.21 1.82 mA IDD2 1.49 2.24 1.60 2.40 2.73 4.10 mA IDD1 0.63 0.95 0.66 0.99 0.95 1.43 mA IDD2 1.45 2.18 1.51 2.27 2.20 3.30 mA IDD1 1.08 1.62 1.16 1.74 1.94 2.91 mA IDD2 1.08 1.62 1.16 1.74 1.94 2.91 mA IDD1 1.04 1.56 1.08 1.62 1.54 2.31 mA IDD2 1.04 1.56 1.08 1.62 1.54 2.31 mA INSULATION AND SAFETY RELATED SPECIFICATIONS Table 9. Insulation Specifications Parameter Symbol Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Value Unit Test Conditions/Comments π14xM3x π14xM6x 3000 6000 L (CLR) 4 8 mm min L (CRP) 4 8 mm min 11 21 µm min Insulation distance through insulation >400 >400 V DIN IEC 112/VDE 0303 Part 1 II II CTI Material Group V rms 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Material Group (DIN VDE 0110, 1/89, Table 1) PACKAGE CHARACTERISTICS Table 10. Package Characteristics Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Symbol Typical Value Unit π14xM3x π14xM6x RI-O 10 11 10 11 Ω Test Conditions/Comments CI-O 0.6 0.6 pF @1MHz Input Capacitance2 CI 3 3 pF @1MHz IC Junction to Ambient Thermal Resistance θJA 100 45 °C/W Thermocouple located at center of package underside Notes: 1The device is considered a 2-terminal device; SOIC-16 Pin 1 - Pin 8(WSOIC-16 Pin 1-Pin8 and SSOP16 Pin 1-Pin8) are shorted together as the one terminal, and SOIC-16 Pin 9- Pin 16(WSOIC-16 Pin 9-Pin16 and SSOP16 Pin 9-Pin16) are shorted together as the other terminal. 2Testing from the input signal pin to ground. REGULATORY INFORMATION See Table 11 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Rev. 1 | Page 7 of 17 π140M/π141M/π142M Data Sheet Table11. Regulatory π14xM3x Regulatory UL π14xM6x Recognized under UL 1577 Component Recognition Recognized under UL 1577 Program1 Component Recognition Program1 Single Protection, 3000 V rms Isolation Voltage CSA Single Protection, 6000 V rms Isolation Voltage File (E494497) File (pending) Approved under CSA Component Acceptance Notice 5A Approved under CSA Component Acceptance Notice 5A CSA 60950-1-07+A1+A2 and CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2: IEC 60950-1, second edition, +A1+A2: Basic insulation at 500Vrms (707Vpeak) Basic insulation at 845Vrms (1200Vpeak) Reinforced insulation at 250 V rms Reinforced insulation at422V rms (353 V peak) (600V peak) File (pending) VDE DIN V VDE V 0884-10 (VDE V File (pending) 0884-10):2006-122 DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Basic insulation, VIORM = 707 V peak, VIOSM = 4615 V peak Basic insulation, VIORM = 1200Vpeak, VIOSM = 7000V peak Reinforced insulation, VIORM =600V peak CQC File (40047929) File (pending) Certified under Certified under CQC11-471543-2012 CQC11-471543-2012 GB4943.1-2011 Basic insulation at 500 V rms (707 V peak) working voltage Reinforced insulation at GB4943.1-2011 250 V rms (353 V peak) 422V rms (600V peak) File (pending) File (pending) Basic insulation at 845V rms (1200V peak) working voltage Reinforced insulation at Notes: 1 In accordance with UL 1577, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec; each π140M6x/π141M6x/π142M6x is proof tested by applying an isulation test voltage ≥ 7200 V rms for 1 sec 2 In accordance with DIN V VDE V 0884-10, each π140M3x/π141M3x/π142M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); each π140M6x/π141M6x/π142M6x is proof tested by ≥ 2250V peak for 1 sec. The marking branded on the component designates DIN V VDE V 0884-10 approval. DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance of the safety data. The marking on packages denotes DIN V VDE V 0884-10 approval. Table 12. VDE Insulation Characteristics Description Test Conditions/Comments Symbol Characteristic π14xM3x π14xM6x I to IV I to IV I to III I to III Unit Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage VIORM Rev. 1 | Page 8 of 17 I to III I to III 40/105/21 40/105/21 2 2 707 1200 V peak π140M/π141M/π142M Data Sheet Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Vpd (m) 1326 2250 V peak VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC Vpd (m) 1061 1800 V peak 849 1440 V peak Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIOTM 4200 8500 V peak Surge Isolation Voltage Basic Basic insulation, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 4615 7000 V peak Surge Isolation Voltage Reinforced Reinforced insulation, 1.2 µs rise time, 50 µs, 50% fall time VIOSM Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 6) V peak Maximum Junction Temperature TS 150 150 °C Total Power Dissipation at 25°C PS 1.56 2.78 W RS >109 >109 Ω Insulation Resistance at TS VIO = 800 V π14xM3x π14xM6x 3 12.0 2.9 Propagation Delay Time(nS) Power Supply Undervoltage Threshold Figure6. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per VDE 2.8 2.7 2.6 2.5 VDDxUV+(V) VDDxUV−(V) 2.4 2.3 2.2 10.0 8.0 6.0 tpHL(ns)@3.3V tpLH(ns)@3.3V tpHL(ns)@5.0V tpLH(ns)@5.0V 4.0 2.0 0.0 0 50 100 150 0 Free-Air Temperature ( °C) Figure7. UVLO vs. Free-Air Temperature 50 100 Free-Air Temperature ( °C) Figure8. Propagation Delay Time vs. Free-Air Temperature Rev. 1 | Page 9 of 17 150 π140M/π141M/π142M 1.6 1.4 1.2 1.0 IDD1@ 0V Input IDD2@ 0V Input IDD1@ 3.3V Input IDD2@ 3.3V Input 0.8 0.6 0.4 0.2 0.0 0 50 100 150 π140Mxx Quiescent Supply Current (mA) π140Mxx Quiescent Supply Current (mA) Data Sheet 1.6 1.4 1.2 1.0 IDD1@ 0V Input IDD2@ 0V Input IDD1@ 5V Input IDD2@ 5V Input 0.8 0.6 0.4 0.2 0.0 0 Free-Air Temperature ( °C) 0.8 0.6 IDD1@ 0V Input IDD2@ 0V Input IDD1@ 3.3V Input IDD2@ 3.3V Input 0 50 100 150 Free-Air Temperature ( °C) π142Mxx Quiescent Supply Current (mA) IDD1@ 0V Input IDD2@ 0V Input IDD1@ 3.3V Input IDD2@ 3.3V Input 0 50 100 1.4 1.2 1.0 0.8 0.6 IDD1@ 0V Input IDD2@ 0V Input IDD1@ 5V Input IDD2@ 5V Input 0.4 0.2 0.0 0 50 100 150 Free-Air Temperature ( °C) Figure 11 π141Mxx Quiescent Supply Current with 3.3V Supply vs.Free-Air Temperature 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 π141Mxx Quiescent Supply Current (mA) 1.0 0.0 150 Figure10 π140Mxx Quiescent Supply Current with 5V Supply vs. Free-Air Temperature 150 Free-Air Temperature ( °C) Figure 13 π142Mxx Quiescent Supply Current with 3.3V Supply vs.Free-Air Temperature Figure 12 π141Mxx Quiescent Supply Current with 5V Supply vs. Free-Air Temperature π142Mxx Quiescent Supply Current (mA) π141Mxx Quiescent Supply Current (mA) 1.2 0.2 100 Free-Air Temperature ( °C) Figure9 π140Mxx Quiescent Supply Current with 3.3V Supply vs.Free-Air Temperature 0.4 50 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 IDD1@ 0V Input IDD2@ 0V Input IDD1@ 5V Input IDD2@ 5V Input 0 50 100 150 Free-Air Temperature ( °C) Figure 14 π142Mxx Quiescent Supply Current with 5V Supply vs. Free-Air Temperature Rev. 1 | Page 10 of 17 π140M/π141M/π142M Data Sheet VDDX Figure15. Transition time waveform measurement Figure16. Propagation delay time waveform measurement Rev. 1 | Page 11 of 17 π140M/π141M/π142M Data Sheet APPLICATIONS INFORMATION the user may also include resistors (50–300 Ω) in series with the inputs and outputs if the system is excessively noisy. OVERVIEW The π1xxxxx are 2PaiSemi digital isolators product family based on 2PaiSEMI unique iDivider technology. Intelligent voltage Divider technology (iDivider technology) is a new generation digital isolator technology invented by 2PaiSEMI. It uses the principle of capacitor voltage divider to transmit signal directly cross the isolator capacitor without signal modulation and demodulation. Compare to the traditional Opto-couple technology, icoupler technology, OOK technology, iDivider is a more essential and concise isolation signal transmit technology which leads to greatly simplification on circuit design and therefore significantly improves device performance, such as lower power consumption, faster speed, enhanced antiinterference ability, lower noise. By using maturated standard semiconductor CMOS technology and the innovative iDivider design, these isolation components provide outstanding performance characteristics and reliability superior to alternatives such as optocoupler devices and other integrated isolators. The π1xxxxx isolator data channels are independent and are available in a variety of configurations with a withstand voltage rating of 1.5 kV rms to 6.0 kV rms and the data rate from DC up to 600Mbps (see the Ordering Guide). The π140Mxx/π141Mxx/π142Mxx are the outstanding 10Mbps quad-channel digital isolators with the enhanced ESD capability. the devices transmit data across an isolation barrier by layers of silicon dioxide isolation. The devices operate with the supply voltage on either side ranging from 3.0 V to 5.5 V, offering voltage translation of 3.3 V, and 5 V logic. The π140Mxx/π141Mxx/π142Mxx have very low propagation delay and high speed. The input/output design techniques allow logic and supply voltages over a wide range from 3.0 V to 5.5 V, offering voltage translation of 3.3 V and 5 V logic. The architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. See the Ordering Guide for the model numbers that have the failsafe output state of low or high. PCB LAYOUT The low-ESR ceramic bypass capacitors must be connected between VDD1 and GND1 and between VDD2 and GND2. The bypass capacitors are placed on the PCB as close to the isolator device as possible. The recommended bypass capacitor value is between 0.1 μF and 10 μF. To enhance the robustness of a design, VDD1 VDD2 GND1 GND2 VIA VIB VIC/VOC VID/VOD Avoid reducing the isolation capability, Keep the space underneath the isolator device free from metal such as planes, pads, traces and vias. To minimize the impedance of the signal return loop, keep the solid ground plane directly underneath the high-speed signal path, the closer the better. The return path will couple between the nearest ground plane to the signal path. Keep suitable trace width for controlled impedance transmission lines interconnect. To reduce the rise time degradation, keep the length of input/output signal traces as short as possible, and route low inductance loop for the signal path and It’s return path. JITTER MEASUREMENT The eye diagram shown in the figure18 provides the jitter measurement result for the π140Mxx/π141Mxx/π142Mxx. The Keysight 81160A pulse function arbitrary generator works as the data source for the π140Mxx/π141Mxx/π142Mxx, which generates 100Mbps pseudo random bit sequence (PRBS). The Keysight DSOS104A digital storage oscilloscope captures the π140Mxx/π141Mxx/π142Mxx output waveform and recoveries the eye diagram with the SDA tools and eye diagram analysis tools. The result shows a typical measurement 120ps p-p jitter. Figure18. π140Mxx/π141Mxx/π142Mxx Eye Diagram CMTI MEASUREMENT To measure the Common-Mode Transient Immunity (CMTI) of π1xxxxx isolator under specified common-mode pulse magnitude (VCM) and specified slew rate of the common-mode pulse (dVCM/dt) and other specified test or ambient conditions, The common-mode pulse generator (G1) will be capable of providing VOA VOB VOC/VIC VOD/VID NC GND1 NC Figure19. Common-mode transient immunity (CMTI) measurement GND2 Figure17.Recommended Printed Circuit Board Layout Rev. 1 | Page 12 of 17 π140M/π141M/π142M Data Sheet fast rising and falling pulses of specified magnitude and duration of the common-mode pulse (VCM) and the maximum commonmode slew rates (dVCM/dt) can be applied to π1xxxxx isolator coupler under measurement. The common-mode pulse is applied between one side ground GND1 and the other side ground GND2 of π1xxxxx isolator and shall be capable of providing positive transients as well as negative transients. OUTLINE DIMENSIONS Figure20. 16-Lead Standard Small Outline Package [16-Lead SOIC_N] Figure21. 16-Lead Wide Body Outline Package [16-Lead SOIC_W] Rev. 1 | Page 13 of 17 π140M/π141M/π142M Data Sheet Figure22. 16-Lead SSOP Outline Package [SSOP16] REEL INFORMATION 16-Lead SOIC_N Rev. 1 | Page 14 of 17 π140M/π141M/π142M Data Sheet 16-Lead SOIC_W 16-Lead SSOP Rev. 1 | Page 15 of 17 π140M/π141M/π142M Data Sheet ORDERING GUIDE π140M31 Pai140M31 −40°C to +125°C No. of Input s, VDD1 Side 4 0 3 High 16-Lead SOIC_N S-16-N 2500 per reel π140M30 Pai140M30 −40°C to +125°C 4 0 3 Low 16-Lead SOIC_N S-16-N 2500 per reel π141M31 Pai141M31 −40°C to +125°C 3 1 3 High 16-Lead SOIC_N S-16-N 2500 per reel π141M30 Pai141M30 −40°C to +125°C 3 1 3 Low 16-Lead SOIC_N S-16-N 2500 per reel π142M31 Pai142M31 −40°C to +125°C 2 2 3 High 16-Lead SOIC_N S-16-N 2500 per reel π142M30 Pai142M30 −40°C to +125°C 2 2 3 Low 16-Lead SOIC_N S-16-N 2500 per reel π140M61 Pai140M61 −40°C to +125°C 4 0 6 High 16-Lead SOIC_W S-16-W 1500 per reel π140M60 Pai140M60 −40°C to +125°C 4 0 6 Low 16-Lead SOIC_W S-16-W 1500 per reel π141M61 Pai141M61 −40°C to +125°C 3 1 6 High 16-Lead SOIC_W S-16-W 1500 per reel π141M60 Pai141M60 −40°C to +125°C 3 1 6 Low 16-Lead SOIC_W S-16-W 1500 per reel π142M61 Pai142M61 −40°C to +125°C 2 2 6 High 16-Lead SOIC_W S-16-W 1500 per reel π142M60 Pai142M60 −40°C to +125°C 2 2 6 Low 16-Lead SOIC_W S-16-W 1500 per reel π140M31S Pai140M31S −40°C to +125°C 4 0 3 High 16-Lead SSOP SSOP16 4000 per reel π140M30S Pai140M30S −40°C to +125°C 4 0 3 Low 16-Lead SSOP SSOP16 4000 per reel π141M31S Pai141M31S −40°C to +125°C 3 1 3 High 16-Lead SSOP SSOP16 4000 per reel π141M30S Pai141M30S −40°C to +125°C 3 1 3 Low 16-Lead SSOP SSOP16 4000 per reel π142M31S Pai142M31S −40°C to +125°C 2 2 3 High 16-Lead SSOP SSOP16 4000 per reel π142M30S Pai142M30S −40°C to +125°C 2 2 3 Low 16-Lead SSOP SSOP16 4000 per reel Model Name Temperature Range No. of Inputs , VDD2 Side Withstan d Voltage Rating (kV rms) FailSafe Outpu t State Package Description Package Option Notes: 1 π14xxxxQ special for Auto, qualified for AEC-Q100 PART NUMBER NAMED RULE π(1)(2)(0)(A)(3)(0)(S) SeriesNumber: 1,2,3... Total Channel Am ount: N=N Channels N=1,2,3,4,5,6... Reverse Channel Amount: N=N Channels N=0,1,2,3... Data Rate:A=600Mbps E=200Mbps M=10Mbps U=150Kbps Isolation Voltag es: N=1 1.5KVrms AC N=3 3KVrms AC N=6 6KVrms AC Fail-Safe Output Stat e: 0=Logic Low 1=Logic High Optional: S=SSOP Package Q=AEC-Q100 Qualified Notes: Pai14xxxx is equals to π14xxxx in the customer BOM Rev. 1 | Page 16 of 17 Quantity π140M/π141M/π142M Data Sheet REVISION HISTORY Revision Updated Date Page Change Record 1 Victory 2018/09/20 All 2 Victory 2018/11/28 P1,P11 3 Devin 2019/09/08 P1,P7,P11 ,P13,P14, P15 Initial version Changed CIN,COUT in Figure2 from 0.1uF to 1uF. Changed the recommended bypass capacitor value from between 0.1 μF and 1 μF to between 0.1 μF and 10 μF. P1: Changed the address from ‘Room 19307, Building 8, No.498, GuoShouJing Road’ to ‘Room 308-309, No.22, Boxia Road’; Changed ‘(W)SOIC package’ to ‘SOIC_N, SOIC_W and SSOP package’; Add iDivider technology description in General Description. Changed propagation delay for 5V from 7.5ns to 8ns. Changed CMTI from 50KV/us to 75KV/us. Changed CIN,COUT in Figure2 from 1uF to 0.1uF. P7: Add ‘and SSOP16 Pin 1-Pin8’ and ‘and SSOP16 Pin 9-Pin16’ in note 1. P11: Add iDivider technology description in overview. P13: Add Figure22. 16-Lead SSOP Outline Package drawing P14: Add 16-Lead SSOP Reel drawing; Updated 16-Lead SOIC_W reel drawing. P15: Add character ‘S’ and ‘Q’ in part number named rule; Changed the SOIC_W quantity from ‘1000 per reel’ to ‘1500 per reel’; Add ‘π140M31S、π140M30S、 π141M31S、π141M30S、π142M31S、π142M30S’ in ordering guide Rev. 1 | Page 17 of 17
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