AW39104
Apr. 2020 V1.4
4-bit Bidirectional Voltage-Level Translator for Open-Drain
and Push-Pull Applications
Features
General Description
AW39104 is a 4-bit high-performance voltage-level
translator without direction control signal, which is a
non-inverting converter and can be used to convert
digital signal with mixed-voltage systems. It needs
two separate power supply rails, with the A ports
tracks the VCCA ranging from 1.65 V to 3.6 V, and
the B ports tracks the VCCB ranging from 2.3 V to 5.5
V. This makes the chip has capabilities of support
both lower and higher logic signal levels translation
between any of the 1.8 V, 2.5 V, 3.3 V, and 5 V
voltage nodes.
l
No power supply sequencing requirements means
either VCCA or VCCB can be powered up first, and
OE should be enabled after both VCCA and VCCB
are established.
fi
Applications
a
If the voltage level of output-enable (OE) pin is low,
the chip works in the high-impedance state, which
costs ultra-low power-supply quiescent current.
And the OE input circuit is supplied by VCCA.
Meanwhile, OE is recommended to be tied to GND
through a pull-down resistor to ensure the highimpedance state during power up or power down.
ti
n
e
d
Voltage Level Translator Without DirectionControl Signal
Maximum Data Rates
- 24Mbps (Push Pull)
- 2Mbps (Open Drain)
Power Supply Range:
- A Port and VCCA: 1.65 V to 3.6 V
- B Port and VCCB: 2.3 V to 5.5 V
- VCCA ≤ VCCB
Pull Up Resistors are Integrated in A Port and B
Port
No Power-Supply Sequencing Required: Either
VCCA or VCCB Can be Ramped First
Support Ultra-Low Power Consumption Mode
with OE Pin is Low Voltage Level
I/O Pin ESD:
- A Port: 2.5 kV (HBM)
- B Port: 6 kV (HBM)
Latch -Up Performance Exceeds ±200mA Under
JESD 78 Standard
FOR 1.87mm×1.37mm-12B Package
I2C / SMBus
UART
GPIO
Handheld Devices Interface
C
o
n
Application Circuit
VCCA
VCCB
ic
VCCA
VCCB
CVCCA=0.1μF
in
CVCCB=0.1μF
a
w
1.8V
System
Controller
A1
B1
A2
B2
A3
AW39104 B3
A4
B4
3.3V
System
OE
GND
RPD
Figure 1 Typical Application Circuit of AW39104
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1
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Pin Configuration and Top Mark
AW39104FOR PIN Configuration
AW39104FOR Marking
(Top View)
(Top View)
2
1
GND
B4
C
A3
OE
B3
B
A2
VCCA
B2
A
A1
VCCB
B1
a
A4
DQFW
XXXX
D
l
3
ti
DQFW – AW39104FOR
n
XXXX – Production tracing code
d
e
Figure 2 Pin Configuration and Top Mark
C
o
n
Description
A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V, VCCA ≤ VCCB.
Input/output A1.
Input/output A2.
Input/output A3.
Input/output A4.
Ground.
Output enable.
Input/output B1.
Input/output B2.
Input/output B3.
Input/output B4.
B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V.
in
ic
Pin Name
VCCA
A1
A2
A3
A4
GND
OE
B1
B2
B3
B4
VCCB
w
Pin No.
B2
A3
B3
C3
D3
D2
C2
A1
B1
C1
D1
A2
fi
Pin Definition
a
NOTE: The Pin number of Pin 1（Pin No.）is A3 instead of A1, and the Pin name is A1.
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Functional Block Diagram
VCCA
VCCB
ONESHOT
EN
R1
10kΩ
EN
R2
10kΩ
G_BIAS
A1
B1
R4
10kΩ
G_BIAS
ti
EN
a
R3
10kΩ
l
ONESHOT
EN
B2
fi
G_BIAS
R6
10kΩ
n
EN
d
ONESHOT
EN
R5
10kΩ
e
n
A2
B3
C
o
A3
EN
ONESHOT
R8
10kΩ
G_BIAS
in
R7
10kΩ
ic
EN
w
A4
B4
a
OE
GND
EN
Figure 3 AW39104 Function Block
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Typical Application Circuits
VCCA
VCCB
VCCA
VCCB
CVCCA=0.1μF
CVCCB=0.1μF
1.8V
System
Controller
A1
B1
A2
B2
A3
AW39104 B3
A4
B4
3.3V
System
OE
GND
RPD
Figure 4 AW39104 Application Circuit
Markin
g
AW39104FOR
-40°C～85°C
FOR
1.87mm×1.37mm-12B
DQFW
Moisture
Sensitivity
Level
Environmenta
l Information
ti
Package
n
Temperatur
e
MSL1
ROHS+HF
Delivery
Form
3000 units/
Tape and Reel
a
w
in
ic
C
o
n
fi
d
e
Part Number
a
l
Ordering Information
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Absolute Maximum Ratings(NOTE1)
PARAMETERS
MIN
MAX
UNIT
Supply voltage range VCCA(NOTE2)
-0.5
5
V
Supply voltage range VCCB(NOTE2)
-0.5
6.5
V
A port
-0.5
5
V
B port
-0.5
6.5
V
A port
-0.5
5
V
B port
-0.5
6.5
V
Operating free-air temperature range
-40
85
°C
Operating junction temperature TJ
-40
125
°C
-65
150
°C
260
°C
Input voltage range, VI (NOTE2)
Output voltage range in high or low state, VO ( NOTE2)
Storage temperature TSTG
Lead temperature (Soldering 10 seconds)
ti
a
l
NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the ranges
listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged
periods may affect device reliability.
e
n
NOTE2: With respect to GND.
d
ESD Rating and Latch Up
VALUE
UNIT
B Port HBM (Human Body Model) (NOTE 3)
±6
kV
Other PINS HBM (Human Body Model)
±2.5
kV
±1.5
kV
o
n
fi
PARAMETERS
C
CDM(NOTE 4)
Latch-Up(NOTE 5)
+IT：200
-IT：-200
mA
ic
NOTE3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: ESDA/JEDEC JS-001-2017
NOTE4: Test method: ESDA/JEDEC JS-002-2018
a
w
in
NOTE5: Test method: JESD78E
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Recommended Operating Conditions
VCCI is the VCC associated with the input port
VIH
High-level input voltage
B-port
OE input
A-port
VIL
Low-level input voltage
B-port
OE input
A-port (NOTE 7)
Δt/ΔV
Input transition rise or
fall rate
B-port (NOTE7)
3.6
V
2.3
5.5
V
VCCI-0.4
VCCI
V
VCCI-0.4
VCCI
V
VCCA×0.65
5.5
V
0.4-IOL×RNPASS
0
Operating junction temperature T A
V
(NOTE6)
0.4-IOL×RNPASS
0
V
(NOTE6)
0
VCCA×0.35
V
10
ns/V
10
ns/V
10
ns/V
-40
85
°C
d
TA
1.65
e
Control input
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
VCCA=1.65V~3.6V
VCCB=2.3V~5.5V
UNIT
l
A-port
MAX
a
VCCB
Supply voltage for A
port
Supply voltage for B
port
MIN
ti
VCCA
CONDITIONS
n
PARAMETERS
fi
NOTE6: IOL is the current from external resistor to output port, RNPASS is equal internal resistor of NMOSFET
between A port and B port.
n
NOTE7: The parameter is defined for push-pull driving.
C
o
Thermal Information
VALUE
UNIT
Junction-to-ambient thermal resistance θJA
120
°C /W
a
w
in
ic
PARAMETERS
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Electrical Characteristics
DC Electrical Characteristics
Operating under recommended conditions, VCCA ≤ VCCB, T A=25°C for typical values (unless otherwise noted)
ICCB+
ICCA
RPU
1.65~3.6
2.3~5.5
IOH= -20μA
VIA≥VCCA-0.4V
1.65~3.6
2.3~5.5
IOL=1mA VIA≤0.15V
1.65~3.6
2.3~5.5
1.65~3.6
2.3~5.5
1.65~3.6
OE=VIH
VI=VO=Open
IO=0
TA=-40°C to 85°C
OE=VIH
VI=VO=Open
IO=0
TA=-40°C to 85°C
Combined
supply current
Resistor pull-up
value
VI=VO=Open
IO=0
T
TA=-40°
=25°CC to 85°C
The resistor of
NMOSFET
between A port
and B port
OE=VIH
TA=25°C
A
0.4
V
VCCB×0.67
V
V
-1
1
μA
2.3~5.5
-2
2
μA
1.65~3.6
2.3~5.5
-1
1
μA
1.65~3.6
2.3~5.5
-2
2
μA
1.65~3.6
2.3~5.5
1
μA
3.6
0
1
μA
0
5.5
-1
μA
2.3~5.5
16
μA
0
-1
μA
0
5.5
1
μA
1.65~3.6
2.3~5.5
18
μA
1.65~3.6
2.3~5.5
12
kΩ
1.8
3.3
1.65~3.6
3.6
a
0.4
ti
VI=VCCI or GND,
TA=25°C
VI=VCCI or GND,
TA=-40°C to 85°C
OE=VIL
TA=25°C
OE=VIL
TA=-40°C to 85°C
V
8
10
Ω
28
in
RNPASS
VCCB supply
current
IOL=1mA VIB≤0.15V
UNIT
l
ICCB
VCCA supply
current
VCCA×0.67
n
ICCA
2.3~5.5
e
IOZ
A or B port
output current in
high impedance
state
1.65~3.6
MAX
d
II
OE input
leakage current
IOH= -20μA
VIB≥VCCB-0.4V
TYP
fi
VOLB
MIN
o
VOHB
VCCB(V)
C
VOLA
Port A output
high voltage
Port A output
low voltage
Port B output
high voltage
Port B output
low voltage
VCCA(V)
ic
VOHA
TEST CONDITION
n
PARAMETER
Timing Requirements (NOTE1)
w
Output load: CL=15pF, push-pull driver, and TA=-40°C to 85°C.
VCCA=1.8V±0.15V / 2.5V±0.2V / 3.3V±0.3V
a
PARAMETER
Data Rate
tw
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Pulse Duration
TEST CONDITION
MIN
MAX
VCCB=2.5V±0.2V
21
VCCB=3.3V±0.3V
24
VCCB=5V±0.5V
24
VCCB=2.5V±0.2V
45
VCCB=3.3V±0.3V
40
7
UNIT
Mbps
ns
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
PARAMETER
TEST CONDITION
MIN
VCCB=5V±0.5V
MAX
UNIT
40
NOTE1: The parameter’s variation is guaranteed by design, not production tested.
Switch Characteristics(NOTE2)
Output load: CL=15pF, TA=25°C for typical values (unless otherwise noted), VCCA=1.8V
VCCB=2.5V
PARAMETER
VCCB=5V
UNIT
MIN
MAX
Push-pull
tPHL(NOTE3)
VCCB=3.3V
TEST CONDITION
MIN
11
MAX
MIN
7.0
MAX
5.0
A-B
ns
Open-drain
2.3
8.8
Push-pull
tPLH(NOTE3)
2.4
7.5
9.6
2.6
6.7
10
5.7
A-B
ns
45
260
36
208
27
198
Push-pull
tPHL(NOTE3)
9.0
5.3
Push-pull
tPLH(NOTE3)
1.1
7.4
OE-A or B
200
tfA
Input fall time
A port
fall time
tfB
Input fall time
B port
fall time
Open-drain
38
Push-pull
4
ns
4
4.1
ns
27
102
35
30
ns
200
200
ns
9.5
2.3
9.3
2
7.6
165
30
132
22
95
10.8
2.7
9.1
2.7
7.6
n
B port
rise time
3.2
o
trB
Input rise time
Push-pull
C
A port
rise time
ns
ns
Open-drain
34
145
23
106
10
58
Push-pull
2
5.9
1.9
6
1.7
13.3
4.4
6.9
4.3
6.4
4.2
6.1
Push-pull
2.9
13.8
2.8
16.2
2.8
16.2
Open-drain
6.9
13.8
7.5
16.2
7
16.2
ns
Open-drain
in
trA
Input rise time
140
e
45
fi
OE-A or B
36
d
175
5
ic
ten
Enable time
tdis
disable time
45
1.2
5.8
B-A
Open-drain
4.4
ti
1.9
n
Open-drain
w
ns
Channel to channel
skew
1
1
1
ns
a
tSK
Skew time
output
5.5
B-A
a
l
Open-drain
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Output load: CL=15pF, TA=25°C for typical values (unless otherwise noted), VCCA=2.5V
VCCB=2.5V
PARAMETER
VCCB=5V
UNIT
MIN
MAX
Push-pull
tPHL(NOTE3)
VCCB=3.3V
TEST CONDITION
MIN
3.2
MAX
MIN
3.7
MAX
3.8
A-B
ns
Open-drain
1.7
6.3
Push-pull
tPLH(NOTE3)
2
3.5
6
2.1
4.1
5.8
4.4
A-B
ns
Open-drain
45
250
Push-pull
tPHL(NOTE3)
36
3
206
27
190
3.6
4.3
B-A
ns
Open-drain
1.8
4.7
Push-pull
tPLH(NOTE3)
2.6
2.5
4.2
1.2
1.6
4
1
B-A
ns
37
140
OE-A or B
200
Open-drain
38
150
28
Push-pull
3.2
8.3
Open-drain
34
151
Push-pull
1.9
Open-drain
4.4
tfA
Input fall time
A port
fall time
tfB
Input fall time
B port
fall time
tSK
Skew time
output
Channel to channel
skew
Push-pull
2.2
5.1
1.8
5.6
121
24
89
2.9
7.2
2.4
6.1
24
112
12
64
1.9
5.5
1.8
5.3
6.9
4.3
6.4
4.2
5.8
7.8
2.4
6.7
2.6
6.6
8.8
5.4
9.4
5.4
10.4
5.7
ns
ns
ns
ns
1
1
1
ns
a
w
in
ic
Open-drain
ns
6.6
n
B port
rise time
o
trB
Input rise time
200
n
2.6
ns
e
7.4
d
2.8
A port
rise time
30
fi
Push-pull
trA
Input rise time
102
ti
35
27
l
170
OE-A or B
C
ten
Enable time
tdis
disable time
44
a
Open-drain
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Output load: CL=15pF, TA=25°C for typical values (unless otherwise noted), VCCA=3.3V
PARAMETER
VCCB=3.3V
MIN
MAX
TEST CONDITION
Push-pull
tPHL(NOTE3)
UNIT
3.1
ns
A-B
1.3
Push-pull
(NOTE3)
4.2
1.4
4.6
4.2
4.4
ns
A-B
Open-drain
36
Push-pull
tPHL(NOTE3)
204
27
165
2.5
3.3
ns
B-A
Open-drain
1
Push-pull
(NOTE3)
124
1
97
2.5
3.3
ns
B-A
Open-drain
ten
Enable time
tdis
disable time
3
139
3
105
30
a
l
OE-A or B
tfB
Input fall time
B port
fall time
Open-drain
25
116
Push-pull
2.5
6.4
Open-drain
26
Push-pull
2
Open-drain
Push-pull
4.8
19
85
2.1
7.4
116
14
72
5.4
1.9
5
4.3
6.4
4.2
5.7
2.3
7.4
2.4
7.6
Open-drain
7.6
4.8
8.3
5
ti
A port
fall time
1.9
n
tfA
Input fall time
5.6
fi
B port
rise time
2.3
n
trB
Input rise time
Push-pull
o
A port
rise time
C
trA
Input rise time
200
d
OE-A or B
e
tPLH
VCCB=5V
MAX
2.4
Open-drain
tPLH
MIN
1
ns
ns
ns
ns
ns
ns
ic
tSK
Channel to channel skew
1
Skew time output
NOTE2: The parameters is guaranteed by design, not production tested.
ns
a
w
in
NOTE3: tPHL presents propagation delay from high to low, and tPLH presents propagation delay from low to
high.
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Typical Characteristics
Test Information
input
output
AW39104
15pF
1MΩ
Test Circuit for Date Rate, Pulse Duration, Propagation Delay, Rise Time and Fall Time
Figure 5 Load Circuit of Push-Pull Driver
input
output
a
l
AW39104
1MΩ
n
ti
15pF
e
Test Circuit for Date Rate, Pulse Duration, Propagation Delay, Rise Time and Fall Time
d
Figure 6 Load Circuit of Open-Drain Driver
fi
S1
50k
C
o
15pF
Open
n
50k
From Output
Under Test
2×Vcco
S1
tPZL/tPLZ
(tdis)
2 × Vcco
tPHZ/tPZH
(ten)
Open
in
ic
TEST
tPLZ and tPHZ are the same as tdis.
2.
tPZL and tPZH are the same as ten.
3.
VCCI is the VCC associated with the input port.
4.
VCCO is the VCC associated with the output port.
5.
The resistance and Capacitance values at output notes above are the total effective values.
a
w
1.
Figure 7 Load Circuit for Enable-Time and Disable-Time Measurement
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
tw
Data in
0.5×VCCI
0.5×VCCI
Data in
tPLH
tPHL
0.5×VCCO
0.9×VCCO
0.9×VCCO
0.1×VCCO
0.1×VCCO
0.5×VCCO
Data out
tr
tf
a
l
The input pulses should have the following characteristics:
ti
1. fIN ≤10MHz.
d
e
Figure 8 Timing Parameter Definition
n
2. dv/dt ≥ 1V/ns.
VCCA/2
VCCA/2
n
fi
OE input
tPZL
o
Output
Waveform 1
S1 at 2×VCCO(1)
VCCA
0V
tPLZ
VOH
C
VCCO×0.9
VOH×0.9
ic
VOL
tPHZ
tPZH
Output
Waveform 2 (2)
S1 at OPEN
VOH×0.1
VOH
VCCO×0.1
in
0V
(1) The Waveform 1 is obtained under the condition that the input is low and S1 at 2*V CCO.
Figure 9 Enable and Disable Times
a
w
(2) The Waveform 2 is obtained under the condition that the input and S1 at OPEN.
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Typical Curve TA=25°C
VCCA=3.3V, OE=1, VILA=0.15V
Figure 11
Low-Level Output Voltage
vs Low Level Current
a
Low-Level Output Voltage
vs Low-Level Current
C
o
n
fi
d
e
n
ti
Figure 10
l
VCCA=1.8V, OE=1, VILA=0.15V
VCCA=1.8V, VCCB=3.3V, OE=1, Push-Pull Driver
Signal is translated from A port to B port
ic
Level Translation of a 1MHz Signal
Figure 13
Level Translation of a 2.5MHz Signal
a
w
in
Figure 12
VCCA=1.8V, VCCB=3.3V, OE=1, Push-Pull Driver
Signal is translated from A port to B port
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Detailed Functional Description
AW39104 is a 4-bit high-performance voltage-level translator without direction control signal, which is a noninverting converter and can be used to convert digital signal with mixed-voltage systems. Port A can support
I/O voltages from 1.65 V to 3.6 V, while Port B is able to support I/O voltage range from 2.3 V to 5.5 V. The
chip uses a transmission gate architecture with an rising edge rate accelerator (one-shot), to increase overall
data rate. Also, 10kΩ pull-up resistors are integrated in the chip, which ensures the chip not only supports
push-pull applications but also can be used in open-drain applications directly.
One-shot Accelerator
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The One-Shot rising edge accelerator circuit speeds up the rising edge to help increasing the chip's data rate.
Once the chip has detected the rising edge of the input signal from low to high, the one-shot circuit generates
a pulse signal of approximately 25ns, which enables the internal pull-up PMOS transistor between power
supply and output, thereby accelerating the output port from low to high. During this acceleration phase, the
output resistance of the driver is reduced from 10kΩ to approximately 60Ω. While detecting the output has
been turned up, the one-shot pulse signal is finished and pull-up PMOS transistor is quickly turned off. This
architecture reduces the average dynamic power consumption of the chip while allowing it to meet different
drive requirements.
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Gate Bias
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For the bidirectional voltage translator AW39104, a NMOS switch transistor is used between the input and
output. When translating high level, the NMOS transistor is turned off, and the input and output terminals are
isolated so that they do not impact each other. When the low level is translated, the NMOS switch transistor is
fully turned on, so that the output terminal can be quickly pulled down to the low voltage level. Therefore, the
gate bias voltage of the NMOS switch transistor is set to a fixed value about VCCA+VTH. It is also because of
this architecture that VCCA≤VCCB needs to be guaranteed in the applications.
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Enable Control
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Input Driver
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The AW39104’s OE pin can disable the chip by setting OE to low voltage level, allowing all I/O to operate in
the Hi-Z state. The disable time (tdis) represents the delay time from OE going low to the chip turns to Hi-Z
state. In the Hi-Z state, the chip consumes ultra-low current. And the enable time (ten) indicates the delay
from OE going high to the chip working in translation state. Meanwhile, OE is recommended to be tied to GND
through a pull-down resistor to ensure the high-impedance state during power up or power down. The minimum
value of the resistor is determined by the current-sourcing capability of the driver.
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The rising edge time of the signal (trA, trB) and propagation delay from low to high (tPLH) are determined by the
rising edge rate of the input signal, the ONE-SHOT accelerator’s pull-up capability, and the capacitive load of
the port. The falling edge time of the signal (t fA, tfB) depends on the falling edge rate of the input signal, the
output impedance of the external driver, and the capacitive load on the data line. Similarly, t PHL and the
maximum data rate also depend on the output impedance of the external driver. So, the test conditions for t rA,
trB, tfA, tfB, tPLH, tPHL and maximum data rate in the data sheet are that the output impedance of the external
driver is less than 50Ω.
Output Load
It is recommended that a PCB layout with short PCB layout length:
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
1. Avoid excessive capacitive load triggers ONE-SHOT circuit falsely;
2. It can ensure that the round trip delay of any reflection is less than a single ONE-SHOT duration;
3. Improve signal integrity.
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Meanwhile, the pulse width of the ONE-SHOT circuit is approximately 25 ns, which determines the maximum
output load capacitance that the chip can drive. For very heavy output capacitive loads, the one-shot
accelerator will time-out before the output is fully pulled to high level, at which case the signal transmission will
be distorted. So the ONE-SHOT duration design requires a trade-off between dynamic power consumption,
capacitive load driving capability and maximum data rate. The signal tw at the maximum translation rate should
be greater than the maximum pulse width of the ONE-SHOT circuit, and the delay caused by the output
capacitive load should be less than the maximum pulse width of the ONE-SHOT circuit.
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Application Information
VCCA
VCCB
VCCA
VCCB
CVCCA=0.1μF
CVCCB=0.1μF
1.8V
System
Controller
A1
B1
A2
B2
A3
AW39104 B3
A4
B4
3.3V
System
OE
GND
RPD
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Figure 14 AW39104 Application Circuit
AW39104 is a 4-bit voltage-level translator without direction control signal, which is suitable for interfacing
devices or systems operating at different interface voltages with one another. Port A can supports I/O voltages
from 1.65 V to 3.6 V, while Port B is able to support I/O voltage range from 2.3 V to 5.5 V. Also, 10kΩ pull-up
resistors are integrated in the chip, which ensures the chip not only supports push-pull applications but also
can be used in open-drain applications directly.
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VCC Capacitor Selection
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The device is a 4-bit high-performance voltage-level translator that requires adequate power supply decoupling.
Place a low equivalent-series-resistance (ESR) ceramic capacitor, recommend 0.1μF or larger than 0.1μF.
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RPD Selection
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Drive OE pin HIGH to enable the device. If the voltage level of OE pin is low, the device works in Highimpedance mode. OE pin is recommended to be tied to GND through a pull-down resistor to ensure the highimpedance state during power up or power down. OE pin is high impedance without internal pull down resistor,
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customer can choose the resistor value based on the source drive capability and current consumption.
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
PCB Layout Consideration
To make full use of the performance of AW39104, the guidelines below should be followed.
1. CVCCA and CVCCB should be placed on the top layer as close as possible to the VCCA and VCCB pin.
2. The trace of signals should be short enough to avoid any reflection when transmitted.
CVCCA=0.1μF
CVCCB=0.1μF
VCCB
A1
B2
VCCA
A2
B3
OE
A3
B4
GND
A4
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U1
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GPIO
Top layer
2nd layer
2nd layer (GND)
GND on Top layer
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Figure 15 AW39104 Layout Example
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Tape and Reel Information
TAPE DIMENSIONS
REEL DIMENSIONS
P1
P0
P2
K0
W
B0
D1
A0
Cavity
A0：Dimension designed to accommodate the component width
B0：Dimension designed to accommodate the component length
K0：Dimension designed to accommodate the component thickness
W：Overall width of the carrier tape
P0：Pitch between successive cavity centers and sprocket hole
P1：Pitch between successive cavity centers
P2：Pitch between sprocket hole
D1：Reel Diameter
D0：Reel Width
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D0
Pin 1
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QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
Q3
Q4
Q3
Q4
User Direction of Feed
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Q1
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Sprocket Holes
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Pocket Quadrants
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Package Description(POD)
1.370
±0.025
PIN1
CORNER
1.870
±0.025
0.624
MAX
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Top View
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0.025±0.005
0.181
±0.020
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0.381
±0.012
0.120
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0.080
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Side View
1
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in
1.500
TYP
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0.500
TYP
2
3
12X(∅0.236±0.020)
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B
A
0.500
TYP
1.000
TYP
SYMM
℄
Bottom View
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SYMM
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Unit: mm
Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Land Pattern Data
1
3
2
12X(∅0.200)
A
0.500
TYP
B
SYMM
C
D
0.500
TYP
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SYMM
℄
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0.05 MIN
All AROUND
0.05 MAX
All AROUND
SOLDER MASK
OPENING
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SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
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METAL
SOLDER MASK DEFINED
Unit: mm
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NON-SOLDER MASK DEFINED
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Revision History
Date
Change Record
V1.0
Jun. 2019
Official Released
V1.1
Sept. 2019
Update the EC Table
V1.2
Dec. 2019
Update the Definition of VIL
V1.3
Feb. 2020
Add the definition of Pin No.
V1.4
Apr. 2020
Delete the spaces of AW39104 FOR
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Version
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Copyright © 2019 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW39104
Apr. 2020 V1.4
Disclaimer
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and shall have no liability for the consequences of use of
such information.
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
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AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC
Technology product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC
Technology products in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
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Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
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All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
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Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
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Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
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Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC
component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for
any such statements.
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