IP1001C
Preliminary Data sheet
IP1001C Gigabit Ethernet Combo PHY
(TP/Fiber Auto Selection, Packet Counters & RGMII_PW down to 1.8V)
Features
Built-in a
General Description
10BASE-Te/100BASE-TX/1000BASE-T
IP1001C consists of the physical layer device for
TP port
1000BASE-T, 100BASE-TX, and 10BASE-Te and
Built-in a 100BASE-FX/1000BASE-X
Serdes
for
1000BASE-X,
100BASE-FX
Fiber port
applications.
IP1001C
also
offers
RGMII/MII
for
Supports TP and Fiber auto selection
different
types
of
10/100/1000
Mbps
Media
Access
Supports 100BASE-FX and 1000BASE-X
Controller (MAC) interface.
auto detection
Supports IEEE 1588 stamp( two steps)
IP1001C supports TP and Fiber auto setection,
- 32 stamps for RX/TX
100BASE-FX and 1000BASE-X auto detection,
- 8 event trigger stamps support
TTL level signal for SD detection, and Green
- PPS output support
Power. For power saving option, IP1001C supports
TTL level Fiber MAU for SD detection
3 types of power saving modes: IEEE802.3az
Auto-negotiation, auto MDI/MDIX and
(EEE), Smart EEE, APS (auto power saving).
auto polarity correction
Supports IEEE802.3az (EEE) and Smart IP1001C also provides IEEE 1588 stamp function
for precision time application. In addition, IP1001C
EEE
have a built-in high efficiency switching regulator,
Auto Power Saving for link down port
this feature minimizes the power dissipation from
Built-in high efficiency switching regulator
the power conversion, simplifies the power plane
(3.3V->1.08V)
and reduces the system cost.
Supports RGMII/MII
Supports 3.3V/2.5V/1.8V signaling for
IP1001C also supports 3.3V/2.5V/1.8V, and
RGMII/MII
TXCLK and RXCLK delay option for RGMII, This
Supports TX_CLK and RX_CLK delay
feature allows IP1001C to adapt to different chips
option
seamlessly and get the EMI lower when needed...
Supports Loopback mode for diagnostics
Supports RX counter and CRC counter
IP1001C supports useful tools to assist user in
Jumbo frame size up to 16KB at
designing, tools included the loopback mode, RX
10/100/1000 Mbps
counter, and CRC counter .., etc.
On chip termination resistors for the
differential pairs
Supports Interrupt function
Supports 4 Fixed LED modes
Supports 25MHz external crystal or OSC
85 nm process
Package -68 Pin QFN
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Table Of Contents
Features................................................................................................................................................... 1
General Description ................................................................................................................................. 1
1.
Features List ............................................................................................................................. 7
2.
Pin Diagram .............................................................................................................................. 8
3.
Pin description........................................................................................................................... 9
4.
Functional Description ............................................................................................................ 15
4.1
Interface ............................................................................................................................. 15
4.1.1
RGMII/MII .............................................................................................................. 15
4.2
Green Power ...................................................................................................................... 17
4.2.1
IEEE802.3az EEE ................................................................................................. 17
4.2.2
Smart AZ ............................................................................................................... 18
4.2.3
APS (Auto Power Saving) ..................................................................................... 18
4.3
MDI Auto-Crossover and Polarity Correction ..................................................................... 19
4.4
The link priority of the combo port ..................................................................................... 19
4.5
Serial Management Interface (SMI) ................................................................................... 20
4.6
Loopback Mode ................................................................................................................. 21
4.7
Power Input ........................................................................................................................ 22
4.8
LED & PHY Address configuration..................................................................................... 23
4.8.1
LED configuration ................................................................................................. 23
4.8.2
PHY Address configuration ................................................................................... 24
4.9
IEEE 1588 Precision Timing Protocol (PTP)...................................................................... 25
5.
Register Description ................................................................................................................ 26
5.1
GPHY register description ................................................................................................. 26
5.1.1
Control Register (Page0 Reg0) ............................................................................ 26
5.1.2
Status Register (Page0 Reg1) .............................................................................. 27
5.1.3
Identifier Register (Page0 Reg2) .......................................................................... 28
5.1.4
Identifier Register (Page0 Reg3) .......................................................................... 28
5.1.5
Advertisement Register (Page0 Reg4) ................................................................. 28
5.1.6
Link Partner’s Ability Register (Page0 Reg5) ....................................................... 29
5.1.7
Auto-Negotiation Expansion Register (Page0 Reg6) ........................................... 29
5.1.8
Auto-Negotiation Next Page Transmit Register (Page0 Reg7) ............................ 30
5.1.9
Auto-Negotiation Link Partner Next Page Register (Page0 Reg8) ....................... 30
5.1.10
1000BASE-T Control Register (Page0 Reg9) ...................................................... 30
5.1.11
1000BASE-T Status Register (Page0 Reg10) ...................................................... 32
5.1.12
Extended Status Register (Page0 Reg15) ............................................................ 32
5.1.13
Specific Control & Status Register 0 (Page0 Reg16) ........................................... 33
5.1.14
Link Status Register (Page0 Reg17) .................................................................... 34
5.1.15
INT# Interrupt Control Register 0 (Page0 Reg18) ................................................ 35
5.1.16
PME# Interrupt Control Register 0 (Page1 Reg18) .............................................. 35
5.1.17
INT# Interrupt Status Register 0 (Page0 Reg19) .................................................. 36
5.1.18
PME# Interrupt Status Register 1 (Page1 Reg19) ................................................ 36
5.1.19
RX to TX Loopback (Page2 Reg18) ..................................................................... 36
5.1.20
Specific Control & Status Register 1 (Page2 Reg16) ........................................... 37
5.1.21
RX counter Control Register (Page5 Reg16) ....................................................... 37
5.1.22
RX CRC Error Count Register (Page1 Reg17)..................................................... 38
5.1.23
RX Packet Count Register (Page2 Reg17) .......................................................... 38
5.1.24
RX Symbol Error Count Register (Page3 Reg17) ................................................ 38
5.1.25
Page Select Register (Reg20) .............................................................................. 38
5.1.26
Smart AZ Control Register (Page48 Reg21) ........................................................ 39
5.1.27
System Spec Control Register 0 (Page512 Reg16) ............................................. 39
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.2
6.
6.1
6.2
6.3
7.
8.
5.1.28
System Spec Control Register 1 (Page512 Reg19) ............................................. 40
5.1.29
IO Spec Control Register 0 (Page517 Reg16) ..................................................... 40
5.1.30
IO Spec Control Register 1 (Page518 Reg16) ..................................................... 40
5.1.31
IO Spec Control Register 2 (Page519 Reg16) ..................................................... 40
5.1.32
MMD Control Register (Page0 Reg13) ................................................................. 41
5.1.33
MMD Data Register (Page0 Reg14) ..................................................................... 41
5.1.34
EEE PCS Control Register (MMD Reg3.0)........................................................... 41
5.1.35
EEE PCS Status Register (MMD Reg3.1) ............................................................ 42
5.1.36
EEE Capability Register (MMD Reg3.20) ............................................................. 42
5.1.37
EEE Wake Error Counter Register (MMD Reg3.22)............................................. 43
5.1.38
EEE Advertisement Register (MMD Reg7.60) ...................................................... 43
5.1.39
EEE Link Partner Ability Register (MMD Reg7.61) ............................................... 44
Fiber register description ................................................................................................... 45
5.2.1
FX PHY 1000BASE-X Control Register(Page 0 Reg 0) ....................................... 45
5.2.2
FX PHY Status Register (Page 0 Reg 1) .............................................................. 46
5.2.3
FX PHY Identifier Register (Page 0 Reg 2) .......................................................... 47
5.2.4
FX PHY Identifier Register (Page 0 Reg 3) .......................................................... 47
5.2.5
FX PHY 1000BASE-X AN Advertisement Register (Page 0 Reg 4) ..................... 47
5.2.6
FX PHY1000BASE-X AN Link PartnerAbility Base PageRegister(Page0Reg 5) . 48
5.2.7
FX PHY 1000BASE-X AN Expansion Register (Page 0 Reg 6) ........................... 48
5.2.8
FX PHY 1000BASE-X AN Next Page Transmit Register (Page 0 Reg 7) ............ 48
5.2.9
FX PHY 1000BASE-X Link Partner Ability Next Page Register (Page 0 Reg 8) .. 49
5.2.10
FX PHY 1000BASE-X Extended Status Register (Page 0 Reg 15) ..................... 49
5.2.11
FX PHY Spec Control Register 2 (Page 2 Reg 16) .............................................. 50
Electrical Characteristics ......................................................................................................... 51
Absolute Maximum Rating ................................................................................................. 51
AC Characteristics ............................................................................................................. 52
6.2.1
Reset, Clock and Power Source ........................................................................... 52
6.2.2
RGMII Timing ........................................................................................................ 53
6.2.3
MII TimingTransmit................................................................................................ 54
6.2.4
EEPROM Timing ................................................................................................... 55
6.2.5
SMI Timing ............................................................................................................ 56
DC Characteristics ............................................................................................................. 57
6.3.1
DC Characteristic .................................................................................................. 57
6.3.2
Crystal Specifications ............................................................................................ 58
6.3.3
I/O Electrical Characteristics table ........................................................................ 58
6.3.4
I/O internal pull high/low resistance ...................................................................... 58
6.3.5
Power consumption table of Green Power ........................................................... 59
6.3.6
Thermal Data ........................................................................................................ 59
Order Information .................................................................................................................... 60
Package Outline ...................................................................................................................... 61
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
IP1001C 68 Pin Diagram ............................................................................................................ 8
Waveform of RGMII Diagram .................................................................................................... 15
RGMII Application Diagram ....................................................................................................... 16
MII Application Diagram ............................................................................................................ 16
Reset, Clock and Power Source Timing Requirements ............................................................ 52
RGMII Transmit Timing Requirements ...................................................................................... 53
RGMII Receive Timing Specifications ....................................................................................... 53
SMI Timing Requirements ......................................................................................................... 56
68-PIN QFN Dimension ............................................................................................................ 61
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Link sequence of the Combo port ............................................................................................... 19
Fixed LED specific application for direct LED mode .................................................................. 23
PHY Address Configuration ........................................................................................................ 24
Reset, Clock and Power Source Timing Requirements.............................................................. 52
RGMII Transmit Timing Requirements ....................................................................................... 53
RGMII Receive Timing Specifications ......................................................................................... 53
MII Transmit Timing Specifications ............................................................................................. 54
MII Receive Timing Specifications .............................................................................................. 54
RX data cycle Specifications....................................................................................................... 55
Command cycle Specifications ................................................................................................. 55
SMI Timing Requirements ......................................................................................................... 56
DC Characteristic ...................................................................................................................... 57
Crystal Specifications................................................................................................................ 58
I/O Electrical Characteristics..................................................................................................... 58
Thermal Data ............................................................................................................................ 59
Part Number and Package ....................................................................................................... 60
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Revision History
Revision #
IP1001C-DS-R00.01
IP1001C-DS-R00.02
Date
2018.08.20
2018.09.19
Change Description
Initial
Correct the pin names’ typo of pins 11,14 and 15.
Disclaimer
This document probably contains the inaccurate data or typographic error. In order to keep this
document correct, IC Plus reserves the right to change or improve the content of this document.
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
1. Features List
Features
Process
Package
10/100/1000Base-TP
100/1000Base-FX
RGMII/MII
Power Consumption (W)
RGMII Voltage
Built In Regulator
Auto MDI/MDI-X
MDC/MDIO
APS(Auto PW Down)
802.3az
Smart AZ
IEEE 1588
RGMII DDR Timing support
TX/RX Phase Delay setting
Jumbo Frame@ 1 Gbps
PHY Address (Default)
PHY Address (Pin Setting)
PHY Address (Register Setting)
RGMII Pin Sequence reorder
IP1001C
85nm
68 QFN (8*8mm2)
Y
Y
Y
0.81
3.3v/2.5v/1.8v
Switching
Y
Y
Y
Y
Y
PTP
Y
Y
16K Bytes
0
0~7
0~31
Y
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
2. Pin Diagram
Figure 1 IP1001C 68 Pin Diagram
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
3. Pin description
Pin No.
Label
Type
Description
PHY interface(Auto-MDI/MDIX, HP-License)
50,47,44,41
MDI[3:0]-
I/O
Transmit/Receive output/input differential negative
signal
49,46,43,40
MDI[3:0]+
I/O
Transmit/Receive
signal
SIN
I
Receive input differential negative signal
65
output/input
differential
positive
64
SIP
I
Receive input differential positive signal
61
SON
O
Transmit output differential negative signal
62
RGMII/MII
SOP
O
Transmit output differential positive signal
TXD[0:3]
I
RGMII / MII transmit data.
25
TXCTL
I
RGMII transmit control.
It is sampled at both the rising edge and falling edge of
TXC.
The TX_CTL indicates a TX_EN at the rising edge of
TXC. TX_ER is derived from the logical operation of
latched “TX_EN” and the value at the falling edge of
TXC.
In MII mode, TXCTLis regarded as TX_EN
19
TXCLK
I/O
RGMII transmit clock.
MDI speed
Description
125MHz input.
IP1001C utilizes this clock to sample TXD
Gigabit
[3:0] and TX_CTL at both the rising edge
and falling edge of TXC.
25MHz input.
IP1001C utilizes this clock to sample TXD
100Mbps
[3:0] and TX_CTL at both the rising edge
and falling edge.
2.5MHz input.
IP1001C utilizes this clock to sample TXD
10Mbps
[3:0] and TX_CTL at both the rising edge
and falling edge.
In MII mode, TXCLK is 25Mhz and is driven by PHY
RXD[0:3]
O
RGMII /MII Sends Data.
Sends out RXD [3:0] and RX_CTL at both the rising
edge and falling edge of RXCLK.
20,21,22,23
12,13,14,15
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
11
RXCTL
O
RGMII receive control
MDI speed
Description
RX_CTL indicates RX_DV at the rising
edge of RXC. The RX_ER is derived
Gigabit
from the logical operation of latched
RX_DV and the value at the falling edge
of RX_CLK.
In MII mode, RXCTL is regarded as RX_DV.
17
RXCLK
O
RGMII receive clock.
MDI speed
Description
125MHz output.
IP1001C sends out RXD[3:0] and
Gigabit
RX_CTL at both the rising edge and
falling edge of RX_CLK.
25MHz output.
IP1001C sends out RXD[3:0] and
100Mbps
RX_CTL at both the rising edge and
falling edge of RX_CLK.
2.5MHz output.
IP1001C sends out RXD[3:0] and
10Mbps
RX_CTL at both the rising edge and
falling edge of RX_CLK.
In MII mode, RXCLK is 25Mhz and is driven by PHY
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IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Pin description (continue)
Pin No.
Label
Type
Description
EEPROM
29
EE_CLK
O
Serial EEPROM clock output
28
EE_DAT
I/O
Serial EEPROM data
30
LED_CLK
O
Serial LED CLK
31
Direct LED
LED_DAT
I/O
Serial LED data
DIRECT_LED
O
Direct LED status drive output
Direct LED 6~1 for IP1001C
7
MDC
I
Serial management Clock
It’s recommended that add a 30pf capacitor to ground
for noise filtering.
6
MDIO
I/O
Serial LED
36,35,34,33,31,30
SMI
Serial management I/O Data
It’s recommendation that add a 1.5K pull up resistor
connecting to VDDIO_IN1(pin16) and a 30pf capacitor
connecting to ground.
Miscellaneous
58,59
X1,X2
I/O
67
RESET
I
System reset (low active)
Should be kept at “low” for at least 10 microseconds.
The input voltage should be not higher than 3.3V
18
SCAN
I
Scan input
52
66
SWR_Vout
SD
O
I
SWR out 1.08V, Switching regulator voltage out
Fiber signal detection, low active
55
ISET
I
Band gap , must be connect 6.19K resister to GND
38
OP_mode
I
The pin must be pulled down by 4.7K resistor for
normal mode.
4
1588_EVENT
I
1588 Event
Event trigger source input.
5
1588_PPS
O
1588 PPS
Pulse per second reference output or clock/trigger
output
68,57,51,10,8,3,
2,1
NC
Crystal input/output
Not connect
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IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Pin description (continue)
Pin No.
Label
Type
Description
IP1001C
Power On setting. The state of these pins will be latched upon reset.
5
RGMII/MII_set
IL, PU
RGMII/MII_set
0: MII
1: RGMII (Default)
The pin is used to select interface for GMAC.
11
RGMII_dly_rxc
IL, PD
RGMII_dly_rxc
0: 1/4 clock period delay (Default)
1: No delay
The pin is used to set precise RXCLK 2ns delay for
RGMII I/F@ 1G speed. DDR is double data rate to
generate clock and select edge to create precise 2ns
delay@1G speed.
RGMII_Dirve[1:0]
IL, PD
14
RGMII_dly_rx
IL, PD
RGMII_Drive[1:0]
00:4mA (Default)
01:8mA
10:18mA
11: 28mA
The pins are used to adjust diving current ability for
RGMII I/F.
RGMII_dly_rx
0: No Delay (Default)
1: delay+1ns.
The pin is used to adjust RX delay timing for RGMII I/F.
15
RGMII_dly_tx
IL, PD
RGMII_dly_tx
0:No Delay (Default)
1:delay+1ns.
The pin is used to adjust TX delay timing for RGMII I/F.
29
AZ enable
IL, PU
30
100FX_msk_en
IL, PU
AZ enable
0: enable
1: disable (Default)
The pin is used to set that IP1001C will enter store
and forward mode in AZ enable of PHY mode
100FX_msk_en
0: disable
1: enable(Default)
The pin is used to mask 100-FX
33,31
LED_mode[1:0]
IL, PU
12,13
LED direct mode selection
00: direct LED mode3
01: direct LED mode2
10: direct LED mode1
11: direct LED mode0 (Default)
The pins are used to select 4 kinds of fixed LED
modes.
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
34
Serdes_set
IL, PU
37
FX_CFG
IL, PU
38
OP_mode
IL, PU
PHY_addr[2:0]
IL, PD
17,36,35
IL, PU
IL, PU
39
XMII_Pin_Reorder
IL, PU
Serdes_ set
0: reserved
1: Serdes (Default)
The pin is used to set Serdes
FX_CFG
Serdes is set:
0: 1000-X.
1: Auto (100-FX/1000-X) (Default)
The pin is used to select serdes auto detection speed
or fixed 1000-X.
The FX_CFG setting is based on Serdes pin setting.
OP_mode
0: Normal mode ,the pin must be pull down.
1:Test mode.
The pin is used to set to normal mode.
PHY address
011b’: PHY address is 0 (Default)
Others: Refer to Table 3
PHY address of IP1001C is 0~7 by setting these pins.
By setting the related registers is 0~31.
XMII_Pin_Reorder
0: xMII TXD/RXD pin bit3~0
1:xMII TXD/RXD pin reorder from bit 3~0 to 0~3
(Default).
The pin is used to reorder TX/RX path for RGMII/MIII
I/F
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Pin description (continue)
Pin No.
Label
Type
Description
60,54,45
AVDD33
P
3.3V analog VDD power
63,56,48
AVDD10
P
1.08V analog VDD power
32,24,9
DVDD10
P
1.08V digital VDD power
26
VDDIO_REG
P
(LDO_out 2.5V/1.8V) for RGMII/MII/RMII/rMII I/O
power
16
VDDIO_IN1
P
3.3V/2.5V/1.8V I/O power for CPU I/F,SMI I/F usage
The related pins are 4,5,6,7,11~15, 17~23.
27
VDDIO_IN2
P
3.3V/2.5V I/O power for LED6~1 and EEPROM
usage .The related pins are 29,30,31,33~39.
AVSS10
P
Analog GND
Power pin
53, 42
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IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4. Functional Description
4.1 Interface
4.1.1 RGMII/MII
A MAC sends out data TXD[3:0] and control signal TXCTL at the rising and falling edge of TXCLK. Two GMII
like signals TXEN and TXER are embedded in the TXCTL. GMII like information TXD[7:0] is embedded in the
TXD[3:0]. By recognizing the decoded TXEN, TXD[7:0] and TXER, a PHY can capture the correct data
stream.
A PHY sends out data RXD[3:0] and control signal RXCTL at the rising and falling edge of RXCLK. Two GMII
like signals RXDV and RXER are embedded in the RXCTL. GMII like information RXD[7:0] is embedded in
the RXD[3:0]. By recognizing the decoded RXDV, RXD[7:0] and RXER, IP1001C can capture the correct data
stream. IP1001C samples the correct data at the rising edge of RXCLK.
At MII interface, RX_data is output,RXCTL is regards RXDV.TX_data is input,TXCTL is regards TXEN,
TXCLK and RXCLK is 25Mhz and driven by PHY.
TXCLK
TXCTL
TXD[3:0]
GMII's TXEN
TXERR
TXD[3:0]
TXD[7:4]
TXERR = GMII's TXEN (XOR) GMII's TXER
RGMII TX waveform
RXCLK
RXCTL
RXD[3:0]
GMII's RXDV
RXERR
RXD[3:0]
RXD[7:4]
RXERR = GMII's RXDV (XOR) GMII's RXER
RGMII RX waveform
Figure 2 Waveform of RGMII Diagram
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IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
IP1829A
MAC
IP1001C
TXCLK
TXCTL
TXD [ 3 : 0 ]
TXCLK
TXCTL
TXD [3 :0 ]
MDC
MDIO
MDC
MDIO
RXCLK
RXCTL
RXD [3 : 0 ]
RXCLK
RXCTL
RXD [ 3 :0 ]
PHY
Figure 3 RGMII Application Diagram
IP1001C
IP1829A
MAC
TXCLK
TXEN
TXD [ 3 : 0 ]
TXCLK
TXEN
TXD [3 :0 ]
MDC
MDIO
MDC
MDIO
RXCLK
RXDV
RXD [3 : 0 ]
RXCLK
RXDV
RXD [ 3 :0 ]
PHY
Figure 4 MII Application Diagram
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.2 Green Power
IP1001C supports 3 types of power saving modes: IEEE802.3az Energy Efficient Ethernet, Smart EEE,
APS (Auto Power Saving)
4.2.1 IEEE802.3az EEE
IP1001C supports Low Power Idle (LPI) mode in UTP port, which complies with IEEE802.3az EEE.
Running this function, both of IP1001C and its link partner declare the EEE capability in auto-negotiation
phase. If both ends are matched in EEE capability, IP1001C will enter Low Power Idle mode and stop sending
signals onto the cable, when it receives the EEE command from the MAC device.
A MAC device must have the capability of handling the EEE commands if it wants to activate the LPI Mode of
a PHY via the RGMII. The higher layer takes care of memorizing the link partner’s wakeup time and waking up
the link partner before sending data.
The EEE module works well at LPI (Low Power Idle) mode when
1. Link at full-duplex and
2. Auto-negotiation is enabled in both local and remote PHYs and
3. 1000/100Mbps and
4. EEE ability is supported in both local & remote PHYs and.
5. EEE_EN (MMD register 7.60[2:1]) is enabled for EEE function via default value.
IP1001C not only supports EEE ability in 100Mbps but also supports 10BASE-Te in 10Mbps, whose
transmission amplitude is smaller than 10BASE-T but it still can operate well over 100 meters on Category 5
or better types of cable.
This function is default on and it can be enabled or disabled by programming register MMD Reg7.60 [2:1].
LPI mode (Low Power Idle)
data
Idle
Sleep
Refresh
Quiet
Refresh
Quiet
Idle
Data
Quiet
Refresh: Duration PHY sends Refresh symbols for timing recovery and synchronization.
Normal mode
data
Idle
1G PMA-5 signal or
100/10 Mbps MLT3 signal
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Copyright © 2018, IC Plus Corp.
Idle
Data
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.2.2 Smart AZ
IP1001C provides Smart AZ function to conduct EEE function even if it is conjunction with a legacy Ethernet
MAC device, which does not provide any command regarding EEE.
This function is default off and it can be enabled or disabled by programming register Page48 Reg21 [15].
4.2.3 APS (Auto Power Saving)
IP1001C will automatically enter this mode if link is down for more than 2 sec. In this mode, IP1001C will
shutdown unnecessary functions and sends out normal link pulses in a period around 64 ms, much longer
than that specified in IEEE 802.3, rather than fast link pluses to save power. When IP1001C receives any
signal on MDI, it resumes to normal operation.
This function is default on and it can be enabled or disabled by programming register Page0 Reg16 [7].
18/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.3
MDI Auto-Crossover and Polarity Correction
IP1001C implements auto-crossover function, which allows the user to ignore the pin position of TX pair and
Rx pair. If IP1001C is connected to a device that does not implement auto MDI/MDIX crossover, IP1001C will
make the necessary adjustment prior to performing auto-negotiation. If IP1001C interoperates with a device
that implements auto MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 section 40.4.4
determines which device performs the crossover.
The auto MDI/MDIX function is turned on automatically after hardware reset and the designers can disable it
by programming register. The following table shows the pin mapping relationship in both the MDI and MDIX
mode.
Pin
MDI[0] +/MDI[1] +/MDI[2] +/MDI[3] +/-
1000BASE-T
BI_DA+/BI_DB+/BI_DC+/BI_DD+/-
MDI
100BASE-TX 10BASE-Te
TX+/TX+/RX+/RX+/Unused
Unused
Unused
Unused
1000BASE-T
BI_DB+/BI_DA+/BI_DD+/BI_DC+/-
MDIX
100BASE-TX 10BASE-Te
RX+/RX+/TX+/TX+/Unused
Unused
Unused
Unused
IP1001C also performs polarity correction without any manual setting. It corrects polarity error on the receive
pairs in 1000BASE-T, and 10BASE-Te modes automatically.
In 1000BASE-T mode, polarity correction is based on the sequence of idle symbols. In 10BASE-Te mode,
polarity correction is based on the detection the polarity of valid normal link pulse and idle pulse. In
100BASE-TX mode, the polarity does not matter.
4.4 The link priority of the combo port
The IP1001C supported an auto-switching function to manage its Combo port.
And the managed rule is the link priority of the fiber is higher than the TP port.
Table 1 Link sequence of the Combo port
Plugging
Fiber
Fiber
TP
TP
If condition was
TP Non-plugged
TP Plugged
Fiber Non-plugged
Fiber Plugged
Link Result
Fiber
Fiber
TP
Fiber
19/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.5 Serial Management Interface (SMI)
The serial management interface consists of two pins, MDC and MDIO, providing the capability to access to
the registers of IP1001C. MDC is a clock input and runs at a maximum rate of 2.5 MHz. MDIO is a
bi-directional data pin that runs synchronously to MDC. The MDIO pin requires a 5.1-k pull up resistor for
correct state transition. To access to register in IP1001C, MDC should be at least one more cycle than MDIO.
This means that a complete command consists of 32 bits MDIO data and at least 33 MDC clocks, as the
timing sequence depicted below.
Frame
format
Read
Operation
Write
Operation
MDC
z
z
MDIO
1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1..1
idle
op
start code
write
A A A A A R R R R R TA b b b b b b b b b b b b b b b b
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
4 3 2 1 0 4 3 2 1 0
PHY address =
Reg address =
5 4 3 2 1 0
Register data
01h
00h
idle
MDC
MDIO
z
z
z
1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1
idle
op
start code
read
A A A A A R R R R R TA b b b b b b b b b b b b b b b b
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
4 3 2 1 0 4 3 2 1 0
PHY address =
Reg address =
5 4 3 2 1 0
Register data
01h
00h
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Copyright © 2018, IC Plus Corp.
idle
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.6 Loopback Mode
1) PMA Loopback (Page 2 Reg 18 [8] =1).
Physical Layer Device
MAC Device
NIC/
Switch
PCS
SS-SMII/ SMII/
RGMII
RMII/ MII
PMA
RX
TP-MDI
or
TP-MDI
100BASE-FX/
1000BASE-X
IP1001C
IP1001G
Packet
TEST
TOOL
(EX. SmartBit)
Generator
TX
2) PCS Loopback (Page 0 Reg0 [14] =1).
Physical Layer Device
MAC Device
RX
NIC/
Switch
SS-SMII/ SMII/
RGMII
RMII/ MII
PCS
PMA
IP1001G
IP1001C
TP-MDI
or
TP-MDI
100BASE-FX/
1000BASE-X
Packet
TEST
TOOL
(EX. SmartBit)
Generator
TX
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.7 Power Input
IP1001C requires 3 levels of power sources for normal operation. These 3 levels of power provide 5 kinds of
circuit as described in the table.
Power source
Related circuit
AVDD33
3.3V used for analog circuit.
AVDD10
1.08V used for analog circuit.
DVDD10
1.08V used for digital circuit.
DVDD_IO
Wide range power source used for
RGMII /MII I/O interface.
The typical power inputs for AVDD33 and DVDD10/AVDD10 are 3.3V and 1.08V respectively; while the power
input of DVDD_IO may range from 3.3V to 1.8V, if the RGMII I/O supply voltage of MAC side is the same as
DVDD_IO.
For AVDD33 and DVDD10/AVDD10 power inputs, it is recommended to place a ferrite bead to separate both
power sources, even they are at the same power level. These ferrite beads can avoid the noise coupling
between the digital/analog power paths to increase the system stability.
IP1001C includes a high efficiency switching regulator to convert 3.3V to 1.08V. Either the built-in switching
regulator or the external 1.08 voltage power can be used as supply source, depending on the designer’s
choice.
SW R Vout
1 .0 8 V (c o n n e c te d
to V O U T )
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.8 LED & PHY Address configuration
4.8.1 LED configuration
The bit stream is output sequentially through LED_DAT and LED_CLK and its sequence starts from LED bit
6~1 for serial LED mode. In the other word, bit 1 LED status is present on the latest LED bit, as shown in the
table. To store the serial LED stream, a serial-to-parallel shift register should be used. IP1001C also supports
direct LED mode to directly drive LED without ultra glued logic for low cost need.
IP1001C supports 4 kinds of fixed LED usage for specific LED application at direct LED mode, please refer to
the following table.
Table 2 Fixed LED specific application for direct LED mode
Fixed
1
2
3
4
5
6
LED
mode
FDX/COL-TP
0
L/A-TP
G-L-TP
L/A-FX
Reserved
Reserved
1
L-TP
(speed)
ACT-TP
FDX/COL_TP
L-FX
/ACT-FX
FDX/COL-FX
2
G-L-TP
10/100-L-TP
ACT-TP
G-L-FX
100-L-FX
ACT-FX
(speed)
(speed)
(speed)
(speed)
Reserved
Reserved
Reserved
Reserved
3
Reserved
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Copyright © 2018, IC Plus Corp.
Reserved
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.8.2 PHY Address configuration
IP1001C only responds to a command through SMI with correct PHY address. Before accessing the
register of IP1001C, initial PHY address should be configured to 0~7 with pin PHY_addr0, PHY_addr1,
PHY_addr2 in advance. The value on PHY_addr pins is latched at the end of power on reset. In addition to
responding to a command with PHY address the same as that of IP1001C,
Table 3 PHY Address Configuration
Pin Name
Initial
PHY
Address
PHY_addr2 PHY_addr1 PHY_addr0
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
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Copyright © 2018, IC Plus Corp.
0(default)
1
2
3
4
5
6
7
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
4.9 IEEE 1588 Precision Timing Protocol (PTP)
IP1001C implements the precision timing protocol (including IEEE1588/IEEE802.1as) function. For the PTP
application, IP1001C uses the PTP dedicated hardware to capture the timestamp of PTP frame and store
them into internal buffer; the software processes the various protocol message and co-work with PTP
dedicated hardware.
To synchronous the master clock, IP1001C offers the adjustable real time clock (RTC), which could
increases, decreases the clock frequency and set the specific time-value into RTC. If the PTP packet is
detected, the PTP dedicated hardware will capture the time-value of SFD position for PTP or event signal.
After the PTP synchronization process, the CPU uses the ingress/egress time-stamp to obtain the
compensation parameter. Then, the CPU will pass the relating compensation value into PTP dedicated
hardware. After the long duration, the PTP dedicated RTC is synchronous with the remote master clock.
P1001C supports 32 depth timestamp FIFO(16 for ingress, 16 for egress) to record PTP time-stamp. When all
time stamps are occupied, user also set overwrite bit enable to over write time stamps cyclically. Another,
IP1001C also supports 8 time stamps for incoming event trigger signal.
For the monitor system application, IP1001C support three different output synchronous signals. These output
signals are pulse-per second, the programming clock duration signal and trigger-out signal. Further, please
refer to PTP application note in detail.
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5. Register Description
Abbreviation description
Abbreviation
SC
LH
LL
RO
R/W
NA
HW Reset
SW Reset
Description
Self-Clear.
Latched High.
Latched Low.
Read Only.
Read and Write.
Not Affected.
Reset by RESET# (RESET) pin.
Reset by register 0 bit 15.
5.1 GPHY register description
5.1.1 Control Register (Page0 Reg0)
Bit
Name
[5:0]
Reserved
6
7
8
9
10
11
12
13
14
15
Description
RO
Bit 6 Bit 13
0
0
10Mb/s
Speed Selection
0
1
100Mb/s
(MSB)
1
0
1000Mb/s
1
1
Reserved
1: Enable COL signal test.
Collision Test
0: Disable COL signal test.
1: Full duplex.
Duplex Mode
0: Half duplex.
1: Restart Auto-Negotiation Process.
Restart Auto-NEG
0: Normal operation.
1:Isolate PHY from RGMII electrically,
Isolate
But MDC/MDIO is still active.
0: Normal operation
Link is down; only Management Interface and
logical active.
Power Down
1: Power down.
0: Normal operation.
Auto-Negotiation 1: Enable Auto-Negotiation Process.
Enable
0: Disable Auto-Negotiation Process.
Speed Selection
Please refer to bit 6 for detail information.
(LSB)
1: Enable PCS loopback mode.
Loopback
0: Disable PCS loopback mode.
1: PHY software reset.
Software Reset
0: Normal operation.
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Copyright © 2018, IC Plus Corp.
Type
R/W
HW
SW
Reset Reset
Always 0
1
NA
R/W
0
0
R/W
1
NA
R/W
SC
0
0 (SC)
R/W
0
0
R/W
0
0
R/W
1
NA
R/W
0
NA
R/W
0
0
R/W
SC
0
0 (SC)
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.2 Status Register (Page0 Reg1)
Bit
Name
Description
0
Extended
Capability
1
Jabber Detect
2
Link Status
3
Auto-Negotiation
Ability
4
Remote Fault
5
Auto-Negotiation
Complete
6
MF Preamble
Suppression
7
Reserved
8
Extended Status
9
100BASE-T2
Half Duplex
10
100BASE-T2 Full
Duplex
11
10Mb/s Half
Duplex
12
10 Mb/s Full
Duplex
1: Support extended register capabilities.
0: Support basic register set capabilities only.
1: Jabber condition detected.
0: No jabber condition detected.
1: Link is up.
0: Link is down.
1: PHY is able to perform Auto-Negotiation.
0: PHY is not able to perform Auto-Negotiation...
1: Remote fault condition detected
0: No remote fault condition detected.
1: Auto-Negotiation process completed.
0: Auto-Negotiation process not completed.
1: PHY accepts management frames with
preamble suppressed.
0: PHY does not accept management frames with
preamble suppressed.
Ignore when read
1: There is extended status information in Register
15
0: No extended status information in Register 15
1: PHY able to perform half duplex 100BASE-T2
0: PHY not able to perform half duplex
100BASE-T2
1: PHY able to perform full duplex 100BASE-T2
0: PHY not able to perform full duplex
100BASE-T2
1: PHY able to operate at 10 Mb/s in half duplex
mode
0: PHY not able to operate at 10 Mb/s in half
duplex mode.
1: PHY able to operate at 10Mb/s in full duplex
mode
0: PHY not able to operate at 10Mb/s in full duplex
mode.
1: PHY able to perform half duplex 100BASE-TX.
0: PHY not able to perform half duplex 100BASE-TX.
1: PHY able to perform full duplex 100BASE-TX.
0: PHY not able to perform full duplex 100BASE-TX.
1: PHY able to perform 100BASE-T4.
0: PHY not able to perform 100BASE-T4.
13
14
15
100BASE-TX
Half Duplex
100BASE-TX
Full Duplex
100BASE-T4
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Copyright © 2018, IC Plus Corp.
Type
HW
Reset
SW
Reset
RO
1
1
0
0
0
0
RO
1
1
RO
LH
0
0
RO
0
0
RO
Reserved 1
RO
Reserved 0
RO
Reserved 1
RO
Reserved 0
RO
Reserved 0
RO
1
1
RO
1
1
RO
1
1
RO
1
1
RO
Reserved 0
RO
LH
RO
LL
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.3 Identifier Register (Page0 Reg2)
Bit
[15:0]
Name
Description
Organizationally 0000_0010_0100_0011
Unique Identifier Note: IC Plus’s OUI is 0x0090C3
Bit [3:18]
Type
RO
HW
SW
Reset Reset
Always
0x0243
5.1.4 Identifier Register (Page0 Reg3)
Bit
Name
[3:0]
Revision Number
[9:4]
[15:10]
Description
Type
RO
Manufacturer’s 000010
Model Number
Organizationally 000011
Unique Identifier
Bit [19:24]
RO
RO
HW
SW
Reset Reset
Change with
IC revision
Always
000010
Always
000011
5.1.5 Advertisement Register (Page0 Reg4)
Bit
Name
[4:0]
Selector Filed
10BASE-T Half
Duplex
10BASE-T Full
Duplex
100BASE-TX Half
Duplex
100BASE-TX Full
Duplex
5
6
7
8
9
100BASE-T4
10
PAUSE
12
Asymmetric
Pause
Reserved
13
Remote Fault
14
Reserved
15
Next Page
11
Description
5’b00001, supports IEEE 802.3.
1 = 10Base-T full duplex is supported
0 = 10Base-T full duplex not supported
1 = 10Base-T half duplex is supported
0 = 10Base-T half duplex not supported
1 = 100Base-TX half duplex is supported
0 = 100Base-TX half duplex not supported
1 = 100Base-TX full duplex is supported
0 = 100Base-TX full duplex not supported
1 = 100Base-T4 is supported
0 = 100Base-T4 not supported
1 = flow control is supported
0 = flow control is not supported
1 = Asymmetric flow control is supported
0 = Asymmetric flow control is not supported
Ignore when read
1 = Advertise remote fault detection capability
0 = Not advertise remote fault detection capability
Ignore when read
1 = Next pages are supported
0 = Next pages are not supported
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Copyright © 2018, IC Plus Corp.
Type
RO
HW
SW
Reset Reset
00001 00001
R/W
1
1
R/W
1
1
R/W
1
1
R/W
1
1
RO
Reserved 0
R/W
1
1
R/W
0
0
R/W
0
0
R/W
0
0
RO
R/W
Reserved 0
0
0
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.6 Link Partner’s Ability Register (Page0 Reg5)
Bit
Name
[4:0]
Selector Field
10BASE-T Half
Duplex
5
6
7
8
9
10
11
12
13
14
15
Description
Type
RO
1 = 10Base-T is supported by link partner
0 = 10Base-T not supported by link partner
1 = 10Base-T full duplex is supported by link
10BASE-T Full partner
Duplex
0 = 10Base-T full duplex not supported by link
partner
100BASE-TX Half 1 = 100Base-TX is supported by link partner
Duplex
0 = 100Base-TX not supported by link partner
1 = 100Base-TX full duplex is supported by link
100BASE-TX Full partner
Duplex
0 = 100Base-TX full duplex not supported by link
partner
1 = 100Base-T4 is supported by link partner
100BASE-T4
0 = 100Base-T4 not supported by link partner
1 = Flow control is supported by Link partner
PAUSE
0 = Flow control is not supported by Link partner
1 = Asymmetric flow control is supported by Link
Asymmetric
partner
Pause
0 = Asymmetric flow control is NOT supported by
Link partner
Reserved
Ignore when read
1 = Link partner is indicating a remote fault
Remote Fault
0 = Link partner does not indicate a remote fault.
It is Received Code Word Bit 13
1 = Link partner acknowledges reception of local
node’s capability
Acknowledge
0 = No acknowledgement
It is Received Code Word Bit 14.
1 = Next pages are supported by link partner
Next Page
0 = Next pages are not supported by link partner. It
is Received Code Word Bit 15.
HW
SW
Reset Reset
0
0
RO
0
0
RO
0
0
RO
0
0
RO
0
0
RO
0
0
RO
0
0
RO
0
0
RO
Reserved 0
RO
0
0
RO
0
0
RO
0
0
5.1.7 Auto-Negotiation Expansion Register (Page0 Reg6)
HW
SW
Reset Reset
Bit
Name
Description
Type
0
Link Partner
Auto-Negotiation
Able
1: Link partner supports Auto-Negotiation
0: Link partner does not support Auto-Negotiation
RO
0
0
RO
LH
0
0
RO
1
0
RO
0
0
RO
0
0
1
2
3
4
1: A new page has been received
0: A new page has not been received
Local Next Page 1: Local device supports Next Page
Able
0: Local device does not support Next Page
Link Partner Next 1: Link Partner supports Next Page
Page Able
0: Link Partner does not support Next Page
Parallel Detection 1: A fault has been detected via Parallel Detection
Fault
function
Page Received
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
[15:5]
Reserved
0: A fault has not been detected via Parallel
Detection function
Ignore when read
RO
Reserve 0
5.1.8 Auto-Negotiation Next Page Transmit Register (Page0 Reg7)
Bit
[10:0]
11
12
13
14
15
Name
Message/Unformat
ted Field
Toggle
Acknowledge 2
Message Page
Reserved
Next Page
Description
Transmit Code Word Bit 10:0
Transmit Code Word Bit 11
Transmit Code Word Bit 12
Transmit Code Word Bit 13
Transmit Code Word Bit 14
Transmit Code Word Bit 15
Type
HW
SW
Reset Reset
R/W
1
RO
R/W
R/W
RO
R/W
1
0
0
0
0
1
1
Reserved 0
0
0
5.1.9 Auto-Negotiation Link Partner Next Page Register (Page0 Reg8)
Bit
[10:0]
11
12
13
14
15
Name
Message/Unformatt
ed Field
Toggle
Acknowledge 2
Message Page
Acknowledge
Next Page
Description
Received Code Word Bit 10:0
Received Code Word Bit 11
Received Code Word Bit 12
Received Code Word Bit 13
Received Code Word Bit 14
Received Code Word Bit 15
Type
HW
Reset
SW
Rese
t
RO
0
0
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
5.1.10 1000BASE-T Control Register (Page0 Reg9)
Bit
[7:0]
8
9
Name
Reserved
1000BASE-T Half
Duplex
1000BASE-T Full
Duplex
10
Port Type
11
Configuration
Value
12
Manual
Configuration
Enable
[15:13]
Test mode
Description
Ignore when read
Type
R/W
1: Advertise 1000BASE-T half duplex capable
0: Not advertise
1: Advertise 1000BASE-T full duplex capable
0: Not advertise
1: Prefer multi-port device (MASTER)
0: Prefer single-port device (SLAVE)
1: Manual configure as MASTER
0: Manual configure as SLAVE
It is valid only if bit 9.12 is set to 1.
HW
SW
Reset Reset
Reserved to
0x00
R/W
1
0
R/W
1
0
R/W
1
0
R/W
0
0
1: Manual Configuration Enabled
0: Manual Configuration Disabled
R/W
0
0
1000BASE_T test mode defined in IEEE802.3
clause 40.6.9
[15:13]
Mode
000
Normal Mode
001
Test Mode 1 –Transmit waveform test
R/W
000
000
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Test Mode 2 –Transmit Jitter test in
MASTER mode
011
Test Mode 3 –Transmit Jitter test in
SLAVE mode
100 Test Mode 4 –Transmit distortion test
Others Reserved
010
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.11 1000BASE-T Status Register (Page0 Reg10)
Bit
Name
Description
Type
[7:0]
8
9
Idle Error Count
Reserved
Reserved
Link Partner’s
1000BASE-T Half
Duplex Capability
Idle Error Count
Ignore when read
Ignore when read
1: Link Partner is capable of 1000BASE-T half
duplex
0: Link Partner is not capable of 1000BASE-T half
duplex
1: Link Partner is capable of 1000BASE-T full
duplex
0: Link Partner is not capable of 1000BASE-T full
duplex
1: Remote Receiver OK
0: Remote Receiver Not OK
1: Local Receiver OK
0: Local Receiver Not OK
RO
RO
RO
10
11
12
13
14
15
Link Partner’s
1000BASE-T Full
Duplex Capability
Remote Receiver
Status
Local Receiver
Status
MASTER/SLAVE
Configuration
Resolution
MASTER/SLAVE
Configuration Fault
HW
SW
Reset Reset
0x00 0x00
Reserved to 0
Reserved to 0
RO
0
0
RO
0
0
RO
0
0
RO
0
0
1: Local PHY configuration resolved to MASTER
0: Local PHY configuration resolved to SLAVE
RO
0
0
1: MASTER/SLAVE configuration fault detected
0: No MASTER/SLAVE configuration fault
detected
RO
SC
0
0
5.1.12 Extended Status Register (Page0 Reg15)
Bit
Name
[11:0]
Reserved
1000BASE-T Half
Duplex
1000BASE-T Full
Duplex
1000BASE-X Half
Duplex
1000BASE-X Full
Duplex
12
13
14
15
Description
Ignore when read
1: Be able to perform half duplex 1000BASE-T
0: Not able to perform half duplex 1000BASE-T
1: Be able to perform full duplex 1000BASE-T
0: Not able to perform full duplex 1000BASE-T
1: Be able to perform half duplex 1000BASE-X
0: Not able to perform half duplex 1000BASE-X
1: Be able to perform full duplex 1000BASE-X
0: Not able to perform full duplex 1000BASE-X
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Copyright © 2018, IC Plus Corp.
Type
RO
HW
SW
Reset Reset
0x000 0x000
RO
1
1
RO
1
1
RO
0
0
RO
0
0
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.13 Specific Control & Status Register 0 (Page0 Reg16)
Bit
Name
Description
Type
0
Reserved
Do not change these bits when need to perform a
write activity to other bits of this register
R/W
1
Reserved
Do not change these bits when need to perform a
write activity to other bits of this register
R/W
Do not change these bits when need to perform a
R/W
write activity to other bits of this register
Do not change these bits when need to perform a
3
Reserved
R/W
write activity to other bits of this register
1: Force MDI when auto-MDIX is disabled
4
MDIX
R/W
0: Force MDIX when auto-MDIX is disabled
1: Enable auto-MDIX
5
EN_AUTOMDIX
R/W
0: Disable auto-MDIX
Do not change these bits when need to perform a
6
Reserved
R/W
write activity to other bits of this register
1: Enable APS
7
APS_MODE
R/W
0: Disable APS
Do not change these bits when need to perform a
[10:8]
Reserved
R/W
write activity to other bits of this register
1: Enable LBAS® capability
0: Disable LBAS® capability
®
11
LBAS
R/W
*Reference
Down_Speed_Select_Enable
P2R16[11]
Do not change these bits when need to perform a
[15:12]
Reserved
R/W
write activity to other bits of this register
The other Registers are reserved registers. User is inhibited to access to these registers.
abnormal function to write these registers.
[3:2]
Reserved
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Copyright © 2018, IC Plus Corp.
HW
SW
Reset Reset
Pin
settin
NA
g
Pin
settin
NA
g
N/A
N/A
N/A
N/A
0
0
1
1
N/A
N/A
1
1
N/A
N/A
1
1
N/A
N/A
It may introduce
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.14 Link Status Register (Page0 Reg17)
Bit
Name
[9:0]
Reserved
Description
Type
Ignore when read
N/A
1: TX sleep
10
APS TX Sleep
RO
0: TX wake up
0: MDI 1: MDIX
MDI
MDIX
1G 100M 10M
1G
100M 10M
M
DI
A
TX
TX
B
RX
RX
0
M
11
MDI/MDIX
RO
DI
B
RX
RX
A
TX
TX
1
M
DI
C
----D
--2
M
DI
D
----C
--3
1: Link at full duplex
12
Link_Duplex
0: Link at half duplex
RO
It is valid only if bit 15 is 1.
2’b00: link at 10Base-Te
2’b01: link at 100Base-TX
[14:13] Link_Speed[1:0] 2’b10: link at 1000Base-T
RO
2’b11: Reserved
It is valid only if bit 15 is 1
1: link up
15
Link_Status
RO
0: link down
The other Registers are reserved registers. User is inhibited to access to these registers.
abnormal function to write these registers.
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Copyright © 2018, IC Plus Corp.
HW
SW
Reset Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
It may introduce
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.15 INT# Interrupt Control Register 0 (Page0 Reg18)
Bit
Name
Description
Type
[3:0]
4
HW
SW
Reset Reset
N/A
N/A
0
0
Reserved
INT#_Polarity_Change_En
INT#_Crossover_Change_
5
0
0
En
6
INT#_Duplex_Change_En
0
0
7
Reserved
0
0
1=Enable interrupt (INT#)
8
INT#_False_Carrier_En
1
1
0=Disable interrupt(INT#)
9
INT#_Symbol_Error_En
1
1
10
INT#_Link_Change_En
1
1
11
INT#_Nway_Complete_En
1
1
12
INT#_Page_Received_En
1
1
[14:13]
Reserved
N/A
N/A
15
INT#_Autoneg_Error_En
1
1
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
5.1.16 PME# Interrupt Control Register 0 (Page1 Reg18)
Bit
Name
Description
0
Type
HW
SW
Reset Reset
0
0
PME#_WOL_Arp_Pkt_Det
PME#_WOL_Mymac_Addr
1
Must be set WOL_EN enable
0
0
_Det
P512R16 [10] =1 first.
PME#_WOL_Magic_Pkt_
R/W
2
0
0
Det
3
PME#_LPI_Mode_Off
0
0
1=Enable interrupt (PME#)
0=Disable interrupt (PME#)
4
PME#_LPI_Mode_On
0
0
[15:5]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.17 INT# Interrupt Status Register 0 (Page0 Reg19)
HW
SW
Reset Reset
[3:0]
Reserved
0
0
4
INT#_Polarity_Change
0
0
5
INT#_Crossover_Change
0
0
6
INT#_Duplex_Change
0
0
7
Reserved
0
0
8
INT#_False_Carrier
0
0
RO
Read for event status
LH
9
INT#_Symbol_Error
0
0
10
INT#_Link_Change
0
0
11
INT#_Nway_Complete
0
0
12
INT#_Page_Received
0
0
[14:13]
Reserved
0
0
15
INT#_Autoneg_Error
0
0
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
Bit
Name
Description
Type
5.1.18 PME# Interrupt Status Register 1 (Page1 Reg19)
Bit
0
1
2
3
4
[15:5]
Name
PME#_Arp_Pkt_Det
PME#_Mymac_Addr_Det
PME#_Magic_Pkt_Det
PME#_LPI_Mode_Off
PME#_LPI_Mode_On
Reserved
Description
Type
Read for event status
RO
LH
SC
Ignore when read
N/A
HW
SW
Reset Reset
0
0
0
0
0
0
0
0
0
0
N/A
N/A
5.1.19 RX to TX Loopback (Page2 Reg18)
Bit
Name
[7:0]
Reserved
Description
Type
HW
SW
Reset Reset
N/A
N/A
Ignore when read
N/A
1: Enable PMA Rx to Tx loopback mode,
8
PMA_RX2TX_LPBK
TXD = RXD
R/W
0
0
0:Normal mode
[15:9]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.20 Specific Control & Status Register 1 (Page2 Reg16)
Bit
Name
Description
Do not change these bits when need to perform a
write activity to other bits of this register
Reserved
Do not change these bits when need to perform a
[3:2]
write activity to other bits of this register
[10:4]
Reserved
Internal test used
When P0 R16 [11] Enable LBAS® capability is
enabled, this bit is used to select down speed.
1: Select 1G -> 100M->10M speed(Default)
Down to 100Mbps when 1000Mbps link fails,
Down Speed
11
If 100Mbps still cannot link up, will down the
10M Enable
speed to 10Mbps automatically.
0: Select 1G -> 100M speed
Down to 100Mbps when 1000Mbps link fails.
If 100Mbps still cannot link up, will be unlink
[15:12]
Reserved
Internal test used
The other Registers are reserved registers. User is inhibited to access to these
abnormal function to write these registers.
[1:0]
Reserved
Type
HW
SW
Reset Reset
R/W
0x2
1
R/W
0x2
1
R/W
NA
NA
R/W
1
1
R/W
NA
NA
registers. It may introduce
5.1.21 RX counter Control Register (Page5 Reg16)
Bit
Name
0
[11:1]
RX_CNT_EN
Reserved
Description
1=Enable RX counter 0=Disable RX counter
Ignore when read
Select the RX error count done value.
2’b00: 1
2’b01: 255
RXERR_CNTDON 2’b10: 1026
[13:12]
E_SEL
2’b11: 65535
The interrupt(RXERR_INT_SEL) is triggered that
must
met
the
counter
of
RXERR_CNTDONE_SEL
1=RX error count rolls over to zero when count
down.
RXERR_CNT_RE
14
0=RX error count keep the value when count
PEAT
down.
This bit is set to 0 when RXERR_INT_EN = 1
RXERR_CNT_RD 1=RX error count read clear enable
15
CLR_EN
0=RX error count read clear disable
The other Registers are reserved registers. User is inhibited to access to these
abnormal function to write these registers.
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Copyright © 2018, IC Plus Corp.
Type
R/W
R/W
HW
SW
Reset Reset
0
NA
NA
NA
R/W
0x3
NA
R/W
1
NA
R/W
0
NA
registers. It may introduce
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.22 RX CRC Error Count Register (Page1 Reg17)
Bit
[15: 0]
Name
Description
CRC_ERR_CNT RX CRC error count
Type
RO
HW
SW
Reset Reset
0
NA
5.1.23 RX Packet Count Register (Page2 Reg17)
Bit
Name
Description
Type
[15: 0]
PKT_STS_CNT
RX packet count (include CRC good and error
packet)
RO
HW
Reset
0
SW
Rese
t
NA
5.1.24 RX Symbol Error Count Register (Page3 Reg17)
Bit
Name
Description
RX symbol error count
Each symbol error of idle will add the counter by
[15: 0] SYMB_ERR_CNT 1.
Several symbol errors of one data frame will add
the counter by 1
Type
HW
Reset
SW
Rese
t
RO
0
NA
5.1.25 Page Select Register (Reg20)
SW
Rese
t
[9:0]
PAGE_SEL
To select extension page
R/W
0
0
[15:10]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
Bit
Name
Description
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Copyright © 2018, IC Plus Corp.
Type
HW
Reset
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.26 Smart AZ Control Register (Page48 Reg21)
Bit
Name
Description
Type
HW
Reset
SW
Reset
Do not change these bits when need to perform
R/W
N/A
N/A
a write activity to other bits of this register.
Smart AZ Function Enable
15
SAZ_EN
1: Enable Smart AZ Function(default)
R/W
1
1
0: Disable Smart AZ Function
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
[14:0]
Reserved
5.1.27 System Spec Control Register 0 (Page512 Reg16)
Bit
0
1
2
[9:3]
10
11
Name
Description
Type
HW
Reset
1: Set IP1001C to COMA mode
R/W
0: Set IP1001C to normal mode"
1: Enable crystall reset function
XTAL_RESET_ 0: Disable crystall reset function
R/W
EN
Crystall reset function can also be enabled via
EFUSE setting."
BYPASS_mg_ 1: Bypass mg_model_cfg from switch
R/W
model_cfg
0: mg_model_cfg is used"
Reserved
Ignore when read
N/A
INTB_en
1: Enable pin "INTB" function
R/W
Wake on LAN enable
R/W
WOL_En
1: Enable WOL event detection
0
0: Disable WOL event detection
COMA_EN
SW
Reset
0
0
0
0
0
0
N/A
1
N/A
1
0
12
0: Open drain and active low.
1: Output type and active high.
0: Open drain and active low.
14
INTB_type
1: Output type and active high.
15
PMEB_EN
1: Enable pin "PMEB" function
The other Registers are reserved registers. User is inhibited to access to these
abnormal function to write these registers.
13
PMEB_type
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Copyright © 2018, IC Plus Corp.
R/W
0
0
R/W
0
0
R/W
1
1
registers. It may introduce
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.28 System Spec Control Register 1 (Page512 Reg19)
Bit
Name
[4:0]
Reserved
PHY_AD_ALL_E
N
Reserved
PAGE_TWICE_
EN
5
[9:6]
8
[13:9] Reserved
Description
Typ
e
N/A
Ignore when read
PHY_AD_SET=0
and
PHY_AD_ALL_EN=1,
R/W
IP1001C reply PHY address 0~31.
Ignore when read
N/A
"1=Write page register twice when switch page.
R/W
0=Write page register once when switch page."
N/A
Ignore when read
HW
Reset
N/A
SW
Reset
N/A
0
Retain
N/A
N/A
0
N/A
N/A
SAZ 1=Force smart AZ clock turn on.
R/W
0
0=Turn off smart AZ clock when function is disabled.
1=Reply PHY address zero SMI command no
matter what PHY_AD is set.
15
ALL_REPLY_0
R/W
0
N/A
0=Reply unitary PHY address SMI command
based on PHY_AD setting.
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
14
FORCE
CLK ON
5.1.29 IO Spec Control Register 0 (Page517 Reg16)
HW
SW
Reset Reset
[15:0]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
Bit
Name
Description
Type
5.1.30 IO Spec Control Register 1 (Page518 Reg16)
HW
SW
Reset Reset
[15:0]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
Bit
Name
Description
Type
5.1.31 IO Spec Control Register 2 (Page519 Reg16)
HW
SW
Reset Reset
[15:0]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
Bit
Name
Description
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Copyright © 2018, IC Plus Corp.
Type
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.32
Bit
Name
[4:0]
DEVAD
MMD Control Register (Page0 Reg13)
Description
HW
Type Rese
t
R/W
0
SW
Reset
Device Address
0
Reserved
[13:5]
Reserved
RO
0
0
Write as 0, ignore on read
00 = address
[15:1
01 = data, no post increment
Function
R/W
0
0
4]
10 = data, post increment on reads and writes
11 = data, post increment on writes only
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
5.1.33 MMD Data Register (Page0 Reg14)
Bit
Name
Description
Type
[15:0]
Address Data
If 13.15:14 = 00, MMD DEVAD’s address register.
Otherwise, MMD DEVAD’s data register as indicated
by the contents of its address register
R/W
HW
SW
Reset Reset
0
0
Example 1, Read 0.3.20 (Read Data from MMD register 3.20 of PHY address 0):
1.
Write 0.13 = 0x0003 //MMD DEVAD 3
2.
Write 0.14 = 0x0014 //MMD Address 20
3.
Write 0.13 = 0x4003 //MMD Data command for MMD DEVAD 3
4.
Read 0.14
//Read MMD Data from 0.3.20
Example 2, Write 1.7.60 = 0x3210 (Write 0x3210 Data to MMD register 7.60 of PHY address 1):
1.
Write 1.13 = 0x0007 //MMD DEVAD 7
2.
Write 1.14 = 0x003C //MMD Address 60
3.
Write 1.13 = 0x4007 //MMD Data command for MMD DEVAD 7
4.
Write 1.14 = 0x3210 //Write MMD Data 0x3210 to 1.7.60
5.1.34 EEE PCS Control Register (MMD Reg3.0)
Bit
Name
Description
[9:0]
Type
HW
SW
Rese
Reset
t
0
N/A
Reserved
Ignore when read
RO
Clock stop
1 for RGMII RX clock is stopped during LPI mode
10
R/W
1
N/A
enable
0 for RGMII RX clock isn’t stopped during LPI mode
[15:11]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
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Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.35 EEE PCS Status Register (MMD Reg3.1)
Bit
Name
[5:0]
Reserved
Clock stop
capable
Reserved
Description
Type
HW
SW
Rese
Reset
t
N/A
N/A
Ignore when read
N/A
1 for TX MAC may stop the clock during LPI
6
RO
1'
0 for clock not stoppable
7
Ignore when read
N/A
N/A
1 for RX PCS is currently receiving LPI
8
RX LPI indication
RO
0
0 for PCS is not currently receiving LPI
1 for TX PCS is currently receiving LPI
9
TX LPI indication
RO
0
0 for PCS is not currently received LPI
1 for RX PCS has received LPI
10
RX LPI received
RO/LH
0
0 for LPI not received
1 for TX PCS has received LPI
11
TX LPI received
RO/LH
0
0 for LPI not received
[15:12]
Reserved
Ignore when read
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may
abnormal function to write these registers.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
introduce
5.1.36 EEE Capability Register (MMD Reg3.20)
Bit
Name
0
Reserved
100BASE-TX
EEE
1000BASE-T
EEE
Description
Type
HW
SW
Rese
Reset
t
N/A
N/A
Ignore when read
N/A
1 for EEE is supported for 100BASE-TX
1
RO
1'
0 for EEE is not supported for 100BASE-TX
1 for EEE is supported for 1000BASE-T
2
RO
1
0 for EEE is not supported for 1000BASE-T
1 for EEE is supported for 10GBASE-T
3
10GBASE-T EEE
RO
0
0 for EEE is not supported for 10GBASE-T
1000BASE-KX 1 for EEE is supported for 1000BASE-KX
4
RO
0
EEE
0 for EEE is not supported for 1000BASE-KX
10GBASE-KX4 1 for EEE is supported for 10GBASE-KX4
5
RO
0
EEE
0 for EEE is not supported for 10GBASE-KX4
10GBASE-KR 1 for EEE is supported for 10GBASE-KR
6
RO
0
EEE
0 for EEE is not supported for 10GBASE-KR
[15:7]
Reserved
Ignore when read
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may
abnormal function to write these registers.
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Copyright © 2018, IC Plus Corp.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
introduce
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.37 EEE Wake Error Counter Register (MMD Reg3.22)
Bit
[15:0]
Name
Description
Wake_err_count EEE wake error counter
Type
RO
RC
HW
SW
Rese
Reset
t
0
0
5.1.38 EEE Advertisement Register (MMD Reg7.60)
Bit
Name
0
Reserved
1
2
3
4
5
6
Description
Ignore when read
1:for advertise that the 100BASE-TX has EEE
capability
100BASE-TX EEE
0:for Do not advertise that the 100BASE-TX has EEE
capability
1:for advertise that the 1000BASE-T has EEE
capability
1000BASE-T EEE
0:for Do not advertise that the 1000BASE-T has EEE
capability
1:for advertise that the 10GBASE-TX has EEE
capability
10GBASE-T EEE
0:for Do not advertise that the 10GBASE-T has EEE
capability
1:for advertise that the 1000BASE-KX has EEE
1000BASE-KX
capability
EEE
0:for Do not advertise that the 1000BASE-KX has
EEE capability
1:for advertise that the 10GBASE-KX4 has EEE
10GBASE-KX4
capability
EEE
0:for Do not advertise that the 10GBASE-KX4 has
EEE capability
1:for advertise that the 10GBASE-KR has EEE
capability
10GBASE-KR EEE
0:for Do not advertise that the 10GBASE-KR has
EEE capability
Type
N/A
HW
SW
Rese
Reset
t
N/A
N/A
R/W
0
N/A
R/W
0
N/A
RO
0
N/A
RO
0
N/A
RO
0
N/A
RO
0
N/A
[15:7
Reserved
Ignore when read
N/A
N/A
N/A
]
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.1.39 EEE Link Partner Ability Register (MMD Reg7.61)
Bit
Name
0
Reserved
Description
Type
HW
SW
Rese
Reset
t
N/A
N/A
Ignore when read
N/A
1:for link partner is advertising EEE capability for
LP_100BASE-TX 100BASE-TX
1
RO
0
0
EEE
0:for link partner is not advertising EEE capability for
100BASE-TX
1:for link partner is advertising EEE capability for
LP_1000BASE-T 1000BASE-T
2
RO
0
0
EEE
0:for link partner is not advertising EEE capability for
1000BASE-T
1:for link partner is advertising EEE capability for
LP_10GBASE-T 10GBASE-T
3
RO
0
0
EEE
0:for link partner is not advertising EEE capability for
10GBASE-T
1:for link partner is advertising EEE capability for
LP_1000BASE-K 1000BASE-KX
4
RO
0
0
X EEE
0:for link partner is not advertising EEE capability for
1000BASE-KX
1:for link partner is advertising EEE capability for
LP_10GBASE-K 10GBASE-KX4
5
RO
0
0
X4 EEE
0:for link partner is not advertising EEE capability for
10GBASE-KX4
1:for link partner is advertising EEE capability for
LP_10GBASE-K 10GBASE-KR
6
RO
0
0
R EEE
0:for link partner is not advertising EEE capability for
10GBASE-KR
[15:7]
Reserved
Ignore when read
N/A
N/A
N/A
The other Registers are reserved registers. User is inhibited to access to these registers. It may introduce
abnormal function to write these registers.
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Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.2 Fiber register description
Bit
5.2.1 FX PHY 1000BASE-X Control Register(Page 0 Reg 0)
Name
Description
Type
15
Software Reset
14
13
12
Loopback
Speed LSB
AN Enable
see the description of P0 R0.6
1000BASE-X auto negotiation enable
HW
Reset
0
SW
Reset
0
0
Desc
Desc
0
Desc
Desc
R/W
R/W
R/W
SC
R/W
0
0
0
0
0
0
Desc
Desc
R/W
Desc
0
Desc
0
Desc
R/W
RO
0
0x00
0
0x00
R/W
SC
R/W
Desc
Desc
When P0 R0.6=0 and P0 R0.13=1, this bit is
read as 0 and unable to write.
11
10
9
Power Down
Isolate
Restart AN
8
Duplex
7
6
Collision Test
Speed MSB
Fiber duplex mode selection
Duplex
1
: Full duplex
0
: Half duplex
When link up, this bit reflect operating
duplex mode.
Fiber port speed selection
Speed [1:0]
P0
R0.6
P0 R0.13
0
1
: 100BASE-FX
1
0
: 1000BASE-X
other
:Invalid
When link up, these bits reflect operating
speed mode.
Set Speed[1:0] to 2'b01 will disable fiber
speed auto detection function and force to
100BASE-FX mode.
5
4~0
Unidirection
45/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.2.2
FX PHY Status Register (Page 0 Reg 1)
Bit
Name
15
14
100BASE-T4
100BASE-X Full
13
100BASE-X Half
12
11
10
9
10BASE-T Full
10BASE-T Half
100BASE-T2 Full
100BASE-T2
Half
Extended Status
8
7
5
4
Unidirection
Ability
MF Preamble
Suppression
AN Complete
Remote Fault
3
AN Ability
2
Link Status
1
0
Jabber Detect
Extended
Capability
6
Description
Type
Read as 1 when P0 R0.6=0 and P0 R0.13=1
Read as 0 when P0 R0.6=1 and P0 R0.13=0
Read as 1 when P0 R0.6=0 and P0 R0.13=1
Read as 0 when P0 R0.6=1 and P0 R0.13=0
Read as 1 when P0 R0.6=1 and P0 R0.13=0
Read as 0 when P0 R0.6=0 and P0 R0.13=1
Read as 1 when P0 R0.6=1 and P0 R0.13=0
Read as 0 when P0 R0.6=0 and P0 R0.13=1
46/61
Copyright © 2018, IC Plus Corp.
RO
RO
HW
Reset
0
Desc
SW
Reset
0
Desc
RO
Desc
Desc
RO
RO
RO
RO
0
0
0
0
0
0
0
0
RO
Desc
Desc
RO
1
1
RO
1
1
RO
RO
LH
RO
0
0
0
0
Desc
Desc
RO
LL
RO
RO
0
0
0
1
0
1
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.2.3 FX PHY Identifier Register (Page 0 Reg 2)
Bit
Name
Description
Type
15~0
OUI[3:18]
ICPlus's OUI is 0x0090C3
RO
HW
Reset
0x0243
SW
Reset
0x0243
HW
Reset
0x03
0x05
0x0
SW
Reset
0x03
0x05
0x0
5.2.4 FX PHY Identifier Register (Page 0 Reg 3)
Bit
Name
15~10
9~4
3~0
OUI[19:24]
Model Number
Revision
Number
Description
Type
RO
RO
RO
5.2.5 FX PHY 1000BASE-X AN Advertisement Register (Page 0 Reg 4)
Bit
Name
15
14
13~12
11~9
8
7
6
Next Page
5
Full Duplex
Description
Type
Remote Fault
ASM_DIR
Pause
Half Duplex
In IP1001C (media converter mode) this bit is
read as 0 and unable to write.
In IP1001C (media converter mode) this bit is
read as 1 and unable to write.
When P256 R4.6 set to 0 this bit is read as 1
and unable to clear
4~0
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Copyright © 2018, IC Plus Corp.
R/W
RO
R/W
RO
R/W
R/W
Desc
HW
Reset
0
0
0x0
0x0
1
1
Desc
SW
Reset
0
0
0x0
0x0
1
1
Desc
Desc
Desc
Desc
RO
0x00
0x00
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
5.2.6
Name
FX PHY1000BASE-X AN Link PartnerAbility Base PageRegister(Page0Reg 5)
Bit
Description
Type
HW
SW
Reset Reset
15
Next Page
RO
0
0
14
ACK
RO
0
0
13~12 Remote Fault
RO
0x0
0x0
11~9
RO
0x0
0x0
8
ASM_DIR
RO
0
0
7
Pause
RO
0
0
6
Half Duplex
RO
0
0
5
Full Duplex
RO
0
0
4~0
RO
0x00
0x00
Bit
15~4
3
2
1
0
Bit
15
14
13
12
11
10~0
5.2.7 FX PHY 1000BASE-X AN Expansion Register (Page 0 Reg 6)
Name
Description
Type
HW
Reset
RO
0x000
LP NP Able
RO
0
Local NP Able
RO
1
Page
RO/L 0
Received
H
LP AN Able
RO
0
SW
Reset
0x000
0
1
0
Retain
5.2.8 FX PHY 1000BASE-X AN Next Page Transmit Register (Page 0 Reg 7)
Name
Description
Type
HW
SW
Reset Reset
Next Page
R/W
0
0
RO
0
0
Message Page
R/W
1
1
ACK2
R/W
0
0
Toggle
RO
0
Retain
Message/
R/W
0x001 0x001
Unformatted
Field
48/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Bit
15
14
13
12
11
10~0
Bit
15
14
13
12
11~0
5.2.9 FX PHY 1000BASE-X Link Partner Ability Next Page Register (Page 0 Reg 8)
Name
Description
Type
HW
SW
Reset Reset
Next Page
RO
0
0
ACK
RO
0
0
Message Page
RO
0
0
ACK2
RO
0
0
Toggle
RO
0
0
Message/
RO
0x000 0x000
Unformatted
Field
5.2.10 FX PHY 1000BASE-X Extended Status Register (Page 0 Reg 15)
Name
Description
Type
HW
Reset
1000BASE-X
Read as 1 when P256 R0.6=1 and P256 RO
Desc
Full
R0.13=0
Read as 0 when P256 R0.6=0 and P256
R0.13=1
1000BASE-X
Read as 1 when P256 R0.6=1 and P256 RO
Desc
Half
R0.13=0
Read as 0 when P256 R0.6=0 and P256
R0.13=1
1000BASE-T
RO
0
Full
1000BASE-T
RO
0
Half
RO
0x000
49/61
Copyright © 2018, IC Plus Corp.
SW
Reset
Desc
Desc
0
0
0x000
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
Bit
15
5.2.11 FX PHY Spec Control Register 2 (Page 2 Reg 16)
Name
Description
Type
FX_SPEED
_AUTO_DET
1=Enable fiber speed auto detection
0=Disable fiber speed auto detection
Desc
HW
Reset
Desc
SW
Reset
Desc
Desc
Desc
When set P0 R0.6=0 and P0 R0.13=1,
this bit is read as 0 and unable to write.
14
FX_SPEED
_MODE
1=100BASE-FX is selected when fiber Desc
speed auto detection is disabled
0=1000BASE-X is selected when fiber
speed auto detection is disabled
When set P0 R0.6=0 and P0 R0.13=1,
this bit is read as 1 and unable to write.
13
12
11
FX100_SDON_
DIS
FX100_LOCKO
N
_DIS
RL_ERR_RND
_TMR_SEL
10~9
8
FX100_SPEED
_UP
7
FX100_FORCE
_LINK
6
100FX
_REPEATER
5
FX100_FEF
_DIS
4
FX100_BYPAS
S_4B5B
3
FX100_BYPAS
S_DSP_RST
2
FX100_ODD_
PREAM_COMP
1~0
1=Disable SdOn link in 100BASE-FX
0=Enable SdOn link in 100BASE-FX
1=Disable LockOn link in 100BASE-FX
0=Enable LockOn link in 100BASE-FX
R/W
0
Retain
R/W
0
Retain
RL_ERR_RND_TMR_DONE
1=6.4ms~12ms
0=0~5.6ms
R/W
0
Retain
RO
R/W
0
0
Retain
R/W
0
Retain
1=Set 100BASE-FX to repeat mode
R/W
1
Retain
1=Disable 100BASE-FX FEF
0=Enable 100base-FX FEF
1=Bypass 100BASE-FX 4B/5B
R/W
0
Retain
R/W
0
Retain
1=Bypass 100BASE-FX DSP reset
R/W
0
Retain
in R/W
1
Retain
0
Retain
1=100BASE-FX speed up mode
0=100BASE-FX normal mode
1=Force 100BASE-FX link up
1=Compensate
odd
100BASE-FX RX
RO
50/61
Copyright © 2018, IC Plus Corp.
preamble
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6. Electrical Characteristics
6.1 Absolute Maximum Rating
Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to the
device. Functional performance and device reliability are not guaranteed under these conditions. All voltages
are specified with respect to GND.
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Ambient Operating Temperature (Ta)
IC Junction Temperature (Tj)
...................
..................
...................
..................
51/61
Copyright © 2018, IC Plus Corp.
-0.1V to 3.63V
-0.1V to 3.63V
-0.1V to 3.63V
-65C to 150C
0C to 70C
0C to 125C
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.2 AC Characteristics
6.2.1 Reset, Clock and Power Source
Table 4 Reset, Clock and Power Source Timing Requirements
Symbol
Tclk_lead
Trst
Tdiff
Tpwr_lead
Description
Min.
Typ.
Max.
Unit
10
10
-
-
ms
ms
TBD
ms
X1 clock valid period before reset released.
Reset period.
Time difference between AVDD33 and
AVDD10/DVDD10
All power source ready before reset released.
Tdiff
11
ms
Tpwr_lead
AVDD33
AVDD10
DVDD10
X1/OSCIN
RESET#
Trst
Tclk_lead
Figure 5 Reset, Clock and Power Source Timing Requirements
52/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.2.2 RGMII Timing
a. Transmit Timing Requirements
Table 5 RGMII Transmit Timing Requirements
Symbol
TTX_CLK
TTX_CLK
TTX_CLK
Ts0
Th1
Description
Period of transmit clock in Giga mode.
Period of transmit clock in 100M mode.
Period of transmit clock in 10M mode.
TXEN, TXD to TXC setup time.
TXEN, TXD to TXC hold time.
Min.
Typ.
Max.
Unit
1.0
1.0
8
40
400
2.0
2.0
-
ns
ns
ns
ns
ns
TTXCLK
TXC
Th0
Th0
TXCTL, TXD[3:0]
Ts0
Ts0
~2ns
~2ns
Figure 6 RGMII Transmit Timing Requirements
b. Receive Timing
Table 6 RGMII Receive Timing Specifications
Symbol
TRclk3
TRclk3
TRclk3
Td3
Description
Period of receive clock in Giga mode.
Period of receive clock in 100M mode.
Period of receive clock in10M mode.
RXC edge to RXCTL, RXD.
(RXPHASE_SEL=0, no clock delay added.)
RXC edge to RXCTL, RXD.
(RXPHASE_SEL=1, clock delay added.)
Min.
Typ.
Max.
Unit
-
8
40
400
-
ns
ns
ns
-0.5
0
0.5
ns
1.5
2
2.5
ns
TRclk3
RXC
Td3
Td3
RXCTL, RXD[3:0]
Figure 7 RGMII Receive Timing Specifications
53/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.2.3 MII TimingTransmit
Table 7 MII Transmit Timing Specifications
Symbol
TTxClk
TTxClk
TsTxClk
ThtxClk
Description
Transmit clock period 100M MII
Transmit clock period 10M MII
TXEN, TXD to MII_TXCLK setup time
TXEN, TXD to MII_TXCLK hold time
T
Min.
Typ.
Max.
Unit
10
5
40
400
-
-
ns
ns
ns
ns
Min.
Typ.
Max.
Unit
5
40
400
-
22
ns
ns
ns
T x C lk
M II_ T X C L K
T
h T x C lk
T X E N , T X D [3 :0 ]
T
Table 8
Symbol
TRxClk
TRxClk
TdRxClk
s T x C lk
MII Receive Timing Specifications
Description
Receive clock period 100M MII
Receive clock period 10M MII
MII_RXCLK rising edge to RXDV, RXD
T
R x C lk
T
d R x C lk
M II_ R X C L K
R X D V , R X D [3 :0 ]
54/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.2.4 EEPROM Timing
Table 9 RX data cycle Specifications
EEPROM Timing Rx Parameters
Symbol
Description
TSCL
TsSCL
ThSCL
Receive clock period
EEDAT to EECLK setup time
EEDAT to EECLK hold time
Min.
Typ.
Max.
Unit
20
20
20480
-
-
ns
ns
ns
Min.
Typ.
Max.
Unit
-
20480
-
5200
ns
ns
Read Data Cycle
T
SC L
EEC LK
T
hSC L
EED AT
T
sS C L
R e a d d a ta c y c le
Table 10 Command cycle Specifications
EEPROM Timing Tx Parameters
Symbol
TSCL
TdSCL
Description
Transmit clock period
EECLK falling edge to EEDAT
Command Cycle
T
SCL
EEC LK
T
dSC L
EEDAT
C o m a n d c y c le
55/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.2.5 SMI Timing
MDC/MDIO Timing Requirements
Table 11 SMI Timing Requirements
Symbol
Tch
Tcl
Tcm
Tmd
Tmh
Tms
Description
MDC High Time.
MDC Low Time.
MDC period.
MDIO output delay (read from PHY).
MDIO setup time (write to PHY).
MDIO hold time (write to PHY).
Min.
Typ.
Max.
Unit
180
180
400
5
10
10
-
15
-
ns
ns
ns
ns
ns
ns
MDC
Tms
Tmh
MDIO
Write Cycle
MDC
Tcl
Tch
Tmd
Tcm
MDIO
Read Cycle
Figure 8 SMI Timing Requirements
56/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.3 DC Characteristics
6.3.1
DC Characteristic
Table 12 DC Characteristic
Symbol
DVDD_IO_
3.3V
Description
Supply voltage of
analog circuit
Supply voltage of
analog circuit
Supply voltage of
digital circuit
I/O_3.3V supply
voltage
DVDD_IO_
2.5V
I/O_2.5V supply
voltage
2.25V
DVDD_IO_
1.8V
I/O_1.8V
supply voltage
1.8V
AVDD33
AVDD10
DVDD10
Minimum
Typical
Maximum
3.2V
3.3V
3.63V
---
1.08V
---
---
1.08V
---
2.97V
3.3V
3.63V
2.5V
The I/O voltage of both
IP1001C and MAC come
from the same power source.
2.0V
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Copyright © 2018, IC Plus Corp.
2.75V
Remark
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.3.2
Crystal Specifications
Table 13 Crystal Specifications
Item
1
Parameter
Range
Nominal Frequency
25.000 MHz
2
Frequency Tolerance at 25℃
+/- 25 ppm
3
4
Temperature Characteristics
Operating Temperature Range
+/- 25 ppm
0℃ ~ +70℃
5
Load Capacitance
20 pF, or Specify
6
Equivalent Series Resistance
40 ohm Max.
7
Shunt Capacitance
7 pF Max
8
Insulation Resistance
Mega ohm Min./DC 100V
9
Aging Rate A Year
+/- 5 ppm/year
6.3.3
I/O Electrical Characteristics table
Table 14 I/O Electrical Characteristics
Symbol
VIH
VIL
VIH
I/O_2.5V
VIL
VIH
I/O_1.8V
VIL
VOH
I/O
(3.3V/2.5V/1.8V) VOL
LED/
VOH
CLK_OUT
VOL
VIH
X1/OSC
VIL
VIH
RESET#
VIL
I/O_3.3V
6.3.4
Specific Name
(Input High Voltage)
(Input Low Voltage)
(Input High Voltage)
(Input Low Voltage)
(Input High Voltage)
(Input Low Voltage)
(Output High Voltage)
(Output Low Voltage)
(Output High Voltage)
(Output Low Voltage)
(Input High Voltage)
(Input Low Voltage)
(Input High Voltage)
(Input Low Voltage)
Minimum
2.5
--2.0
--1.7
--0.9*DVDD_IO
--0.9*DVDD33
--0.8* DVDD33
-0.5V
0.8*DVDD33
---
Typical
-----------------------------
Maximum
--1.32
--1
--0.8
--0.1*DVDD_IO
--0.1*DVDD33
3.3V +0.5V
0.2*DVDD33
--0.2*DVDD33
I/O internal pull high/low resistance
DVDD_IO
1.8V
2.5V
3.3V
Pull-high
184k ohm
241k ohm
303k ohm
Pull-low
185k ohm
253k ohm
325k ohm
*According DVDD_IO Voltage different, with different I/O internal resistance
58/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
6.3.5
Item
1
2
3
4
Power consumption table of Green Power
1000BASE-T (@25 oC)
TBD
TBD
TBD
TBD
Mode
Active
802.3az LPI
Smart EEE LPI
Auto Power Saving
6.3.6
Thermal Data
Table 15 Thermal Data
Theta Ja
Theta Jc
Conditions
Units
o
55
12.8
2 Layer PCB
C/W
o
24.8
10.7
4 Layer PCB
C/W
We present the thermal resistance on 2L/4L JEDEC PCB using Finite Element Molding (FEM) method
59/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
7. Order Information
Table 16 Part Number and Package
Part No.
IP1001C
Package
68Pin QFN
Notice
60/61
Copyright © 2018, IC Plus Corp.
Sep 19 2018
IP1001C DS-R00.02
IP1001C
Preliminary Data sheet
8. Package Outline
Figure 9 68-PIN QFN Dimension
IC Plus Corp.
Headquarters
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 30071, R.O.C.
TEL : 886-3-575-0275
FAX : 886-3-575-0475
Website: www.icplus.com.tw
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, New Taipei City, Taiwan 22102, R.O.C.
TEL : 886-2-2696-1669
FAX : 886-2-2696-2220
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Sep 19 2018
IP1001C DS-R00.02
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湘ICP备2023018690号
