BL706C-10-Q2I

BL702/704/706 Datasheet Version：2.1 Copyright @ 2021 www.bouffalolab.com BL702/704/706 Datasheet Features • Wireless – Embedded pSRAM (BL704/BL706,optional) – 2.4 GHz RF transceiver • Security – Bluetooth® Specification v5.0 – Secure boot – Bluetooth® Low Energy 1Mbps and 2Mbps – Secure debug ports – Bluetooth® Long Range Coded 500Kbps – QSPI Flash On-The-Fly AES Decryption (OTFAD) - AES-128, CTR+ mode and 125Kbps – Zigbee 3.0, Base Device Behavior, Core Stack R21, Green Power – Support AES 128/192/256 bits – Support MD5, SHA-1/224/256/384/512 – IEEE 802.15.4 MAC/PHY – Support TRNG (True Random Number Generator) – Support BLE/zigbee coexistence – Support PKA (Public Key Accelerator) – Integrated balun, PA/LNA • Peripheral • MCU Subsystem – USB2.0 FS (Full-Speed) device interface – 32-bit RISC CPU with FPU – IR remote control interface – Level-1 cache – One SPI master/slave – One RTC timer update to one year – Two UARTs – Two 32-bit general purpose timers Support ISO 17987(Local Interconnect Network) – Eight DMA channels – CPU frequency configurable from 1MHz to 144MHz – One I2C master – One I2S master/slave – JTAG development support – Five PWM channels – XIP QSPI Flash/pSRAM with hardware encryp- – Quadrature decoder tion support – Key-Scan-Matrix interface • Memory – 12-bit general ADC – 132KB RAM – 10-bit general DAC – 192KB ROM – PIR (Passive Infra-Red) detection – 1Kb eFuse – Ethernet RMII interface(BL704/BL706) – Embedded Flash (optional) BL702/704/706 Datasheet – Camera interface(BL706) 2/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet – 15(BL702)/23(BL704)/31(BL706) Flexible GPIOs (flexible) – Active Tx • Clock • Power Management – External main clock XTAL 32MHz – Active CPU – External low power consumption and the RTC – Idle clock XTAL 32/32.768kHz – Power Down Sleep (flexible) – Internal RC 32kHz oscillator – Hibernate – Internal RC 32MHz oscillator – Off – Internal System PLL – Active Rx – Internal Audio PLL BL702/704/706 Datasheet 3/ 43 @2021 Bouffalo Lab Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Functional Description 2.1 CPU 2.2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.8 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10.1 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.10.2 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.10.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.10.4 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.10.5 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.10.6 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.7 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.8 IR(IR-remote) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.9 USB2.0(Full Speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.10 EMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10.11 QDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10.12 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10.13 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10.14 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 BL702/704/706 Datasheet 4/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 3 Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.1 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.2 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.3 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.4 GPADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Product use 5.1 Moisture Sensitivity Level(MSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 Electro-Static discharge（ESD） . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Package Information(QFN32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Package Information(QFN40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Package Information(QFN48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 Reference Design 10 Top Marking Definition BL702/704/706 Datasheet 5/ 43 @2021 Bouffalo Lab List of Figures 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Clock Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Pin layout (QFN32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Pin layout (QFN40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Pin layout (QFN48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 Classification Profile (Not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 QFN32 Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 QFN40 Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1 QFN48 Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.1 Top Marking Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.1 Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 BL702/704/706 Datasheet 6/ 43 @2021 Bouffalo Lab List of Tables 2.1 Bus Connectiom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 GPIO Muxed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 GPIO Muxed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 UART Signal Mapping(Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 UART Signal Mapping(Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Recommended Power Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 Recommended Temperature Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5 GPADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.6 ADC electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Reference Conditions for Drying Mounted or Unmounted SMD Packages (User Bake: Floor life begins counting at time = 0 after bake) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 Classification Reflow Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 QFN32 Size Description(Units Of Measure=Millimeter) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 QFN32 Size Description(Units Of Measure=Millimeter) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 QFN40 Size Description(Units Of Measure=Millimeter) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.1 QFN40 Size Description(Units Of Measure=Millimeter) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 QFN48 Size Description(Units Of Measure=Millimeter) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 BL702/704/706 Datasheet 7/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 9.1 QFN48 Size Description(Units Of Measure=Millimeter) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 Part Order Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.1 Part Order Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 BL702/704/706 Datasheet 8/ 43 @2021 Bouffalo Lab 1 Overview BL702/BL704/BL706 is highly integrated BLE and zigbee combo chipsets for IoT applications. Wireless subsystem contains 2.4G radio, BLE+zigbee baseband and MAC designs. Microcontroller subsystem contains 32-bit RISC CPU, high-speed cache and memories. Power Management Unit controls ultra-low-power modes. Moreover, variety of security features are supported. Peripheral interfaces include USB2.0, Ethernet(BL704/BL706), IR-remote, SPI, UART, ISO 17987, I2C, I2S, PWM, QDEC, KeyScan, ADC, DAC, PIR, Camera(BL706), and GPIOs. BLE 32-bit RISC CPU USB2.0 USB host IR remote RF SPI Zigbee Cache / RAM / ROM UART ISO 17987 Car System I2C PMU DMA Clock System PLL I2S PWM Timers Crypto Engine Audio PLL XIP Flash Controller Flash HID Device KeyScan RC Clock DAC eFuse XTAL QDEC ADC pSRAM (BL704/BL706) pSRAM Ethernet I/F Camera DVP (BL704/BL706) RJ45 (10/100M) (BL706) PIR GPIO Camera Sensor Fig. 1.1: Block Diagram BL702/704/706 Datasheet 9/ 43 @2021 Bouffalo Lab 2 Functional Description BL702/BL704/BL706 main functions described as follows： eFUSE RISC 32-bit CPU SYSRAM GLB REG PMU ROM Cache TCM RTC Timer QSPI Flash Control DMA Channels x6 SPI UART x2 I2C x8 I2S Crypto Engines USB pSRAM USB2.0 PWM x5 IR-Remote QDEC x3 KYS pSRAM (BL704/BL706) BLE 5.0 General Pinmux EMAC (BL704/BL706) GPIO DAC RF ADC Zigbee 3.0 EINT GPIO CAM (BL706) Bus Fig. 2.1: System Architecture BL702/704/706 Datasheet 10/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 2.1 CPU BL702/BL704/BL706 32-bit RISC CPU contains FPU (floating-point unit) for 32-bit single-precision arithmetic, threestage pipelined (IF, EXE, WB), compressed 16 and 32-bit instruction set, standard JTAG debugger port including 4 hardware-programmable breakpoints, interrupt controller including 64 interrupts and 16 interrupt levels/priorities for low latency interrupt processing. Up to 144MHz clock frequency, can be dynamically configured to change clock frequency, enter the power saving mode to achieve low power consumption. Both zigBee/BLE stack and application run on single 32-bit RISC CPU for simple and ultra-low power applications. CPU performance ~1.46 DMIPS/MHz. ~3.1 CoreMark/MHz. 2.2 Cache BL702/BL704/BL706 cache improves CPU performance to access external memory. Cache memories can be partially or fully configured as TCM (tightly coupled memory). 2.3 Memory BL702/BL704/BL706 memories include: on-chip zero-delay SRAM memories, read-only memories, write-once memories, embedded flash memory (optional), embedded pSRAM (BL704/BL706,optional). 2.4 DMA BL702/BL704/BL706 DMA (direct memory access) controller has eight dedicated channels that manage data transfer between peripherals and memories to improve cpu/bus efficiency. There are four main types of transfers including memory to memory, memory to peripheral, peripheral to peripheral and peripheral to memory. DMA also supports LLI (link list item) that multiple transfers are pre-defined by a series of linked lists, then hardware automatically complete all transfers according to each LLI size and address. DMA supports peripheral USB, UART, I2C, I2S, SPI, ADC and DAC. 2.5 Bus BL702/BL704/BL706 bus fabric connection and memory-map summarized as follows： Table 2.1: Bus Connectiom Slave/ Master CPU Ethernet DMA Crypto Debug Engine SRAM V V V V V Peripheral V - V - V BLE/zigbee V - V - V BL702/704/706 Datasheet 11/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 2.2: Memory Map Module Base Address Size Description RETRAM 0x40010000 4KB Deep sleep memory (Retention RAM) HBN 0x4000F000 4KB Deep sleep control (Hibernate) PDS 0x4000E000 4KB Sleep control (Power Down Sleep) USB 0x4000D800 1KB USB control EMAC 0x4000D000 2KB Ethernet MAC control (BL704/BL706) DMA 0x4000C000 4KB DMA control QSPI 0x4000B000 4KB Flash/pSRAM QSPI control CAM 0x4000AD00 256B CAM control (BL706) I2S 0x4000AA00 256B I2S control KYS 0x4000A900 256B Key-Scan control QDEC2 0x4000A880 64B Quadrature decoder control QDEC1 0x4000A840 64B Quadrature decoder control QDEC0 0x4000A800 64B Quadrature decoder control IRR 0x4000A600 256B IR Remote control TIMER 0x4000A500 256B Timer control PWM 0x4000A400 256B Pulse Width Modulation *5 control I2C 0x4000A300 256B I2C control SPI 0x4000A200 256B SPI master/slave control UART1 0x4000A100 256B UART control (support ISO 17987) UART0 0x4000A000 256B UART control (support ISO 17987) L1C 0x40009000 4KB Cache control eFuse 0x40007000 4KB eFuse memory control SEC 0x40004000 4KB Security engine GPIP 0x40002000 4KB General purpose DAC/ADC/ACOMP interface control MIX 0x40001000 4KB Mixed signal register GLB 0x40000000 4KB Global control register pSRAM 0x24000000 8MB pSRAM memory XIP 0x23000000 8MB XIP Flash memory OCRAM 0x22020000 64KB On-chip memory DTCM 0x22014000 48KB Data cache memory ITCM 0x22010000 16KB Instruction cache memory BL702/704/706 Datasheet 12/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 2.2: Memory Map Module Base Address Size Description ROM 0x21000000 192KB Read-only memory 2.6 Interrupt BL702/BL704/BL706 supports internal RTC wake-up and external GPIO interrupts wake-up. The CPU interrupt controller supports a total of 64 maskable interrupt trigger sources including UART interrupt, I2C interrupt, SPI interrupt, timer interrupt, DMA interrupt, etc. All I/O pins can be configured as external interrupt input mode. The external interrupt supports four trigger types: high level trigger, low level trigger, rising edge trigger and falling edge trigger. 2.7 Boot BL702/BL704/BL706 supports multiple boot options: UART, USB, and Flash. 2.8 Power PMU (power management unit) manages the power of the entire chip and is divided into running, idle, sleep, hibernation and power off modes. The software can be configured to enter sleep mode and wake-up via RTC timer or EINT to achieve low-power sleep and accurate wake-up management. Power down sleep modes are flexible for applications to configure as the lowest power consumption. 2.9 Clock Clock control unit generates clocks to the core MCU and the peripheral SOC devices. The root clock source can be XTAL, PLL or RC oscillator. Dynamic power-saved by proper configurations such as sel, div, en, etc. PMU runs at 32KHz clock to keep system low-power in sleep mode. BL702/704/706 Datasheet 13/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet DIV XTAL32K 11bit CG en f32k_clk RC32K PMU f32k_sel 1 en DIV sel en /8 kys clk(128KHz) DIV gpdac clk (~512KHz) CG sel root_clk_sel[0] xtal_clk 1 xclk RC32M Cnt CG 16bit en DIV CG i2c clk DIV CG spi clk 5bit en 0 sel ir clk (~2MHz) DIV CG 6bit en 8bit DIV 96MHz 72MHz CG 3bit flash clk en sel 57.6MHz CG 120MHz pll_en 0 bclk DIV CG bclk_div bclk_en DIV CG hclk_div hclk_en SOC hclk fclk 1 144MHz 96MHz en pwm clk duty duty clkpll_xtal_rc32m_sel CG en en 1 kys clk(1MHz) i2s clk(~2MHz) CG 32MHz XTAL CG en AUPLL PLL qdec clk(1MHz) en 5bit sel pir 6bit 24.576MHz 32.768MHz 32MHz CG DIV general adc clk CG 1 MCU root_clk_sel[1] pll_sel DIV CG 3bit en uart clk sel /2 48MHz (duty 50/50) CG usb clk en Fig. 2.2: Clock Architecture 2.10 Peripherals Peripherals include USB2.0, Ethernet, IR-remote, SPI, UART, ISO 17987, I2C, I2S, PWM, QDEC, KeyScan, ADC, DAC, PIR, Camera. Each peripheral can be assigned to different groups of GPIOs through flexible configurations. Each GPIO can be used as a general-purpose input and output function. BL702/704/706 Datasheet 14/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 2.10.1 GPIO BL702 includes 15 GPIOs, BL704 includes 23 GPIOs, BL706 includes 31 GPIOs, and each GPIO can be used as a general-purpose input and output function. The pull-up/pull-down/floating can be configured by software. Each GPIO supports interrupt function, interrupt supports rising edge trigger, falling edge trigger, high level trigger and low level trigger. Each GPIO can be set to a high impedance state for power saving in low power consumption mode. 2.10.2 UART Built-in 2 UARTs (UART0 and UART1), and support LIN master/slave function. The working clock of the UART module can be selected as FCLK or 96M, and the maximum baud rate is 8M. Support hardware CTS and RTS signal management. TX and RX have independent FIFOs with a FIFO depth of 128 bytes and support DMA functions. 2.10.3 SPI One SPI interface, which can be configured as master mode or slave mode, and the SPI module clock is BCLK. As a master, the maximum SPI Clock can reach 36MHz. As a slave, the maximum SPI Clcok of the master is 24MHz. The bit width of each frame can be configured as 8 bits/16 bits/24 bits/32 bits. The transmission and reception of SPI has independent FIFO, and the FIFO depth is fixed to 4 frames (that is, if the bit width of the frame is 8 bits, the depth of the FIFO is 4 bytes), and the DMA function is supported. 2.10.4 I2C One I2C interface, support host mode and 7 bit addressing, I2C module clock is BCLK, support standard and fast mode. With device address register, register address register, the length of the register address can be configured as 1 byte/2 bytes/3 bytes/4 bytes. The I2C transceiver has an independent FIFO, the FIFO depth is 2 words, and it supports DMA function. 2.10.5 I2S One I2S interface, support Left-justified/Right-justified/DSP and other data formats, support 8/16/24/32 bit data width, in addition to mono/dual-channel mode, support four-channel mode at the same time. The I2S transceiver has an independent FIFO, and the FIFO depth is 16 frames. When the data width is 16 bits, the FIFO depth can be set to 32 frames. The I2S module has an independent Audio PLL, and supports two types of sampling rates of 48K (and its integer frequency division) and 44.1K (and its integer frequency division). BL702/704/706 Datasheet 15/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 2.10.6 TIMER The TIMER module contains two general-purpose timers and a watchdog timer. The clock source of the generalpurpose timer can be FCLK/32K/1K/XTAL, and the clock source of the watchdog timer can be FCLK/32K/XTAL. Each The counter has an 8-bit frequency divider. Each group of general-purpose timers contains three compare registers, supports compare interrupts, and count mode supports FreeRun mode and PreLoad mode. The bit width of the watchdog timer counter is 16 bits, and it supports two watchdog overflow modes: interrupt and reset. 2.10.7 PWM 5-channel PWM interface, three kinds of clock sources BCLK/XCLK/32K can be selected, the bit width of the frequency divider register is 16 bits, and the bit width of the period register is 16 bits. Supports adjustable output polarity and dual threshold settings to increase the flexibility of pulse output. Support PWM cycle counting interrupt, used to count the number of output pulses, etc. 2.10.8 IR(IR-remote) One infrared remote control, supports two modes of generating and receiving, supports receiving data with fixed protocols NEC and RC-5, and also supports receiving data in any format in pulse width counting mode. The IR module clock source is XCLK, which has powerful infrared waveform editing capabilities and can send out waveforms that conform to various protocols. The transmit power is adjustable in 15 levels, and the receive FIFO depth can reach 64 bytes. 2.10.9 USB2.0(Full Speed) Built-in a device controller compatible with full-speed USB, following the full-speed USB device standard, with 8 endpoints, each of which has a 64-byte deep FIFO, except for endpoint 0, all other endpoints support interrupt /batch /synchronous transmission . With standby /resume function. The 48MHz clock dedicated to USB is directly generated by the internal main PLL. 2.10.10 EMAC EMAC is a 10/100Mbps Ethernet controller (Ethernet Media Access Controller) compatible with IEEE 802.3. Compatible with the MAC layer functions defined by IEEE 802.3, support the PHY of the RMII interface defined by IEEE 802.3, interact with the PHY through MDIO, support 10Mbps and 100Mbps Ethernet, support half-duplex and full-duplex, data transmission and reception are realized through the Buffer Descriptor data structure . EMAC control is embedded with AHB Master, which can read or write data directly from the memory. The Buffer Descriptor data structure is stored in the internal RAM of EMAC. The total number of Buffer Descriptors is up to 128. The user can flexibly configure the number of Buffer Descriptors for transmission and receiving according to the scene. BL702/704/706 Datasheet 16/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 2.10.11 QDEC The chip has built-in three sets of quadrature decoders, which are used to decode the two sets of pulses with a phase difference of 90 degrees generated by the dual-channel rotary encoder into the corresponding speed and rotation. Direction. QDEC clock source can be 32K (f32k_clk) or 32M (xclk), with 16-bit pulse count range (-32768~32767 pulse/sample), with 12 configurable sample periods (32us~131ms per sample at 1MHz) ), with a 16-bit settable report period (0~65535 ample/report). 2.10.12 ADC The chip has a built-in 12bits successive approximation analog-to-digital converter (ADC) with a maximum working clock of 2MHz, supports 12 external analog inputs and several internal analog signal selections, and supports singlechannel conversion and multi-channel scanning modes. ADC can work in two modes of single conversion and multi-channel scanning. It supports 2.0V, 3.2V optional internal reference voltage, and the conversion result is 12/14/16bits (achieved by oversampling) left-justified mode. The ADC has a FIFO with a depth of 32, supports a variety of interrupts, and supports DMA operations. In addition to measuring common analog signals, ADC can also be used to measure power supply voltage. In addition, ADC can also be used for temperature detection by measuring internal/external diode voltage. 2.10.13 DAC The chip has a built-in 10bits digital-to-analog converter (DAC) with a FIFO depth of 1 word and supports 2 DAC modulation outputs. Can be used for audio playback, conventional analog signal modulation, DAC input clock can be selected as 32M or Audio PLL, support DMA to transfer memory to the DAC modulation register, DAC output pin is fixed to ChannelA to GPIO11, ChannelB to GPIO17. 2.10.14 Debug interface Support standard JTAG 4-wire debugging interface, and use debuggers such as Jlink/OpenOCD/CK Link for debugging. BL702/704/706 Datasheet 17/ 43 @2021 Bouffalo Lab 3 Pin Definition 32 31 30 29 28 27 26 25 VDDIO_1 PAD_GPIO_28 PAD_GPIO_27 PAD_GPIO_26 PAD_GPIO_25 PAD_GPIO_24 PAD_GPIO_23 VDDIO_3 BL702 32-pin package includes 11 power pins, 6 analog pins, and 15 flexible GPIO pins. VDDIO_1 1.8V or 3.3V GPIO0-8 / GPIO23-31 3.3V GPIO9-13 VDDIO_3 1.8V or 3.3V GPIO14-22/PAD32-37(Embedded pad) 1 PAD_GPIO_0 VDDIO_2 PAD_GPIO_17 24 2 PAD_GPIO_1 PAD_GPIO_15 23 3 PAD_GPIO_2 PAD_GPIO_14 22 4 PAD_GPIO_7 XTAL_HF_OUT 21 QFN32 (15GPIOs) 5 PAD_GPIO_8 6 VDDBUS_USB XTAL_HF_IN 20 AVDD_RF 19 7 VDDCORE AVDD15 18 8 DCDC_OUT AVDD33_PA 17 VDDIO_2 PAD_GPIO_9 XTAL32K_IN XTAL32K_OUT AVDD33_AON PU_CHIP ANT SW_DCDC 9 10 11 12 13 14 15 16 Fig. 3.1: Pin layout (QFN32) BL704 40-pin package includes 11 power pins, 6 analog pins, and 23 flexible GPIO pins. BL702/704/706 Datasheet 18/ 43 @2021 Bouffalo Lab 33 32 31 VDDIO_3 34 PAD_GPIO_21 35 PAD_GPIO_22 PAD_GPIO_26 36 PAD_GPIO_23 37 PAD_GPIO_24 38 PAD_GPIO_25 39 PAD_GPIO_27 VDDIO_1 40 PAD_GPIO_28 BL702/704/706 Datasheet VDDIO_1 1.8V or 3.3V GPIO0-8 / GPIO23-31 1 PAD_GPIO_0 VDDIO_2 PAD_GPIO_20 30 2 PAD_GPIO_1 PAD_GPIO_19 29 GPIO9-13 3.3V VDDIO_3 1.8V or 3.3V GPIO14-22/PAD32-37(Embedded pad) 3 PAD_GPIO_2 PAD_GPIO_18 28 4 PAD_GPIO_3 PAD_GPIO_17 27 5 PAD_GPIO_7 PAD_GPIO_15 26 QFN40 (23GPIOs) 6 PAD_GPIO_8 PAD_GPIO_14 25 XTAL_HF_OUT 24 7 VDDBUS_USB XTAL_HF_IN 23 8 VDDCORE 9 DCDC_OUT AVDD_RF 22 10 SW_DCDC AVDD15 21 18 19 AVDD33_PA 17 ANT 16 PU_CHIP 15 AVDD33_AON 14 XTAL32K_OUT PAD_GPIO_10 13 XTAL32K_IN PAD_GPIO_9 12 PAD_GPIO_11 VDDIO_2 11 20 Fig. 3.2: Pin layout (QFN40) BL706 48-pin package includes 11 power pins, 6 analog pins, and 31 flexible GPIO pins. BL702/704/706 Datasheet 19/ 43 @2021 Bouffalo Lab 47 46 45 44 43 42 41 40 39 38 37 PAD_GPIO_30 PAD_GPIO_29 PAD_GPIO_28 PAD_GPIO_27 PAD_GPIO_26 PAD_GPIO_25 PAD_GPIO_24 PAD_GPIO_23 PAD_GPIO_22 PAD_GPIO_21 VDDIO_1 48 PAD_GPIO_31 BL702/704/706 Datasheet VDDIO_1 1.8V or 3.3V GPIO0-8 / GPIO23-31 VDDIO_3 1 PAD_GPIO_0 VDDIO_2 2 PAD_GPIO_1 GPIO9-13 3.3V VDDIO_3 1.8V or 3.3V GPIO14-22/PAD32-37(Embedded pad) 36 PAD_GPIO_20 35 3 PAD_GPIO_2 PAD_GPIO_19 34 4 PAD_GPIO_3 PAD_GPIO_18 33 5 PAD_GPIO_4 PAD_GPIO_17 32 QFN48 6 PAD_GPIO_5 PAD_GPIO_16 31 (31GPIOs) 7 PAD_GPIO_6 PAD_GPIO_15 30 8 PAD_GPIO_7 PAD_GPIO_14 29 9 PAD_GPIO_8 XTAL_HF_OUT 28 10 VDDBUS_USB XTAL_HF_IN 27 11 AVDD_RF 26 AVDD15 25 VDDCORE 12 DCDC_OUT 20 21 22 AVDD33_PA 19 ANT 18 PU_CHIP XTAL32K_IN 17 AVDD33_AON PAD_GPIO_12 16 XTAL32K_OUT PAD_GPIO_11 15 PAD_GPIO_10 14 PAD_GPIO_9 VDDIO_2 SW_DCDC 13 23 24 Fig. 3.3: Pin layout (QFN48) Table 3.1: Pin description No Voltage Domain BL702 BL704 BL706 I/O Type Pin Name 1 VDDIO_1 1 1 1 DI/DO PAD_GPIO_0 - 2 VDDIO_1 2 2 2 DI/DO PAD_GPIO_1 - 3 VDDIO_1 3 3 3 DI/DO PAD_GPIO_2 - 4 VDDIO_1 - 4 4 DI/DO PAD_GPIO_3 - 5 VDDIO_1 - - 5 DI/DO PAD_GPIO_4 - 6 VDDIO_1 - - 6 DI/DO PAD_GPIO_5 - 7 VDDIO_1 - - 7 DI/DO PAD_GPIO_6 - 8 VDDIO_1 4 5 8 DI/DO PAD_GPIO_7 - 9 VDDIO_1 5 6 9 DI/DO PAD_GPIO_8 - 10 VDDIO_2 11 12 15 DI/DO PAD_GPIO_9 - 11 VDDIO_2 - 13 16 DI/DO PAD_GPIO_10 - 12 VDDIO_2 - 14 17 DI/DO PAD_GPIO_11 - 13 VDDIO_2 - - 18 DI/DO PAD_GPIO_12 - BL702/704/706 Datasheet 20/ 43 Description @2021 Bouffalo Lab BL702/704/706 Datasheet Table 3.1: Pin description No Voltage Domain BL702 BL704 BL706 I/O Type Pin Name 14 VDDIO_3 22 25 29 DI/DO PAD_GPIO_14 - 15 VDDIO_3 23 26 30 DI/DO PAD_GPIO_15 - 16 VDDIO_3 - - 31 DI/DO PAD_GPIO_16 - 17 VDDIO_3 24 27 32 DI/DO PAD_GPIO_17 - 18 VDDIO_3 - 28 33 DI/DO PAD_GPIO_18 - 19 VDDIO_3 - 29 34 DI/DO PAD_GPIO_19 - 20 VDDIO_3 - 30 35 DI/DO PAD_GPIO_20 - 21 VDDIO_3 - 32 37 DI/DO PAD_GPIO_21 - 22 VDDIO_3 - 33 38 DI/DO PAD_GPIO_22 - 23 VDDIO_1 26 34 39 DI/DO PAD_GPIO_23 - 24 VDDIO_1 27 35 40 DI/DO PAD_GPIO_24 - 25 VDDIO_1 28 36 41 DI/DO PAD_GPIO_25 - 26 VDDIO_1 29 37 42 DI/DO PAD_GPIO_26 - 27 VDDIO_1 30 38 43 DI/DO PAD_GPIO_27 - 28 VDDIO_1 31 39 44 DI/DO PAD_GPIO_28 - 29 VDDIO_1 - - 45 DI/DO PAD_GPIO_29 - 30 VDDIO_1 - - 46 DI/DO PAD_GPIO_30 - 31 VDDIO_1 - - 47 DI/DO PAD_GPIO_31 - 32 VDDIO_3 - - - DI/DO PAD_32 Embedded pad for embedded psram or flash 33 VDDIO_3 - - - DI/DO PAD_33 Embedded pad for embedded psram or flash 34 VDDIO_3 - - - DI/DO PAD_34 Embedded pad for embedded psram or flash 35 VDDIO_3 - - - DI/DO PAD_35 Embedded pad for embedded psram or flash 36 VDDIO_3 - - - DI/DO PAD_36 Embedded pad for embedded psram or flash 37 VDDIO_3 - - - DI/DO PAD_37 Embedded pad for embedded psram or flash 38 AVDD33_AON 12 15 19 Analog XTAL32K_IN 39 AVDD33_AON 13 16 20 Analog XTAL32K_OUT 40 AVDD33_AON 20 23 27 Analog XTAL_HF_IN 41 AVDD33_AON 21 24 28 Analog XTAL_HF_OUT 42 AVDD33_AON 15 18 22 Analog PU_CHIP 43 AVDD15 16 19 23 Analog ANT RF input and output (single pin) 44 - 32 40 48 Power VDDIO_1 Externally powered 3.3V or 1.8V 45 - 10 11 14 Power VDDIO_2 Externally powered 3.3V 46 - 25 31 36 Power VDDIO_3 Externally powered 3.3V or 1.8V 47 - 14 17 21 Power AVDD33_AON Externally powered 3.3V 48 - 17 20 24 Power AVDD33_PA Externally powered 3.3V 49 - 19 22 26 Power AVDD_RF BL702/704/706 Datasheet 21/ 43 Description Crystal oscillator 32.768kHz input Crystal oscillator 32.768kHz output External crystal input, 32MHz External crystal output, 32MHz Chip power-up Externally powered 3.3/1.8/1.5V @2021 Bouffalo Lab BL702/704/706 Datasheet Table 3.1: Pin description No Voltage Domain BL702 BL704 BL706 I/O Type Pin Name Description 50 - 18 21 25 Power AVDD15 Internal LDO output (for internal use only) 51 - 9 10 13 Power SW_DCDC DCDC power 1.8V 52 - 8 9 12 Power DCDC_OUT DCDC power 1.8V 53 - 6 7 10 Power VDDBUS_USB 54 - 7 8 11 Power VDDCORE BL702/704/706 Datasheet 22/ 43 USB power Internal LDO output (for internal use only) @2021 Bouffalo Lab BL702/704/706 Datasheet Table 3.2: GPIO Muxed Pins Pin Name Flash1 I2S SPI CAM (Default /SWAP=1) PAD_GPIO_0 - BCLK MOSI - FS MISO - DIO/DO SS PWM Analog External_PA SIG0 JTAG FRAME_VLD SIG1 Ether_Mac QDEC Key_Scan_In Key_Scan_Drive IR RMII_REF_- QDEC0_a ROW0 COL0 - (Default /SWAP=1) SCL PWM_CH0 - FEM0 TMS/TCK /SIG4 /MOSI PAD_GPIO_2 I2C Master /SWAP=1) PIX_CLK /MISO PAD_GPIO_1 UART2 (Default CLK SDA PWM_CH1 - FEM1 TDI/TDO RMII_TXD[0] QDEC0_b ROW1 COL1 - SCL PWM_CH2 - FEM2 TCK/TMS RMII_TXD[1] QDEC0_led ROW2 COL2 - SDA PWM_CH3 - FEM3 TDO/TDI - QDEC1_a ROW3 COL3 - SCL PWM_CH4 - FEM4 TMS/TCK - QDEC1_b ROW4 COL4 - SDA PWM_CH0 - FEM0 TDI/TDO - QDEC1_led ROW5 COL5 - SCL PWM_CH1 - FEM1 TCK/TMS - QDEC2_a ROW6 COL6 - SDA PWM_CH2 USB_- FEM2 TDO/TDI RMII_RXD[0] QDEC2_b ROW7 COL7 - FEM3 TMS/TCK RMII_RXD[1] QDEC2_led ROW0 COL8 - /SIG5 LINE_VLD SIG2 /SIG6 PAD_GPIO_3 - RCLK_O SCLK PIX_DAT0 /DI PAD_GPIO_4 - BCLK MOSI PIX_DAT1 /MISO PAD_GPIO_5 - FS MISO - DIO/DO SS SIG4 /SIG0 PIX_DAT2 /MOSI PAD_GPIO_6 SIG3 /SIG7 SIG5 /SIG1 PIX_DAT3 SIG6 /SIG2 PAD_GPIO_7 - RCLK_O SCLK - /DI SIG7 /SIG3 DP/ADC_CH6 PAD_GPIO_8 - BCLK MOSI - /MISO SIG0 SCL PWM_CH3 /SIG4 USB_DM/ADC_- 23/ 43 CH0 PAD_GPIO_9 - FS MISO - /MOSI PAD_GPIO_10 - DIO/DO SS SIG1 SDA PWM_CH4 ADC_CH7 FEM4 TDI/TDO - QDEC0_a ROW1 COL9 - SCL PWM_CH0 MICBIAS FEM0 TCK/TMS - QDEC0_b ROW2 COL10 - SDA PWM_CH1 ADC_CH3 FEM1 TDO/TDI - QDEC0_led ROW3 COL11 - SCL PWM_CH2 ADC_CH4 FEM2 TMS/TCK - QDEC1_a ROW4 COL12 - SDA PWM_CH3 - FEM3 TDI/TDO - QDEC1_b ROW5 COL13 - SCL PWM_CH4 ADC_CH5 FEM4 TCK/TMS - QDEC1_led ROW6 COL14 - SDA PWM_CH0 ADC_CH1 FEM0 TDO/TDI - QDEC2_a ROW7 COL15 - SCL PWM_CH1 - FEM1 TMS/TCK - QDEC2_b ROW0 COL16 - SDA PWM_CH2 ADC_- FEM2 TDI/TDO - QDEC2_led ROW1 COL17 /SIG5 - SIG2 /SIG6 PAD_GPIO_11 - RCLK_O SCLK - /DI PAD_GPIO_12 - BCLK MOSI PIX_DAT4 /MISO - FS MISO - /MOSI PAD_GPIO_14 - DIO/DO SS SIG4 /SIG0 SIG5 /SIG1 - SIG6 /SIG2 PAD_GPIO_15 - RCLK_O SCLK - /DI PAD_GPIO_16 - BCLK MOSI - /MISO PAD_GPIO_17 SF1_IO0 FS /SF2_CS2 SIG7 /SIG3 MISO SIG0 /SIG4 PIX_DAT4 /MOSI SIG1 /SIG5 CH2/psw_- IRRX (ir_rx_gpio_sel=1) irrcv @2021 Bouffalo Lab PAD_GPIO_18 SF1_IO1 DIO/DO SS PIX_DAT5 SIG2 SCL PWM_CH3 ADC_CH8 FEM3 TCK/TMS RMII_MDC QDEC0_a ROW2 COL18 /SIG6 PAD_GPIO_19 SF1_CS RCLK_O SCLK PIX_DAT6 /DI PAD_GPIO_20 SF1_IO3 BCLK SF1_CLK FS SDA PWM_CH4 ADC_CH9 FEM4 TDO/TDI RMII_MDIO QDEC0_b ROW3 COL19 /SIG7 MOSI PIX_DAT7 /MISO PAD_GPIO_21 SIG3 MISO /MOSI SIG4 SIG5 /SIG1 IRRX (ir_rx_gpio_sel=3) SCL PWM_CH0 ADC_CH10 FEM0 TMS/TCK RMII_RXERR QDEC0_led ROW4 COL0 /SIG0 - IRRX (ir_rx_gpio_sel=2) IRRX (ir_rx_gpio_sel=4) SDA PWM_CH1 ADC_CH11 FEM1 TDI/TDO RMII_TX_EN QDEC1_a ROW5 COL1 IRRX (ir_rx_gpio_sel=5) BL702/704/706 Datasheet PAD_GPIO_13 SIG3 /SIG7 BL702/704/706 Datasheet Table 3.2: GPIO Muxed Pins Pin Name Flash1 I2S SPI CAM (Default /SWAP=1) PAD_GPIO_22 SF1_IO2 DIO/DO UART2 I2C (Default Master PWM Analog External_PA /SWAP=1) SS - SIG6 JTAG Ether_Mac QDEC Key_Scan_In Key_Scan_Drive RMII_RX_DV QDEC1_b ROW6 COL2 /SWAP=1) SCL PWM_CH2 IRTX FEM2 TCK/TMS /SIG2 PAD_GPIO_23 SF2_IO2 RCLK_O SCLK PIX_DAT4 /DI PAD_GPIO_24 SF2_IO1 BCLK MOSI PIX_DAT5 SF2_CS FS MISO SF2_IO3 DIO/DO SDA PWM_CH3 IRTX FEM3 TDO/TDI - QDEC1_led ROW7 COL3 PIX_DAT6 SS SIG1 SCL PWM_CH4 - FEM4 TMS/TCK RMII_MDC QDEC2_a ROW0 COL4 SIG2 SDA PWM_CH0 - FEM0 TDI/TDO RMII_MDIO QDEC2_b ROW1 COL5 SF2_CLK RCLK_O SCLK - /DI PAD_GPIO_28 SF2_IO0 BCLK SCL PWM_CH1 - FEM1 TCK/TMS RMII_RXERR QDEC2_led ROW2 COL6 MOSI PIX_DAT4 - FS MISO - DIO/DO SDA PWM_CH2 - FEM2 TDO/TDI RMII_TX_EN QDEC0_a ROW3 COL7 PIX_DAT5 SS SIG5 SCL PWM_CH3 - FEM3 TMS/TCK RMII_RX_DV QDEC0_b ROW4 COL8 SIG6 SDA PWM_CH4 - FEM4 TDI/TDO - QDEC0_led ROW5 COL9 - RCLK_O SCLK PIX_DAT7 24/ 43 /DI SIG7 IRRX (ir_rx_gpio_sel=13) SCL PWM_CH0 - FEM0 TCK/TMS - QDEC1_a ROW6 COL10 /SIG2 PAD_GPIO_31 IRRX (ir_rx_gpio_sel=12) /SIG1 PIX_DAT6 IRRX (ir_rx_gpio_sel=11) /SIG0 /MOSI PAD_GPIO_30 SIG4 IRRX (ir_rx_gpio_sel=10) /SIG7 /MISO PAD_GPIO_29 SIG3 IRRX (ir_rx_gpio_sel=9) /SIG6 PAD_GPIO_27 IRRX (ir_rx_gpio_sel=8) /SIG5 PIX_DAT7 IRRX (ir_rx_gpio_sel=7) /SIG4 /MOSI PAD_GPIO_26 SIG0 IRRX (ir_rx_gpio_sel=6) /SIG3 /MISO PAD_GPIO_25 SIG7 IR (Default IRRX (ir_rx_gpio_sel=14) SDA /SIG3 PWM_CH1 - FEM1 TDO/TDI - QDEC1_b ROW7 COL11 IRRX (ir_rx_gpio_sel=15) 1 There are 2 groups of Flash, and the smallest selection unit is group, which is configured according to group when used. In Dual CS mode, PAD_GPIO_17 can be configured as SF2_CS2 function. 2 The default UART signal mapping table is shown below. BL702/704/706 Datasheet @2021 Bouffalo Lab BL702/704/706 Datasheet Table 3.3: UART Signal Mapping(Default) UART Signal uart_sig_x_sel Mapping Signal UART_SIG0 uart_sig_0_sel=0 UART0_RTS UART_SIG1 uart_sig_1_sel=1 UART0_CTS UART_SIG2 uart_sig_2_sel=2 UART0_TXD UART_SIG3 uart_sig_3_sel=3 UART0_RXD UART_SIG4 uart_sig_4_sel=4 UART1_RTS UART_SIG5 uart_sig_5_sel=5 UART1_CTS UART_SIG6 uart_sig_6_sel=6 UART1_TXD UART_SIG7 uart_sig_7_sel=7 UART1_RXD Note: UART_SIG0-UART_SIG7 can be configured as any of 8 Mapping Signals. For example: UART_SIG0 can also be configured as UART_RXD. The specific signal mapping example is shown in the table below. Table 3.4: UART Signal Mapping(Example) UART Signal uart_sig_x_sel Mapping Signal UART_SIG0 uart_sig_0_sel=7 UART1_RXD UART_SIG1 uart_sig_1_sel=6 UART1_TXD UART_SIG2 uart_sig_2_sel=5 UART1_CTS UART_SIG3 uart_sig_3_sel=4 UART1_RTS UART_SIG4 uart_sig_4_sel=3 UART0_RXD UART_SIG5 uart_sig_5_sel=2 UART0_TXD UART_SIG6 uart_sig_6_sel=1 UART0_CTS UART_SIG7 uart_sig_7_sel=0 UART0_RTS BL702/704/706 Datasheet 25/ 43 @2021 Bouffalo Lab 4 Electrical Specifications 4.1 Absolute Maximum Rating Table 4.1: Absolute Maximum Rating Pin Name Min. Max. Unit VDDIO_1 -0.3 3.63 V VDDIO_2 -0.3 3.63 V VDDIO_3 -0.3 3.63 V VSSBUS_USB -0.3 5.5 V AVDD33_AON -0.3 3.63 V AVDD33_PA -0.3 3.63 V AVDD33_RF -0.3 3.63 V 2000 V 125 ◦C ESD Protection (HBM) Storage Temperature -40 4.2 Operating Condition BL702/704/706 Datasheet 26/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 4.2.1 Power characteristics Table 4.2: Recommended Power Operating Range Pin Name Min. Typ Max. Unit VDDIO_1 1.62/1.8 1.8/3.3 1.92/3.63 V VDDIO_2 1.8 3.3 3.63 V VDDIO_3 1.8 3.3 3.63 V VDDBUS_USB 4.5 5 5.5 V AVDD33_AON 1.8 3.3 3.63 V AVDD33_PA 1.4/2.97 1.5/3.3 1.6/3.63 V AVDD33_RF 1.4/2.97 1.5/3.3 1.6/3.63 V 4.2.2 Temperature sensor characteristics Table 4.3: Recommended Temperature Operating Range Item Min. Max. Unit Main Die -40 105 ◦C Multi-Die SiP -40 85 ◦C Temperature 4.2.3 General operating conditions Table 4.4: General Operating Conditions Item Description Min. Typ Max. Unit FCPU CPU/TCM/Cache 0 32 144 MHz 0 32 72 MHz clock frequency FSYS System clock frequency 4.2.4 GPADC characteristics BL702/704/706 Datasheet 27/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 4.5: GPADC characteristics Symbol Parameter Conditions Min Typ Max Units VDD33 Vbat supply voltage 2.3 3.6 V T Working tempreture -40 125 ◦C Current consumption of Ivdd33 ADC on VDD33 PGA1&2 off (2M clock) 150 PGA1&2 on(2M clock) 350 μA ADC input top clock Fclk frequency Clock from SOC 1.5 32 MHz 2 MHz 2.048M(12bit mode) Fsample Sampling rate 32K-128K(14bit mode) 8K-16K(16bit mode) Input conversion Vin voltage range Differential mode 6.4 Single-ended mode 3.2 V(vpp) Total input channel Rin resistance Tcal Calibration time Tpu Power up time Tconv Total conversion time Fsample=2M (16bit mode) 2 KΩ 140 uS 1 uS 12bit mode 1 14bit mode 1 16 14bit mode 2 64 16bit mode 3 128 16bit mode 4 256 1/Fsample 1. 14-bit mode with 16 times average 2. 14-bit mode with 64 times average 3. 16-bit mode with 128 times average 4. 16-bit mode with 256 times average Note: Unless otherwise specified, the parameters given in Table 1 are derived from test under -40 to 125oC, supply AVDD=3.3V, DVDD=1.1V. BL702/704/706 Datasheet 28/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 4.6: ADC electrical characteristic Symbol Parameter DNL 1 Max Units Differential linearity error +/-1 LSB INL 1 Integral linearity error +/-2 LSB Offset Input offset +/-2 LSB Ge 1&2 Gain error +/-1 % ENOB SNDR SNDR Effective number of bits Signal-to-noise-distortion (PGA on) Signal-to-noise-distortion (PGA gain=4) Conditions Min Typ 12bit mode(201KHz input) 9.7 10.5 14bit mode(2.5KHz input) 10.8 11.4 16bit mode(1KHz input) 11.5 12.3 12bit mode(201KHz input) 59 65 14bit mode(2.5KHz input) 66 72.4 16bit mode(1KHz input) 71 76.8 12bit mode(201KHz input) 58 64 14bit mode(2.5KHz input) 64 69.5 16bit mode(1KHz input) 70 74 bit dB dB 1. more test needed 2. after calibration BL702/704/706 Datasheet 29/ 43 @2021 Bouffalo Lab 5 Product use 5.1 Moisture Sensitivity Level(MSL) The moisture sensitivity level of the chip is: MSL3. After the vacuum package is opened, it needs to be used up within 168 hours (7 days) at ≤30°C/60%RH, otherwise it needs to be baked and put online. For baking temperature and time, please refer to IPC/JEDECJ-STD-033B01. Table 5.1: Reference Conditions for Drying Mounted or Unmounted SMD Packages (User Bake: Floor life begins counting at time = 0 after bake) Bake @ 90°C Bake @ 40°C ≤5% RH ≤5% RH Bake @ 125°C Package Body Level Exceeding Exceeding Exceeding Exceeding Exceeding Exceeding Floor Life Floor Life Floor Life Floor Life Floor Life Floor Life by >72 h by ≤72 h by >72 h by ≤72 h by >72 h by ≤72 h 2 5 hours 3 hours 17 hours 11 hours 8 days 5 days 2a 7 hours 5 hours 23 hours 13 hours 9 days 7 days 3 9 hours 7 hours 33 hours 23 hours 13 days 9 days 4 11 hours 7 hours 37 hours 23 hours 15 days 9 days 5 12 hours 7 hours 41 hours 24 hours 17 days 10 days 5a 16 hours 10 hours 54 hours 24 hours 22 days 10 days Thickness ≤1.4 mm BL702/704/706 Datasheet 30/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet 5.2 Electro-Static discharge（ESD） • Human Body Model(HBM): 2000V • Charged-Device Model(CDM): 500V 5.3 Reflow Profile For details, please refer to IPC/JEDEC J-STD-020E. Fig. 5.1: Classification Profile (Not to scale) BL702/704/706 Datasheet 31/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 5.2: Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Temperature Min (Tsmin ) 100 °C 150 °C Temperature Max (Tsmax ) 150 °C 200 °C Time (ts ) from (Tsmin to Tsmax ) 60-120 seconds 60-120 seconds Ramp-up rate (TL to Tp ) 3 °C/second max. 3 °C/second max. Liquidous temperature (TL ) 183 °C 217 °C Time (tL ) maintained above TL 60-150 seconds 60-150 seconds Peak package body temperature (Tp ) 240 °C+0/-5 °C 250 °C+0/-5 °C 10-30 seconds 20-40 seconds Ramp-down rate (Tp to TL ) 6 °C/second max 6 °C/second max Time 25 °C to peak temperature 6 minutes max 8 minutes max Preheat/Soak Time (tp )* within 5 °C of the specified classification temperature (Tc ) - Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum. BL702/704/706 Datasheet 32/ 43 @2021 Bouffalo Lab 6 Reference Design Antenna 3.3V ANT VDD33 AVDD33_2 CHIP_EN AVDD33_1 VDDIO_2 VDDCORE GPIOs 15/23/31x GPIO AVDD15_RF BL702/704/706 AVDD18_RF VDDIO_1 SW_DCDC VDDIO_3 DCDC_OUT XTAL_IN XTAL_OUT XTAL32K_IN 32MHz 1.8V or 3.3V 1.8V or 3.3V XTAL32K_OUT 32.768kHz Fig. 6.1: Reference Design BL702/704/706 Datasheet 33/ 43 @2021 Bouffalo Lab 7 Package Information(QFN32) Fig. 7.1: QFN32 Package drawing Table 7.1: QFN32 Size Description(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 BL702/704/706 Datasheet 34/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 7.1: QFN32 Size Description(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A2 0.50 0.55 0.60 A3 0.20REF b 0.15 0.20 0.25 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 2.80 2.90 3.00 E2 2.80 2.90 3.00 e 0.30 0.40 0.50 H 0.30REF K 0.25REF L 0.25 0.30 0.35 R 0.09 - - c1 - 0.10 - c2 - 0.10 - BL702/704/706 Datasheet 35/ 43 @2021 Bouffalo Lab 8 Package Information(QFN40) Fig. 8.1: QFN40 Package drawing Table 8.1: QFN40 Size Description(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A 0.80 0.85 0.90 A1 0 0.02 0.05 BL702/704/706 Datasheet 36/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 8.1: QFN40 Size Description(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A2 0.60 0.65 0.70 A3 0.20REF b 0.15 0.20 0.25 D 4.90 5.00 5.10 E 4.90 5.00 5.10 D2 3.60 3.70 3.80 E2 3.60 3.70 3.80 e 0.35 0.40 0.45 K 0.20 - - L 0.35 0.40 0.45 R 0.075 - - C1 - 0.12 - C2 - 0.12 - BL702/704/706 Datasheet 37/ 43 @2021 Bouffalo Lab 9 Package Information(QFN48) Fig. 9.1: QFN48 Package drawing Table 9.1: QFN48 Size Description(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A 0.80 0.85 0.90 A1 0 0.02 0.05 BL702/704/706 Datasheet 38/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 9.1: QFN48 Size Description(Units Of Measure=Millimeter) SYMBOL MIN NOM MAX A3 0.20REF b 0.15 0.20 0.25 D 5.90 6.00 6.10 E 5.90 6.00 6.10 D2 4.30 4.40 4.50 E2 4.30 4.40 4.50 e 0.30 0.40 0.50 H 0.35REF K 0.30 0.40 0.50 L 0.30 0.40 0.50 R 0.075 - - BL702/704/706 Datasheet 39/ 43 @2021 Bouffalo Lab 10 Top Marking Definition Temperature code: C/I/H Pin1 Loca�on I Lot number Part number: BL702/4/6(C/S): C:BLE+Zigbee Combo, S:BLE+802.15.4 Slim 00: MSB=flash, 0: no flash, A:4Mb, 1: 8Mb, 3(no use),... LSB=pSRAM, 0:no pSRAM, other:TBD BL702C-A0 Lot Number YYWW-AC Date code Fig. 10.1: Top Marking Definition BL702/704/706 Datasheet 40/ 43 @2021 Bouffalo Lab 11 Ordering Information Show in package BL70xC- 00-Q 2I Environment code : +=RoHS 0/6 , - = RoHS 5 /6 , 1 =RoHS 6 / 6 , 2 = Green Temperature code : C/ I /H Package code: Q(QFN), B(BGA),CSP Band: S: Single-band 2.4G; D: dualband, 2.4G/5G; NA; MSB=flash, 0: no flash, 1: 8Mbit, 4:32Mbit, , A:4Mbit LSB=pSRAM, 0:no pSRAM, other: TBD Part number: C/S: BLE+Zigbee Combo, BLE+802.15.4 Slim, BL70xC-> 702C: QFN32 Zigbee/BLE Combo 702S: QFN32 BLE+802.15.4 Slim(no zigbee stack), Or MCU 704S: QFN40 BLE+802.15.4 Slim(no zigbee stack), Or MCU 706C: QFN48 Zigbee/BLE Combo 706S: QFN48 BLE+802.15.4 Slim(no zigbee stack), Or MCU Fig. 11.1: Part Number Table 11.1: Part Order Options Product Description No. BL702S-A0-Q2I BLE+802.15.4 Slim, MCU, QFN32, 4Mb flash BL702C-10-Q2H Zigbee+BLE Combo, QFN32, 8Mb flash BL702/704/706 Datasheet 41/ 43 @2021 Bouffalo Lab BL702/704/706 Datasheet Table 11.1: Part Order Options Product Description No. BL704S-10-Q2I BLE+802.15.4 Slim, MCU, QFN40, 8Mb flash BL706C-10-Q2I Zigbee+BLE Combo, QFN48, 8Mb flash BL706S-10-Q2I BLE+802.15.4 Slim, MCU, QFN48, 8Mb flash BL702/704/706 Datasheet 42/ 43 @2021 Bouffalo Lab 12 Revision history Table 12.1: Document revision history Date Revision Changes 2020/9/15 1.0 Initial release 2020/9/22 1.1 Add package information(QFN48) 2020/10/20 1.2 Modify the number of TIMER 2020/12/4 1.4 Differentiate different package information 2021/1/11 1.5 Add GPIO Muxed Pins 2021/1/22 1.6 Add Reference design 2021/3/16 1.7 Add Product use, ADC characteristics, modify the default function of SPI pins 2021/4/9 1.8 Add peripheral introduction 2021/5/27 1.9 Modify Pinmux description and minimum temperature value 2021/6/9 2.0 Update product number 2021/7/1 2.1 Modify the description of embedded pad BL702/704/706 Datasheet 43/ 43 @2021 Bouffalo Lab