2Pai Semi
Enhanced ESD, 3.0 kV rms/6.0 kV rms
150Kbps Hexa-Channel Digital Isolators
Data Sheet
FEATURES
Ultra low power consumption (150Kbps):
0.55mA/Channel
High data rate: π16xAxx: 600Mbps
π16xExx: 200Mbps
π16xMxx: 10Mbps
π16xUxx: 150kbps
High common-mode transient immunity: 150 kV/µs typical
High robustness to radiated and conducted noise
Isolation voltages:
π16xx3x: AC 3000Vrms
π16xx6x: AC 6000Vrms
High ESD rating:
ESDA/JEDEC JS-001-2017
Human body model (HBM) ±8kV, all pins
Safety and regulatory approvals (Pending)：
UL certificate number: E494497
3000Vrms/6000Vrms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate number: 40047929
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 707V peak/1200V peak
CQC certification per GB4943.1-2011
3 V to 5.5 V level translation
AEC-Q100 qualification
Wide temperature range: -40°C to 125°C
16-lead, RoHS-compliant, (W)SOIC package
π160U/π161U/π162U/π163U
rating of 1.5 kV rms to 6.0 kV rms and the data rate from DC up
to 600Mbps (see the Ordering Guide). The devices operate with
the supply voltage on either side ranging from 3.0 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. The fail-safe state is available in which the outputs
transition to a preset state when the input power supply is not
applied.
FUNCTIONAL BLOCK DIAGRAMS
π160XXX
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VOD
VID
5
12
VIE
6
11
VOE
VIF
7
10
VOF
GND1
8
9
GND2
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VID
5
12
VOD
VIE
6
11
VOE
VOF
7
10
VIF
GND1
8
9
GND 2
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VOD
π161XXX
π162XXX
VID
5
12
VOE
6
11
VOF
7
10
1
8
9
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VOD
5
12
VID
VOE
6
11
V IE
VOF
7
10
VIF
GND 1
8
9
GND2
GND
VIE
VIF
GND 2
APPLICATIONS
General-purpose multichannel isolation
Industrial field bus isolation
ENERAL DESCRIPTION
The π1xxxxx is a 2PaiSemi digital isolators product family that
includes over hundreds of digital isolator products. By using
maturated standard semiconductor CMOS technology and
2PaiSEMI iDivider technology, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators.
Intelligent voltage divider technology (iDivider technology) is a
new generation digital isolator technology invented by 2PaiSEMI.
It uses the principle of capacitor voltage divider to transmit
voltage signal directly cross the isolator capacitor without signal
modulation and demodulation.
π163XXX
Figure1. π160xxx/π161xxx/π162xxx/π163xxx functional Block Diagram
VDD1
VDD2
CIN
COUT
0.1uF
0.1 uF
1
2
3
4
5
6
7
8
VIN_A
VIN_B
VIN_C
VIN_D
VIN_E
VIN_F
GND 1
VDD1
VIA
VIB
VIC
VID
VIE
VIF
GND1
VDD2
VOA
VOB
VOC
VOD
VOE
VOF
GND2
16
15
14
13
12
11
10
9
VOUT_A
VOUT_B
VOUT_C
VOUT_D
VOUT_E
VOUT_F
GND2
Figure2. π160xxx Typical Application Circuit
The π1xxxxx isolator data channels are independent and are
available in a variety of configurations with a withstand voltage
Rev.1
Information furnished by 2Pai semi is believed to be accurate and reliable. However, no
responsibility is assumed by 2Pai semi for its use, nor for any infringements of patents or
other rights of third parties that may result from its use. Specifications subject to change
without notice. No license is granted by implication or otherwise under any patent or
patent rights of 2Pai semi.
Trademarks and registered trademarks are the property of their respective owners.
Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China
021-50850681
2Pai Semiconductor Co., Limited. All rights reserved.
http://www.rpsemi.com/
π160U/π161U/π162U/π163U
Data Sheet
PIN CONFIGURATIONS AND FUNCTIONS
π160Uxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
3
VIB
Logic Input B.
4
VIC
5
VDD1 1
16 VDD2
π160
15 VOA
VIA
2
VIB
3
14 VOB
Logic Input C.
VIC
4
13 VOC
VID
Logic Input D.
VID
5
6
VIE
Logic Input E.
6
VIF
Logic Input F.
VIE
7
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
VOF
Logic Output F.
11
VOE
Logic Output E.
12
VOD
Logic Output D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
TOP VIEW
(Not to scale)
VIF 7
12 VOD
11 VOE
10 VOF
GND1 8
9 GND2
Figure3. π160Uxx Pin Configuration
Figure3. π160Mxx Pin Configuration
π161Uxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
VIA
3
VIB
Logic Input B.
VIC
Logic Input C.
VIB 3
14 VOB
4
5
VID
Logic Input D.
VIC
13 VOC
6
VIE
Logic Input E.
VID 5
7
VOF
Logic Output F.
VIE
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
VOF 7
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
VIF
Logic Input F.
11
VOE
Logic Output E.
12
VOD
Logic Output D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
2
16 VDD2
π161
4
6
GND1 8
TOP VIEW
(Not to scale)
15 VOA
12 VOD
11 VOE
10 VIF
9 GND2
Figure4. π161Uxx Pin Configuration
Figure8. π121x6 Pin Configuration
Rev. 1 | Page 2 of 16
π160U/π161U/π162U/π163U
Data Sheet
π162Uxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
VIA 2
3
VIB
Logic Input B.
VIB
3
14 VOB
4
VIC
Logic Input C.
VIC
4
VID
Logic Input D.
13 VOC
5
6
VOE
Logic Output E.
VID
5
7
VOF
Logic Output F.
VOE 6
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
VOF 7
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
GND1 8
10
VIF
Logic Input F.
11
VIE
Logic Input E.
12
VOD
Logic Output D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
16 VDD2
π162
TOP VIEW
(Not to scale)
15 VOA
12 VOD
11 VIE
10 VIF
9 GND2
Figure5. π162Uxx Pin Configuration
Figure9. π122x6 Pin Configuration
π163Uxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
VIA
2
3
VIB
Logic Input B.
VIB
3
14 VOB
4
VIC
Logic Input C.
VIC
4
VOD
Logic Output D.
13 VOC
5
6
VOE
Logic Output E.
7
VOF
Logic Output F.
VOE 6
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
VOF 7
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
GND1 8
10
VIF
Logic Input F.
11
VIE
Logic Input E.
12
VID
Logic Input D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
VOD 5
16 VDD2
π163
TOP VIEW
(Not to scale)
15 VOA
12 VID
11 VIE
10 VIF
9 GND2
Figure6. π163Uxx Pin Configuration
Figure9. π122x6 Pin Configuration
Rev. 1 | Page 3 of 16
π160U/π161U/π162U/π163U
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 1. Absolute Maximum Ratings4
Parameter
Rating
Supply Voltages (VDD1-GND1, VDD2-GND2)
Input Voltages
−0.5 V to +7.0 V
(VIA, VIB)1
Output Voltages
−0.5 V to VDDx + 0.5 V
(VOA, VOB)1
−0.5 V to VDDx + 0.5 V
Average Output Current per Pin2 Side 1 Output Current (IO1)
−10 mA to +10 mA
Average Output Current per Pin2 Side 2 Output Current (IO2)
−10 mA to +10 mA
Common-Mode Transients
Immunity 3
−150 kV/µs to +150 kV/µs
Storage Temperature (TST) Range
−65°C to +150°C
Ambient Operating Temperature (TA) Range
−40°C to +125°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
2 See Figure7 for the maximum rated current values for various temperatures.
3 See Figure21 for Common-mode transient immunity (CMTI) measurement.
4 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating
conditions for extended periods may affect product reliability.
RECOMMENDED OPERATING CONDITIONS
Table 2. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min
VDDx 1
3
High Level Input Signal Voltage
VIH
0.7*VDDx
Low Level Input Signal Voltage
VIL
0
High Level Output Current
IOH
-6
Low Level Output Current
IOL
Maximum Data Rate
Typ
1
Max
Unit
5.5
V
VDDx
1
0.3*VDDx
V
1
V
mA
6
mA
0
150
Kbps
Junction Temperature
TJ
-40
150
°C
Ambient Operating Temperature
TA
-40
125
°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
Truth Tables
Table 3. π160xxx/π161xxx/π162xxx/π163xxx Truth Table
Default Low
Default High
VOx Output1
VOx Output1
Test Conditions
/Comments
Powered2
Low
Low
Normal operation
Powered2
High
High
Normal operation
Open
Powered2
Powered2
Low
High
Default output
Don’t Care4
Unpowered3
Powered2
Low
High
Default output5
Don’t Care4
Powered2
Unpowered3
High Impedance
High Impedance
VIx Input1
VDDI State1
VDDO State1
Low
Powered2
High
Powered2
Notes:
1 VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel.
Rev. 1 | Page 4 of 16
π160U/π161U/π162U/π163U
Data Sheet
2 Powered
means VDDx≥ 2.9 V
means VDDx < 2.3V
4 Input signal (VIx) must be in a low state to avoid powering the given VDDI1 through its ESD protection circuitry.
5 If the VDDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input
status logic signal after around 3us.
3 Unpowered
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Table 4. Switching Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Parameter
Minimum Pulse Width
Symbol
Maximum Data Rate
Propagation Delay Time1,4
Pulse Width Distortion4
Part to Part Propagation Delay
Skew4
Channel to Channel Propagation
Delay Skew4
Min
Typ
Max
PW
6.5
150
Common-Mode Transient
Immunity3
CMTI
ESD（HBM - Human body
model）
ESD
Within PWD limit
us
The different time between 50% input signal to
50% output signal 50% @ 5VDC supply
3.2
4.8
us
@ 3.3VDC supply
0
0.02
0.2
us
The max different time between tpHL and tpLH@
5VDC supply. And The value is | tpHL - tpLH |
0
0.02
0.2
us
@ 3.3VDC supply
0.3
us
The max different propagation delay time
between any two devices at the same
temperature, load and voltage @ 5VDC supply
0.3
us
0
0.2
us
0
0.2
us
tCSK
tr/tf
Kbps
4.5
tPSK
Output Signal Rise/Fall Time4
Test Conditions/Comments
Within pulse width distortion (PWD) limit
3.0
tpHL, tpLH
PWD
Unit
us
100
@ 3.3VDC supply
The max amount propagation delay time
differs between any two output channels in
the single device @ 5VDC supply.
@ 3.3VDC supply
1.5
ns
10% to 90% signal terminated 50，See
figure17.
150
kV/µs
VIN = VDDx2 or 0V, VCM = 1000 V
±8
kV
All pins
Notes:
1 tpLH = low-to-high propagation delay time, tpHL = high-to-low propagation delay time. See figure 18.
2 VDDx is the side voltage power supply VDD, where x = 1 or 2.
3 See Figure21 for Common-mode transient immunity (CMTI) measurement.
4 Output Signal Terminated 50
Table 5. DC Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Symbol
Rising Input Signal Voltage
Threshold
Falling Input Signal Voltage
Threshold
High Level Output Voltage
Low Level Output Voltage
Min
VIT+
Typ
Max
0.6*VDDx1
0.7*VDDx1
Unit
Test Conditions/Comments
V
VIT-
0.3* VDDX1
0.4* VDDX1
V
VOH 1
VDDx − 0.1
VDDx
V
−20 µA output current
VDDx − 0.2
VDDx − 0.1
V
−2 mA output current
V
20 µA output current
VOL
0
0.1
Rev. 1 | Page 5 of 16
π160U/π161U/π162U/π163U
Data Sheet
Input Current per Signal
Channel
VDDx1 Undervoltage Rising
Threshold
VDDx1 Undervoltage Falling
Threshold
VDDx1 Hysteresis
0.1
0.2
V
2 mA output current
0 V ≤ Signal voltage ≤ VDDX1
IIN
−10
0.5
10
µA
VDDxUV+
2.45
2.65
2.9
V
VDDxUV−
2.3
2.5
2.75
V
VDDxUVH
0.15
V
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
Table 6. Quiescent Supply Current
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
Symbol
π160Uxx Quiescent Supply Current @ 5VDC
Supply
@ 3.3VDC Supply
π161Uxx Quiescent Supply Current @ 5VDC
Supply
@ 3.3VDC Supply
π162Uxx Quiescent Supply Current @ 5VDC
Supply
@ 3.3VDC Supply
π163Uxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
Min
Typ
Max
Unit
Test Conditions
IDD1 (Q)
461
576
749
µA
0V Input signal
IDD2 (Q)
2124
2655
3452
µA
0V Input signal
IDD1 (Q)
182
228
296
µA
5V Input signal
IDD2 (Q)
2302
2877
3740
µA
5V Input signal
IDD1 (Q)
338
423
550
µA
0V Input signal
IDD2 (Q)
2088
2610
3393
µA
0V Input signal
IDD1 (Q)
180
225
293
µA
3.3V Input signal
IDD2 (Q)
2275
2844
3697
µA
3.3V Input signal
IDD1 (Q)
738
923
1199
µA
0V Input signal
IDD2 (Q)
1847
2309
3002
µA
0V Input signal
IDD1 (Q)
536
670
870
µA
5V Input signal
IDD2 (Q)
1949
2436
3167
µA
5V Input signal
IDD1 (Q)
630
788
1024
µA
0V Input signal
IDD2 (Q)
1797
2246
2920
µA
0V Input signal
IDD1 (Q)
529
662
860
µA
3.3V Input signal
IDD2 (Q)
1926
2408
3130
µA
3.3V Input signal
IDD1 (Q)
1015
1269
1650
µA
0V Input signal
IDD2 (Q)
1570
1963
2552
µA
0V Input signal
IDD1 (Q)
IDD2 (Q)
889
1596
1111
1995
1444
2594
µA
µA
5V Input signal
5V Input signal
IDD1 (Q)
922
1152
1498
µA
0V Input signal
IDD2 (Q)
1506
1882
2447
µA
0V Input signal
IDD1 (Q)
878
1098
1427
µA
3.3V Input signal
IDD2 (Q)
1578
1972
2564
µA
3.3V Input signal
IDD1 (Q)
1294
1617
2102
µA
0V Input signal
IDD2 (Q)
1294
1617
2102
µA
0V Input signal
IDD1 (Q)
1243
1554
2020
µA
5V Input signal
IDD2 (Q)
1243
1554
2020
µA
5V Input signal
IDD1 (Q)
1214
1518
1973
µA
0V Input signal
IDD2 (Q)
1214
1518
1973
µA
0V Input signal
IDD1 (Q)
1229
1536
1997
µA
3.3V Input signal
IDD2 (Q)
1229
1536
1997
µA
3.3V Input signal
Rev. 1 | Page 6 of 16
π160U/π161U/π162U/π163U
Data Sheet
Table 7. Total Supply Current vs. Data Throughput (CL = 0 pF)
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
Symbol
π160Uxx Supply Current @ 5VDC
@ 3.3VDC
π161Uxx Supply Current @ 5VDC
@ 3.3VDC
π162Uxx Supply Current @ 5VDC
@ 3.3VDC
π163Uxx Supply Current @ 5VDC
@ 3.3VDC
2 Kbps
Min
50Kbps
Typ
Max
IDD1
0.39
IDD2
Min
150Kbps
Typ
Max
0.59
0.39
2.76
4.14
IDD1
0.30
IDD2
Min
Typ
Max
Unit
0.59
0.39
0.59
mA
2.79
4.19
2.82
4.23
mA
0.45
0.30
0.45
0.30
0.45
mA
2.73
4.10
2.73
4.10
2.76
4.14
mA
IDD1
0.79
1.18
0.79
1.19
0.80
1.19
mA
IDD2
2.37
3.56
2.39
3.59
2.42
3.63
mA
IDD1
0.71
1.06
0.71
1.07
0.71
1.07
mA
IDD2
2.33
3.50
2.33
3.50
2.35
3.53
mA
IDD1
1.18
1.77
1.19
1.79
1.21
1.82
mA
IDD2
1.97
2.96
1.99
2.99
2.02
3.03
mA
IDD1
1.11
1.67
1.12
1.68
1.12
1.68
mA
IDD2
1.92
2.88
1.93
2.90
1.94
2.91
mA
IDD1
1.59
2.39
1.59
2.39
1.62
2.43
mA
IDD2
1.59
2.39
1.59
2.39
1.62
2.43
mA
IDD1
1.53
2.30
1.53
2.30
1.53
2.30
mA
IDD2
1.53
2.30
1.53
2.30
1.53
2.30
mA
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 8. Insulation Specifications
Parameter
Symbol
Rated Dielectric Insulation Voltage
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
Value
Unit
Test Conditions/Comments
π16xU3x
π16xU6x
3000
6000
L (CLR)
4
8
mm min
L (CRP)
4
8
mm min
11
21
µm min
Insulation distance through insulation
>400
>400
V
DIN IEC 112/VDE 0303 Part 1
II
II
CTI
Material Group
V rms
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 9. Package Characteristics
Parameter
Resistance (Input to Output)1
Capacitance (Input to
Output)1
Symbol
Typical Value
Unit
π16xU3x
π16xU6x
RI-O
10 11
10 11
Ω
Test Conditions/Comments
CI-O
0.6
0.6
pF
@1MHz
Input Capacitance2
CI
3
3
pF
@1MHz
IC Junction to Ambient Thermal
Resistance
θJA
76
45
°C/W
Thermocouple located at center
of package underside
Rev. 1 | Page 7 of 16
π160U/π161U/π162U/π163U
Data Sheet
Notes:
1The device is considered a 2-terminal device; SOIC-16 Pin 1 - Pin 8(WSOIC-16 Pin 1-Pin8) are shorted together as the one terminal, and SOIC-16 Pin 9 - Pin 16(WSOIC-16
Pin 9-Pin16) are shorted together as the other terminal.
2Testing from the input signal pin to ground.
REGULATORY INFORMATION
See Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross
isolation waveforms and insulation levels.
Table10. Regulatory
π16xU3x
Regulatory
UL
CSA
VDE
CQC
π16xU6x
Recognized under UL 1577
Recognized under UL 1577
Component Recognition Program1
Component Recognition Program1
Single Protection, 3000 V rms Isolation Voltage
Single Protection, 6000 V rms Isolation Voltage
File (E494497)
File (pending)
Approved under CSA Component Acceptance Notice 5A
Approved under CSA Component Acceptance Notice 5A
CSA 60950-1-07+A1+A2 and
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
IEC 60950-1, second edition, +A1+A2:
Basic insulation at 500 V rms (707 V peak)
Basic insulation at 845 V rms (1200 V peak)
Reinforced insulation at 250 V rms
Reinforced insulation at 422 V rms
(353 V peak)
(600 V peak)
File (pending)
File (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Basic insulation, VIORM = 707 V peak, VIOSM = 4615 V peak
Basic insulation, VIORM = 1200 V peak, VIOSM = 7000 V peak
File (40047929)
File (pending)
Certified under
Certified under
CQC11-471543-2012
CQC11-471543-2012
GB4943.1-2011
GB4943.1-2011
Basic insulation at 500 V rms (707 V peak) working voltage
Basic insulation at 845 V rms (1200 V peak) working voltage
Reinforced insulation at
Reinforced insulation at
250 V rms (353 V peak)
422 V rms (600 V peak)
File (pending)
File (pending)
Notes:
1 In accordance with UL 1577, each π160U3x/π161U3x/π162U3x /π163U3xis proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec; each
π160U6x/π161U6x/π162U6x /π163U6xis proof tested by applying an isulation test voltage ≥ 7200 V rms for 1 sec
2 In accordance with DIN V VDE V 0884-10, eachπ160U3x/π161U3x/π162U3x /π163U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial
discharge detection limit = 5 pC); each π160U6x/π161U6x/π162U6x /π163U6x is proof tested by ≥ 2250 V peak for 1 sec. The * marking branded on the component
designates DIN V VDE V 0884-10 approval.
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11. VDE Insulation Characteristics
Description
Test Conditions/Comments
Symbol
Characteristic
π16xx3x
π16xx6x
I to IV
I to IV
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
Rev. 1 | Page 8 of 16
Unit
π160U/π161U/π162U/π163U
Data Sheet
For Rated Mains Voltage ≤ 300 V rms
I to III
I to III
For Rated Mains Voltage ≤ 400 V rms
I to III
I to III
40/105/21
40/105/21
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
2
2
VIORM
707
1200
V peak
VIORM × 1.875 = Vpd (m), 100% production
test, tini = tm = 1 sec, partial discharge <
5 pC
Vpd (m)
1326
2250
V peak
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
Vpd (m)
1061
1800
V peak
849
1440
V peak
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
VIOTM
4200
8500
V peak
Surge Isolation Voltage Basic
Basic insulation, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM
4615
7000
V peak
Surge Isolation Voltage Reinforced
Reinforced insulation, 1.2 µs rise time,
50 µs, 50% fall time
VIOSM
Safety Limiting Values
Maximum value allowed in the event of
a failure (see Figure 7)
Maximum Junction Temperature
TS
Total Power Dissipation at 25°C
Insulation Resistance at TS
π16xU3x
VIO = 800 V
V peak
150
°C
PS
1.56
2.78
W
RS
>109
>109
Ω
π16xU6x
Figure7. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per VDE
Rev. 1 | Page 9 of 16
150
π160U/π161U/π162U/π163U
3
Propagation Delay Time(uS)
Power Supply Undervoltage Threshold
Data Sheet
2.9
2.8
2.7
2.6
2.5
VDDxUV+(V）
VDDxUV−(V）
2.4
2.3
3.2
3
2.8
2.6
2.4
0
50
100
0
150
tpHL(uS)@5V
tpLH(uS)@5V
50
2.5
2
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
1
0.5
0
0
50
100
150
Free-Air Temperature ( °C)
Figure10. π160Uxx Quiescent Supply Current with 3.3V
Supply vs. Free-Air Temperature
0.5
0
0
50
100
Free-Air Temperature ( °C)
Figure12. π161Uxx Quiescent Supply Current with 3.3V
Supply vs. Free-Air Temperature
150
π161Uxx Quiescent Supply Current
(mA)
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
1
2.5
2
1.5
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
1
0.5
0
0
50
100
150
Free-Air Temperature ( °C)
Figure11. π160Uxx Quiescent Supply Current with 5.0V
Supply vs. Free-Air Temperature
2
1.5
150
Figure9. Propagation Delay Time vs. Free-Air Temperature
π160Uxx Quiescent Supply Current
(mA)
Figure8. UVLO vs. Free-Air Temperature
1.5
100
Free-Air Temperature ( °C)
Free-Air Temperature ( °C)
π160Uxx Quiescent Supply Current
(mA)
tpLH(uS)@3.3V
2.2
2.2
π161Uxx Quiescent Supply Current
(mA)
tpHL(uS)@3.3V
2
1.5
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
1
0.5
0
0
50
100
150
Free-Air Temperature ( °C)
Figure13. π161Uxx Quiescent Supply Current with 5.0V
Supply vs. Free-Air Temperature
Rev. 1 | Page 10 of 16
π160U/π161U/π162U/π163U
π162Uxx Quiescent Supply Current
(mA)
1.6
1.4
1.2
1
0.8
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
0.6
0.4
0.2
0
0
50
100
150
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
0
Figure14. π162Uxx Quiescent Supply Current with 3.3V
Supply vs. Free-Air Temperature
50
100
150
Free-Air Temperature ( °C)
Free-Air Temperature ( °C)
Figure15. π162Uxx Quiescent Supply Current with 5.0V
Supply vs. Free-Air Temperature
1.4
π163Uxx Quiescent Supply Current
(mA)
π162Uxx Quiescent Supply Current
(mA)
Data Sheet
1.2
1
0.8
@3.3V Supply with 0V Input
0.6
@3.3V Supply with 3.3V Input
0.4
@5V Supply with 0V Input
@5V Supply with 5V Input
0.2
0
0
50
100
150
Free-Air Temperature ( °C)
Figure16. π163Uxx Quiescent Supply Current vs. Free-Air
Temperature
VDDX
Figure17. Transition time waveform measurement
Figure18. Propagation delay time waveform measurement
Rev. 1 | Page 11 of 16
π160U/π161U/π162U/π163U
Data Sheet
APPLICATIONS INFORMATION
the user may also include resistors (50–300 Ω) in series with the
inputs and outputs if the system is excessively noisy.
OVERVIEW
The π1xxxxx are 2PaiSemi digital isolators product family based
on 2PaiSEMI unique iDivider technology. Intelligent voltage
Divider technology (iDivider technology) is a new generation
digital isolator technology invented by 2PaiSEMI. It uses the
principle of capacitor voltage divider to transmit signal directly
cross the isolator capacitor without signal modulation and
demodulation. Compare to the traditional Opto-couple
technology, icoupler technology, OOK technology, iDivider is a
more essential and concise isolation signal transmit technology
which leads to greatly simplification on circuit design and
therefore significantly improves device performance, such as
lower power consumption, faster speed, enhanced antiinterference ability, lower noise.
By using maturated standard semiconductor CMOS technology
and the innovative iDivider design, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators. The π1xxxxx isolator data channels are
independent and are available in a variety of configurations with
a withstand voltage rating of 1.5 kV rms to 6.0 kV rms and the
data rate from DC up to 600Mbps (see the Ordering Guide).
The π160Uxx/π161Uxx/π162Uxx/π163Uxx are the outstanding
150Kbps hexa-channel digital isolators with the enhanced ESD
capability. the devices transmit data across an isolation barrier by
layers of silicon dioxide isolation.
The devices operate with the supply voltage on either side
ranging from 3.0 V to 5.5 V, offering voltage translation of 3.3 V
and 5 V logic.
The π160Uxx/π161Uxx/π162Uxx/π163Uxx have very low
propagation delay and high speed. The input/output design
techniques allow logic and supply voltages over a wide range
from 3.0 V to 5.5 V, offering voltage translation of 3.3 V and 5 V
logic. The architecture is designed for high common-mode
transient immunity and high immunity to electrical noise and
magnetic interference.
Avoid reducing the isolation capability, Keep the space
underneath the isolator device free from metal such as planes,
pads, traces and vias.
To minimize the impedance of the signal return loop, keep the
solid ground plane directly underneath the high-speed signal path,
the closer the better. The return path will couple between the
nearest ground plane to the signal path. Keep suitable trace width
for controlled impedance transmission lines interconnect.
To reduce the rise time degradation, keep the length of
input/output signal traces as short as possible, and route low
inductance loop for the signal path and It’s return path.
VDD1
VIA
VIB
VIC
VID/VOD
VIE/VOE
VIF/VOF
VDD2
VOA
VOB
VOC
VOD/VID
VOE/VIE
VOF/VIF
GND1
GND2
Figure19.Recommended Printed Circuit Board Layout
CMTI MEASUREMENT
To measure the Common-Mode Transient Immunity (CMTI) of
π1xxxxx isolator under specified common-mode pulse magnitude
(VCM) and specified slew rate of the common-mode pulse
(dVCM/dt) and other specified test or ambient conditions, The
common-mode pulse generator (G1) will be capable of providing
fast rising and falling pulses of specified magnitude and duration
of the common-mode pulse (VCM) and the maximum commonmode slew rates (dVCM/dt) can be applied to π1xxxxx isolator
coupler under measurement. The common-mode pulse is applied
between one side ground GND1 and the other side ground GND2
of π1xxxxx isolator and shall be capable of providing positive
transients as well as negative transients.
See the Ordering Guide for the model numbers that have the failsafe output state of low or high.
PCB LAYOUT
The low-ESR ceramic bypass capacitors must be connected
between VDD1 and GND1 and between VDD2 and GND2. The
bypass capacitors are placed on the PCB as close to the isolator
device as possible. The recommended bypass capacitor value is
between 0.1 μF and 10 μF. To enhance the robustness of a design,
Figure20. Common-mode transient immunity (CMTI) measurement
Rev. 1 | Page 12 of 16
π160U/π161U/π162U/π163U
Data Sheet
OUTLINE DIMENSIONS
Figure21. 16-Lead Standard Small Outline Package [16-Lead SOIC_N]
Figure22. 16-Lead Wide Body Outline Package [16-Lead SOIC_W]
Rev. 1 | Page 13 of 16
π160U/π161U/π162U/π163U
Data Sheet
REEL INFORMATION
16-Lead SOIC_N
16-Lead SOIC_W
Rev. 1 | Page 14 of 16
π160U/π161U/π162U/π163U
Data Sheet
ORDERING GUIDE
Model Name
Temperature
Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating (kV
rms)
FailSafe
Output
State
Package
Description
Package
Option
Quantity
π160U31
Pai160U31
−40°C to +125°C
6
0
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π160U30
Pai160U30
−40°C to +125°C
6
0
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π161U31
Pai161U31
−40°C to +125°C
5
1
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π161U30
Pai161U30
−40°C to +125°C
5
1
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π162U31
Pai162U31
−40°C to +125°C
4
2
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π162U30
Pai162U30
−40°C to +125°C
4
2
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π163U31
Pai163U31
−40°C to +125°C
3
3
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π163U30
Pai163U30
−40°C to +125°C
3
3
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π160U61
Pai160U61
−40°C to +125°C
6
0
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π160U60
Pai160U60
−40°C to +125°C
6
0
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π161U61
Pai161U61
−40°C to +125°C
5
1
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π161U60
Pai161U60
−40°C to +125°C
5
1
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π162U61
Pai162U61
−40°C to +125°C
4
2
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π162U60
Pai162U60
−40°C to +125°C
4
2
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π163U61
Pai163U61
−40°C to +125°C
3
3
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π163U60
Pai163U60
−40°C to +125°C
3
3
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
Notes:
1 π16xxxxQ special for Auto, qualified for AEC-Q100
PART NUMBER NAMED RULE
π(1)(2)(0)(A)(3)(0)(S)
SeriesNumber:
1,2,3...
Total Channel Am ount:
N=N Channels N=1,2,3,4,5,6...
Reverse Channel Amount:
N=N Channels N=0,1,2,3...
Data Rate:A=600Mbps
E=200Mbps
M=10Mbps
U=150Kbps
Isolation Voltag es:
N=1
1.5KVrms AC
N=3
3KVrms AC
N=6
6KVrms AC
Fail-Safe Output Stat e:
0=Logic Low
1=Logic High
Optional：
S=SSOP Package
Q=AEC-Q100 Qualified
Notes:Pai16xxxx is equals to π16xxxx in the customer BOM
Rev. 1 | Page 15 of 16
π160U/π161U/π162U/π163U
Data Sheet
REVISION HISTORY
Revision
Updated
Date
Page
1
Devin
2018/09/19
All
2
Devin
2018/11/28
P1,P12
3
Devin
2019/09/08
P1,P13,
P15,P16
Change Record
Initial version
Changed CIN，COUT in Figure2 from 0.1uF to 1uF.
Changed the recommended bypass capacitor value from between 0.1 μF and 1 μF to
between 0.1 μF and 10 μF.
P1: Changed the address from ‘Room 19307, Building 8, No.498, GuoShouJing Road’ to
‘Room 308-309, No.22, Boxia Road’; Add iDivider technology description in General
Description.
Changed CIN，COUT in Figure2 from 1uF to 0.1uF.
P13: Add iDivider technology description in overview.
P15: Updated 16-Lead SOIC_W reel drawing.
P16: Add character ‘S’ and ‘Q’ in part number named rule; Changed the SOIC_W
quantity from ‘1000 per reel’ to ‘1500 per reel’.
Rev. 1 | Page 16 of 16
工商网监
湘ICP备2023018690号
