0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
QN8035

QN8035

  • 厂商:

    QUINTIC(昆天科技)

  • 封装:

    MSOP10

  • 描述:

    音频接收器 MSOP10 5V

  • 数据手册
  • 价格&库存
QN8035 数据手册
QN8035 Single-Chip Low-Power FM Receiver for Portable Devices __________________________ General Description __________________________ The QN8035 is a high performance, low power; full-featured single-chip stereo FM receiver designed for cell phones, MP3 players. It integrates FM receive functions, auto-seek and clear channel scan. Advanced digital architecture enables superior receiver sensitivity and crystal clear audio. With its small footprint, minimal external component count and multiple clock frequency support, the QN8035 is easy to integrate into a variety of small form-factor low power portable applications. _______________________________ Key Features ___________________________  Worldwide FM Band Coverage • 60 MHz to 108 MHz full band tuning in 50/100/200 kHz step sizes • 50/75s de-emphasis  Adaptive Noise Cancellation • Integrated adaptive noise cancellation (SNC, HCC, SM)  Very Low Power Consumption • 13.1 mA typical • VCC: 2.7~5.0V, integrated LDO, support battery direct connection • Power saving Standby mode • Low shutdown leakage current • Accommodate 1.6~3.6V digital interface  Volume Control  High Performance • Superior sensitivity, 1.1 µVEMF • 67dB stereo SNR, 0.04% THD • Improved auto channel seek • L/R separation 47dB  Robust Operation • -250C to +850C operation • ESD protection on all input and output pads  1 KHz Tone Generator Inside  Direct Earphone Driving Longtern  Ease of Integration • Small footprint, available in MSOP10 packages • 32.768 kHz and Multiple MHz crystal and direct clock input supported • I2C control interface ___________________________ Typical Applications ________________________ • Feature Phone / Smart Phones • Netbook • Portable Audio & Media Players QN8035 Functional Blocks: RX ANT ARO De Mod RFI De MPX De Emph ALO 2.7–5.0V VCC PHY 10µF Voltage Regulator Crystal Oscillator DSP FSM Control Interface SDA SCL Controller Ordering Information appears at Section 6. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 1 QN8035 CONTENTS 1 Pin Assignment ................................................................................................................................................... 5 2 Electrical Specifications ..................................................................................................................................... 6 3 Functional Description ..................................................................................................................................... 11 3.1 FM Receiver ............................................................................................................................. 11 3.2 Audio Processing ...................................................................................................................... 12 3.3 RDS/RBDS ............................................................................................................................... 13 4 Control Interface Protocol ................................................................................................................................ 14 5 Typical Application Schematic ........................................................................................................................ 16 6 Ordering Information ........................................................................................................................................ 17 7 Package Description ......................................................................................................................................... 18 8 Solder Reflow Profile ....................................................................................................................................... 20 8.1 Package Peak Reflow Temperature .......................................................................................... 20 8.2 Classification Reflow Profiles .................................................................................................. 20 8.3 Maximum Reflow Times .......................................................................................................... 21 Longtern 3.4 Auto Seek (CCA) ...................................................................................................................... 13 REVISION HISTORY REVISION CHANGE DESCRIPTION DATE 0.1 Draft. 2011-08-08 0.2 Update the data from the test report. 2011-09-02 1.0 Release version. 2011-12-20 Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 2 QN8035 1 PIN ASSIGNMENT (Top View) VCC 1 10 SDA ALO 2 9 SCL ARO 3 8 GND AGND 4 7 XCLK RFI 5 6 INT Figure 1 Pin Descriptions MSOP10 NAME 1 VCC Voltage supply 2 ALO Analog audio output – left channel 3 ARO Analog audio output – right channel 4 AGND 5 RFI FM Receiver RF input 6 INT Interrupt output, active low, need pull-up externally 7 XCLK Clock input 8 GND Ground 9 SCL Clock for I2C serial bus. 10 SDA Bi-directional data line for I2C serial bus. Rev 1.0 (12/20) Confidential A DESCRIPTION Ground Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Longtern Table 1: QN8035-SANE Pin Out MSOP10 Page 5 QN8035 2 ELECTRICAL SPECIFICATIONS Table 2: Absolute Maximum Ratings SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vbat Supply voltage VCC to GND -0.3 5 V VIO1 Logic signal level SCL, SDA, INT to GND -0.3 3.6 V -55 +150 Ts Storage temperature o C Notes: 1. VIO is pulled up externally via resisters. SYMBOL PARAMETER CONDITIONS Vcc Supply voltage TA Operating temperature RFin RF input level1 VIO2 Digital I/O voltage VCC to GND MIN TYP MAX UNIT 2.7 3.3 5.0 V +85 o 0.3 V 3.6 V -25 Peak input voltage 1.6 Notes: 1. At RF input pin, RFI. 2. VIO is pulled up externally via resisters. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). C Longtern Table 3: Recommended Operating Conditions Page 6 QN8035 Table 4: DC Characteristics (Typical values are at Vcc = 3.3V and TA = 25oC). SYMBOL PARAMETER CONDITIONS IRX Receive mode supply current IIDLE Idle mode supply current ISTBY Standby mode supply current MIN TYP MAX UNIT 13.1 mA Idle mode 650 A Standby mode 50 A Interface High level output voltage VOL Low level output voltage VIH High level input voltage VIL Low level input voltage 0.9*VIO1 V 0.1*VIO1 1.1 V V 0.3 V MAX UNIT Notes: 1. VIO is pulled up externally via resisters. Table 5: AC Characteristics (Typical values are at Vcc = 3.3V and TA = 25oC). SYMBOL PARAMETERS Fxtal Clock frequency Fxtal_err Clock frequency accuracy CONDITIONS MIN TYP 0.032768 -401 Over temperature, and aging -50 MHz 50 ppm Longtern VOH Notes: 1. See also XTAL_DIV[10:0], PLL_DLT[12:0] Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 7 QN8035 Table 6: Receiver Characteristics (Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC). PARAMETERS CONDITIONS MIN TYP MAX UNIT SRX FM sensitivity (S+N)/N = 26dB 1.1 VEMF IP3 Input referred IP3 At maximum gain 120 dBV RejAM AM suppression 52 dB Rin RF input impedance At pin RFI 5 k SRX_Adj Adjacent channel rejection 200 kHz offset 49 dB SRX_Alt Alternate channel rejection 400 kHz offset 62 dB MONO, f = 22.5 kHz1 58 STEREO, f = 67.5 kHz, fpilot = 6.75 kHz 67 SNRaudio_in THDaudio_in Audio SNR Audio THD dB MONO, f = 75 kHz 0.04 % STEREO, f = 67.5 kHz, fpilot = 6.75 kHz 0.03 % LR_in L/R separation 47 dB AttPilot Pilot rejection 70 dB BLR L/R channel imbalance L and R channel gain imbalance at 1 kHz offset from DC 1 dB De-emphasis time constant PETC = 1 71.3 75 78.7 s PETC = 0 47.5 50 52.5 s Vaudio_out Audio output voltage Peak-Peak, single ended 1 1 V RLOAD Audio output Loading Resistance CLOAD Audio output loading capacitance RSSIerr RSSI uncertainty THDdriver Audio THD after earphone driver emph1 Longtern SYMBOL  32 -3 RLOAD=32, 1 Vpp output 0.05 RLOAD=1k1 Vpp output 0.03 20 pF 3 dB % Notes: 1. Guaranteed by design. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 8 QN8035 Table 7: Timing Characteristics (Typical values are at Vcc = 3.3V and TA = 25oC). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT pup Chip power-up time 1 From power up to register access. 20 ms chsw Channel switching time1 From any channel to any channel. 200 ms Receiver Timing wkup Wake-up time from standby to receive Standby to RX mode. 200 ms tune Tune time Per channel during CCA. 50 ms Table 8: I2C Interface Timing Characteristics (Typical values are at Vcc = 3.3V and TA = 25oC). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT 400 kHz fSCL I2C clock frequency tLOW Clock Low time 1.3 s tHI Clock High time 0.6 s tST SCL input to SDA falling edge start 1,3 0.8 s SDA falling edge to SCL falling edge start3 0.8 s tSTHD trc tfc SCL rising edge3 SCL falling edge 3 Level from 30% to 70% 300 ns Level from 70% to 30% 300 ns tdtHD SCL falling edge to next SDA rising edge3 tdtc SDA rising edge to next SCL rising edge3 tstp SCL rising edge to SDA rising edge 2,3 0.6 s tw Duration before restart3 1.3 s Cb SCL, SDA capacitive loading3 20 Longtern Notes: 1. Guaranteed by design. ns 900 10 ns pF Notes: 1. Start signaling of I2C interface. 2. Stop signaling of I2C interface. 3. Guaranteed by design. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 9 Figure 2 Rev 1.0 (12/20) Confidential A I2C Serial Control Interface Timing Diagram Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Longtern QN8035 Page 10 QN8035 3 FUNCTIONAL DESCRIPTION The QN8035 is a high performance, low power, single chip FM receiver IC that supports worldwide FM broadcast band (60 to 108MHz). RDS/RBDS data service is also supported. RX ANT ARO De Mod RFI De MPX De Emph ALO 2.7–5.0V VCC PHY 10µF Crystal Oscillator Control Interface SDA SCL Controller Figure 3 QN8035 Functional Blocks The QN8035 integrates FM receive functions, including RF front-end circuits (LNA, Mixer and channel selective filter etc), a fully digitized FM demodulator, MPX decoder, de-emphasis and audio processing (SM, HCC, and SNC). Advanced digital architecture enables superior receiver sensitivity and crystal clear audio. The QN8035's Auto Seek function enables automatically selecting the channel of better sound quality. The QN8035 supports a small footprint, high level of integration and multiple clock frequencies. These features make it easy to be integrated into a variety of small form-factor, low-power portable applications. Low phase noise digital synthesizers and extensive on-chip auto calibration ensures robust and consistent performance over temperature and process variations. An integrated voltage regulator enables direct connection to a Li-ion battery and provides high PSRR for superior noise suppression. A low-power IDLE and Standby mode extends battery life. 3.1 FM Receiver  Longtern Voltage Regulator DSP FSM The QN8035 receiver uses a highly digitized low-IF architecture, allowing for the elimination of external components and factory adjustments. The received RF signal is first amplified by an integrated LNA and then down converted to an intermediate frequency (IF) via a quadrature mixer. To improve image rejection (IMR), the quadrature mixer can be programmed to be at high-side or low-side injection. An integrated IF channel filter rejects out-of-channel interference signals. AGC is also performed simultaneously to optimize the signal to noise ratio as well as linearity and interference rejection. The filtered signal is digitized and further processed with a digital FM demodulator and MPX decoder. Audio processing is then performed based on received signal quality and channel condition. Two highquality audio DACs are integrated on chip to drive the audio output. The RDS signal will also be decoded if RDS reception is enabled. A receive signal strength indicator (RSSI) is provided and can be read from RSSIDB [7:0]. Figure 4 shows the curve of RSSI vs. different RF input levels. Auto seek utilizes RSSI to search for available channels. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 11 QN8035 Figure 4 3.2 Audio Processing The MPX signal after FM demodulation is comprised of left and right channel signal, pilot and RDS signal in the following way: m(t )   L(t )  R(t )   L(t )  R(t ) sin(4 ft  20 )   sin(2 ft  0 )  d (t )sin(6 ft  30 ) Here, L(t) and R(t) correspond to the audio signals on the left and right channels respectively, f = 19 kHz, is the initial phase of pilot tone and  is the magnitude of the pilot tone, and d(t) is the RDS signal. In stereo mode, both L and R are recovered by de-MPX. In mono mode, only the L+R portion of audio signal exists. L(t) and R(t) are recovered by de-MPX. Rev 1.0 (12/20) Confidential A Longtern The following figure is measured at FM=88MHz. The RSSI Curve is not varied by FM frequency. RSSI vs RF Input In receive mode, stereo noise cancellation (SNC) for FM only, high cut control (HCC) and soft mute (SM) are supported. Stereo noise suppression is achieved by gradually combining the left and right signals to be a mono signal as the received signal quality degrades. SNC, HCC and SM are controlled by SNR and multipath channel estimation results. The three functions will be archived automatically in the device. The QN8035 has an integrated mono or stereo audio status indicator. There is also a Read ST_MO_RX (Reg04h [0]) bit to get status. In addition, there also is a force mono function to constrain output mono in Reg00h[2]. Two selectable de-emphasis time constants (75us and 50us) supported. Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 12 Figure 5 The audio output can be muted with the MUTE_EN (Reg14h[7]) bit and the output can also be replaced by an internally generated 1KHz tone whenever the RFI has a RF signal input. The QN8035 supports RDS/RBDS data reception in FM mode, including station ID, Meta data, TMC information, etc. The integrated RDS processor performs all symbol Confidential A Audio Response encoding/decoding, block synchronization, error detection and correction functions. RDS/RBDS data communicates with an external MCU through the serial control interface. 3.4 Auto Seek (CCA) 3.3 RDS/RBDS Rev 1.0 (12/20) Longtern QN8035 In receive mode, the QN8035 can automatically tune to stations with good signal quality. The auto seek function is referred to CCA (Clear Channel Assessment). Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 13 QN8035 4 CONTROL INTERFACE PROTOCOL The QN8035 supports the standard I2C serial interfaces. At power-on, all register bits are set to default values. I2C Serial Control Interface QN8035 provides an I2C-compatible serial interface. It consists of two wires; serial bi-directional data line (SDA) and input clock line (SCL). It operates as a slave on the bus and the slave address is 0010000. The data transfer rate on the bus is up to 400 Kbit/s. SDA must be stable during the high period of SCL, except for start and stop conditions. SDA can only change with SCL being low. A high-to-low transition on SDA while SCL is high indicates a start condition. A low-to-high transition on SDA while SCL is high indicates a stop condition. Longtern An I2C master initiates a data transfer by generating a start condition followed by the QN8035 slave address, MSB first, followed by a 0 to indicate a write cycle. After receiving an ACK from the QN8035 (by pulling SDA low), the master sends the sub-address of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The QN8035 acknowledges each byte after completion of each transfer. The I 2C master terminates the write operation by generating a stop condition (P). The read operation consists of two phases. The first phase is the address phase. In this phase, an I 2C master initiates a write operation to the QN8035 by generating a start condition (S) followed by the QN8035 slave address, MSB first, followed by a 0 to indicate a write cycle. After receiving ACK from the QN8035, the master sends the sub-address of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). The second phase is the data phase. In this phase, an I2C master initiates a read operation to the QN8035 by generating a start condition followed by the QN8035 slave address, MSB first, followed by a 1 to indicate a read cycle. After an acknowledge from the QN8035, the I2C master receives one or more bytes of data from the QN8035. The I2C master acknowledges the transfer at the end of each byte. After the last data byte to be sent has been transferred from the QN8035 to the master, the master generates a NACK followed by a stop. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 14 QN8035 The timing diagrams below illustrate both write and read operations. I2C Write Operation SCL SDA A7 I2C Slave Address Start A6 A5 A4 A3 A2 A1 D7 A0 Base Address R/W ACK D6 ACK by slave D5 D4 D3 D2 D1 D0 Data Byte 1 ACK by slave by slave SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 ACK Data Byte 2 D4 D3 D2 D1 D0 D7 D6 D5 ACK Data Byte 3 by slave D4 D3 D2 D1 Data Byte n D0 ACK by slave Stop by slave I2C Read Operation SCL SDA A7 Start I2C Slave Address A6 R/W ACK A5 A4 A3 A2 A1 A0 ACK Base Address by slave Stop by slave SDA D7 Start I2C Slave Address D6 D5 D4 D3 D2 Data Byte 1 R/W ACK by slave Figure 6 D1 D0 D7 D6 ACK D5 D4 D3 D2 D1 D0 Data Byte n by master ACK Stop by master I2C Serial Control Interface Protocol Notes: 1. 2. The default IC address is 0010000. “20” for a WRITE operation, “21” for a READ operation. Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 15 Longtern SCL QN8035 5 TYPICAL APPLICATION SCHEMATIC VCC_3.3V 10K 10K 10K U7 6 7 XCLK 56p/10V SCL SDA 8 9 10 INT RFI XCLK GND GND ARO SCL ALO SDA VCC QN8035 MSOP10 Figure 7 Rev 1.0 (12/20) Confidential A 5 4 Antenna 1000p 330nH 0402 0603 0603 4.7uF/16V 3 2 1 ARO VCC_3.3V 4.7uF/16V 0603 ALO 0.1uF/10V 0402 Longtern INT Typical Application Schematic Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 16 QN8035 6 ORDERING INFORMATION Part Number The QN8035-SANE is Single-Chip Low-Power FM receiver. Package Body [MSOP10] Longtern QN8035-SANE Description Rev 1.0 (12/20) Confidential A Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 17 QN8035 7 PACKAGE DESCRIPTION Figure 8 Symbol MSOP10 Package Outline Dimensions Description Millimeters Minimum Nominal Maximum A Overall package height 0.820 0.95 1.100 A1 Board standoff 0.020 - 0.150 A2 Package thickness 0.750 0.85 0.950 b Lead width 0.180 0.23 0.280 c Lead thickness 0.090 - 0.230 D Package’s outside, X-axis 2.900 3.00 3.100 e Lead pitch 0.50 (BSC) E Package’s outside, Y-axis 2.900 3.00 3.100 E1 Lead to lead, Y-axis 4.750 4.90 5.050 L Foot length 0.400 0.60 0.800 θ Foot to board angle 0° - 6° Longtern 10-Lead plastic Quad Flat, No Lead Package (ML) –Body [MSOP] Notes: 1. 2. Pin 1 visual index feature may vary, but must be located within the area indicated in the drawing. Dimensioning and tolerance per ASME Y 14.5M. BSC: Basic Dimension. The theoretically exact value is shown without tolerance. Carrier Tape Dimensions Rev 1.0 (12/20) Confidential A Copyright ©2011 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 18 QN8035 Figure 9 MSOP10 Carrier Tape Drawing NOTES: 1. 10 sprocket hole pitch cumulative tolerance +0.2mm maximum. 2. Camber not to exceed 1mm in 100mm:
QN8035 价格&库存

很抱歉,暂时无法提供与“QN8035”相匹配的价格&库存,您可以联系我们找货

免费人工找货