Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
MSP432P401R, MSP432P401M SimpleLink™ Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Core
– ARM® 32-Bit Cortex®-M4F CPU With FloatingPoint Unit and Memory Protection Unit
– Frequency up to 48 MHz
– ULPBench™ Benchmark:
– 192.3 ULPMark™-CP
– Performance Benchmark:
– 3.41 CoreMark/MHz
– 1.22 DMIPS/MHz (Dhrystone 2.1)
• Advanced Low-Power Analog Features
– 14-Bit 1-MSPS SAR ADC With 13.2 ENOB
Native and Capability to Reach 16 ENOB With
Oversampling, Differential and Single-Ended
Inputs
– Internal Voltage Reference With 10-ppm/°C
Typical Stability
– Two Analog Comparators
• Memories
– Up to 256KB of Flash Main Memory (Organized
Into Two Banks Enabling Simultaneous
Read/Execute During Erase)
– 16KB of Flash Information Memory (Used for
BSL, TLV, and Flash Mailbox)
– Up to 64KB of SRAM (Including 6KB of Backup
Memory)
– 32KB of ROM With MSP432™ Peripheral Driver
Libraries
• Ultra-Low-Power Operating Modes
– Active: 80 µA/MHz
– Low-Frequency Active: 83 µA at 128 kHz
– LPM3 (With RTC): 660 nA
– LPM3.5 (With RTC): 630 nA
– LPM4: 500 nA
– LPM4.5: 25 nA
• Development Kits and Software (See Tools and
Software)
– MSP-EXP432P401R LaunchPad™
Development Kit
– MSP-TS432PZ100 100-Pin Target Board
– SimpleLink™ MSP432 Software Development
Kit (SDK)
• Operating Characteristics
– Wide Supply Voltage Range: 1.62 V to 3.7 V
– Temperature Range (Ambient): –40°C to 85°C
• Flexible Clocking Features
– Tunable Internal DCO (up to 48 MHz)
– 32.768 kHz Low-Frequency Crystal Support
(LFXT)
– High-Frequency Crystal Support (HFXT) up to
48 MHz
– Low-Frequency Internal Reference Oscillator
(REFO)
– Very Low-Power Low-Frequency Internal
Oscillator (VLO)
– Module Oscillator (MODOSC)
– System Oscillator (SYSOSC)
• Code Security Features
– JTAG and SWD Lock
– IP Protection (up to Four Secure Flash Zones,
Each With Configurable Start Address and Size)
• Enhanced System Features
– Programmable Supervision and Monitoring of
Supply Voltage
– Multiple-Class Resets for Better Control of
Application and Debug
– 8-Channel DMA
– RTC With Calendar and Alarm Functions
• Timing and Control
– Up to Four 16-Bit Timers, Each With up to Five
Capture, Compare, PWM Capability
– Two 32-Bit Timers, Each With Interrupt
Generation Capability
• Serial Communication
– Up to Four eUSCI_A Modules
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI (up to 16 Mbps)
– Up to Four eUSCI_B Modules
– I2C (With Multiple-Slave Addressing)
– SPI (up to 16 Mbps)
• Flexible I/O Features
– Ultra-Low-Leakage I/Os (±20 nA Maximum)
– All I/Os With Capacitive-Touch Capability
– Up to 48 I/Os With Interrupt and Wake-up
Capability
– Up to 24 I/Os With Port Mapping Capability
– Eight I/Os With Glitch Filtering Capability
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
• Encryption and Data Integrity Accelerators
– 128-, 192-, or 256-Bit AES Encryption and
Decryption Accelerator
– 32-Bit Hardware CRC Engine
1.2
•
•
Applications
Industrial and Automation
– Glass Breakage Detectors
– Smart Thermostats
– Access Panels
– Gas Monitors
– Field Transmitters
– Process Automation
– Home Automation
Metering
– Flow Meters
– Electric Meters
– Communication Modules
1.3
• JTAG and Debug Support
– 4-Pin JTAG and 2-Pin SWD Debug Interfaces
– Serial Wire Trace
– Power Debug and Profiling of Applications
•
•
•
Test and Measurement
– Digital Multimeters
– Wireless Digital Multimeters
– Contactless and Hand-Held Digital Meters
Health and Fitness
– Watches
– Activity Monitors
– Fitness Accessories
– Blood Glucose Meters
Consumer Electronics
– Mobile Devices
– Sensor Hubs
Description
The SimpleLink MSP432P401x microcontrollers (MCUs) are optimized wireless host MCUs with an
integrated 14-bit analog-to-digital converter (ADC) capable of up to 16 ENOB delivering ultra-low-power
performance including 80 µA/MHz in active power and 660 nA in standby power with FPU and DSP
extensions. As an optimized wireless host MCU, the MSP432P401x allows developers to add highprecision analog and memory extension to applications based on SimpleLink wireless connectivity
solutions.
The MSP432P401x devices are part of the SimpleLink microcontroller (MCU) platform, which consists of
Wi-Fi®, Bluetooth® low energy, Sub-1 GHz, and host MCUs. All share a common, easy-to-use
development environment with a single core software development kit (SDK) and rich tool set. A one-time
integration of the SimpleLink platform lets you add any combination of devices from the portfolio into your
design. The ultimate goal of the SimpleLink platform is to achieve 100 percent code reuse when your
design requirements change. For more information, visit www.ti.com/simplelink.
MSP432P401x devices are supported by a comprehensive ecosystem of tools, software, documentation,
training, and support to get your development started quickly. The MSP-EXP432P401R LaunchPad
development kit or MSP-TS432PZ100 target socket board (with additional MCU sample) along with the
free SimpleLink MSP432 SDK is all you need to get started.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP432P401RIPZ
MSP432P401MIPZ
LQFP (100)
14 mm × 14 mm
MSP432P401RIZXH
MSP432P401MIZXH
NFBGA (80)
5 mm × 5 mm
MSP432P401RIRGC
MSP432P401MIRGC
VQFN (64)
9 mm × 9 mm
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
1.4
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the MSP432P401R and MSP432P401M devices.
LFXIN, LFXOUT,
HFXIN HFXOUT
DCOR
PJ.x
P1.x to P10.x
LPM3.5 Domain
Capacitive Touch IO 0,
Capacitive Touch IO 1
DMA
PCM
PSS
Power
Control
Manager
Power
Supply
System
CS
RTC_C
WDT_A
Clock
System
Real-Time
Clock
Watchdog
Timer
RSTCTL
SYSCTL
Reset
Controller
System
Controller
Backup
Memory
SRAM
6KB
I/O Ports
I/O Ports
P1 to P10
78 I/Os
PJ
6 I/Os
8 Channels
Address
CPU
®
ARM
Cortex™-M4F
Bus
Control
Logic
Data
Flash
256KB
128KB
SRAM
(includes
Backup
Memory)
64KB
32KB
ROM
(Peripheral
Driver
Library)
32KB
AES256
Security
Encryption,
Decryption
CRC32
MPU
NVIC, SysTick
FPB, DWT
ITM, TPIU
JTAG, SWD
ADC14
Comp_E0,
Comp_E1
REF_A,
14 bit,
1 Msps,
SAR A/D
Analog
Comparator
Voltage
Reference
TA0, TA1,
TA2,TA3
Timer32
Timer_A
16 Bit
5 CCR
2 x 32-bit
Timers
eUSCI_A0,
eUSCI_A1,
eUSCI_A2,
eUSCI_A3
(UART,
IrDA, SPI)
eUSCI_B0,
eUSCI_B1,
eUSCI_B2,
eUSCI_B3
2
(I C, SPI)
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. MSP432P401R, MSP432P401M Functional Block Diagram
The CPU and all of the peripherals in the device interact with each other through a common AHB matrix.
In some cases, there are bridges between the AHB ports and the peripherals. These bridges are
transparent to the application from a memory map perspective and, therefore, are not shown in the block
diagram.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Device Overview
3
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
2
3
Revision History ......................................... 5
Device Comparison ..................................... 6
4
Terminal Configuration and Functions .............. 8
4.1
Pin Diagrams ......................................... 8
4.2
Pin Attributes ........................................ 11
4.3
Signal Descriptions .................................. 17
4.4
Pin Multiplexing
4.5
Buffer Types......................................... 27
4.6
Connection for Unused Pins ........................ 27
.....................................
6
27
Specifications ........................................... 28
........................
........................................
Recommended Operating Conditions ...............
Recommended External Components .............
Operating Mode VCC Ranges .......................
Operating Mode CPU Frequency Ranges .........
Operating Mode Peripheral Frequency Ranges ....
5.1
Absolute Maximum Ratings
28
5.2
ESD Ratings
28
5.3
5.4
5.5
5.6
5.7
5.8
28
29
29
30
30
Operating Mode Execution Frequency vs Flash
Wait-State Requirements ........................... 31
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
4
5.20
Related Products ..................................... 7
3.1
5
5.19
Current Consumption During Device Reset.........
Current Consumption in LDO-Based Active
Modes – Dhrystone 2.1 Program ...................
Current Consumption in DC-DC-Based Active
Modes – Dhrystone 2.1 Program ...................
Current Consumption in Low-Frequency Active
Modes – Dhrystone 2.1 Program ...................
Typical Characteristics of Active Mode Currents for
CoreMark Program ..................................
Typical Characteristics of Active Mode Currents for
Prime Number Program .............................
Typical Characteristics of Active Mode Currents for
Fibonacci Program ..................................
Typical Characteristics of Active Mode Currents for
While(1) Program ...................................
Typical Characteristics of Low-Frequency Active
Mode Currents for CoreMark Program ..............
31
31
8
32
32
33
34
35
36
37
Current Consumption in LDO-Based LPM0 Modes . 38
Table of Contents
7
9
Current Consumption in DC-DC-Based LPM0
Modes ............................................... 38
Current Consumption in Low-Frequency LPM0
Modes ............................................... 38
5.21
Current Consumption in LPM3, LPM4 Modes ...... 39
5.22
Current Consumption in LPM3.5, LPM4.5 Modes .. 39
........ 40
5.24 Thermal Resistance Characteristics ................ 40
5.25 Timing and Switching Characteristics ............... 41
Detailed Description ................................... 90
6.1
Overview ............................................ 90
6.2
Processor and Execution Features ................. 90
6.3
Memory Map ........................................ 91
6.4
Memories on the MSP432P401x .................. 111
6.5
DMA ................................................ 114
6.6
Memory Map Access Details ...................... 115
6.7
Interrupts ........................................... 117
6.8
System Control..................................... 119
6.9
Peripherals ......................................... 124
6.10 Code Development and Debug .................... 134
6.11 Performance Benchmarks ......................... 136
6.12 Input/Output Diagrams ............................. 138
6.13 Device Descriptors (TLV) .......................... 176
6.14 Identification........................................ 178
Applications, Implementation, and Layout ...... 180
7.1
Device Connection and Layout Fundamentals .... 180
5.23
Current Consumption of Digital Peripherals
7.2
Peripheral and Interface-Specific Design
Information ......................................... 181
Device and Documentation Support .............. 183
...................
8.1
Getting Started and Next Steps
8.2
Device and Development Tool Nomenclature ..... 183
8.3
Tools and Software ................................ 184
8.4
Documentation Support ............................ 186
8.5
Related Links
8.6
Community Resources............................. 188
8.7
Trademarks ........................................ 188
8.8
Electrostatic Discharge Caution
8.9
Export Control Notice .............................. 188
8.10
Glossary............................................ 188
......................................
...................
183
187
188
Mechanical, Packaging, and Orderable
Information ............................................. 188
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 26, 2016 to March 7, 2017
•
•
•
•
•
Page
Added "SimpleLink" branding, including updates to the titles of referenced documents .................................... 1
Reorganized contents of Section 1.1, Features .................................................................................. 1
Updated Section 1.2, Applications ................................................................................................. 2
Updated Section 1.3, Description ................................................................................................... 2
Updated lists of software and tools in Section 8.3, Tools and Software.................................................... 185
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Revision History
5
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
3 Device Comparison
Table 3-1 summarizes the features of the MSP432P401x microcontrollers.
Table 3-1. Device Comparison (1)
eUSCI
(1)
(2)
6
CHANNEL
A:
UART,
IrDA, SPI
CHANNEL
B:
SPI, I2C
20-mA
DRIVE I/O
TOTAL
I/Os
PACKAGE
100 PZ
DEVICE
FLASH
(KB)
SRAM
(KB)
ADC14
(Channels)
COMP_E0
(Channels)
COMP_E1
(Channels)
Timer_A (2)
MSP432P401RIPZ
256
64
24 ext, 2 int
8
8
5, 5, 5, 5
4
4
4
84
MSP432P401MIPZ
128
32
24 ext, 2 int
8
8
5, 5, 5, 5
4
4
4
84
100 PZ
MSP432P401RIZXH
256
64
16 ext, 2 int
6
8
5, 5, 5
3
4
4
64
80 ZXH
MSP432P401MIZXH
128
32
16 ext, 2 int
6
8
5, 5, 5
3
4
4
64
80 ZXH
MSP432P401RIRGC
256
64
12 ext, 2 int
2
4
5, 5, 5
3
3
4
48
64 RGC
MSP432P401MIRGC
128
32
12 ext, 2 int
2
4
5, 5, 5
3
3
4
48
64 RGC
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
Device Comparison
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
3.1
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers
connectivity options.
Low-power and high-performance MCUs, with wired and wireless
Products for SimpleLink MSP432 MCUs SimpleLink MSP432 MCUs with an ultra-low-power ARM
Cortex-M4 core are optimized for Internet-of-Things sensor node applications. With an
integrated 14-bit ADC, the family enables acquisition and processing of high-precision
signals without sacrificing power and is an optimal host MCU for TI's SimpleLink wireless
connectivity solutions.
Companion Products for MSP432P401R Review products that are frequently purchased or used with
this product.
Reference Designs for MSP432P401R The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Device Comparison
7
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
P6.2/UCB1STE/C1.5
P6.3/UCB1CLK/C1.4
P6.4/UCB1SIMO/UCB1SDA/C1.3
P6.5/UCB1SOMI/UCB1SCL/C1.2
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
DVSS3
RSTn/NMI
AVSS2
PJ.2/HFXOUT
PJ.3/HFXIN
AVCC2
P7.0/PM_SMCLK/PM_DMAE0
P7.1/PM_C0OUT/PM_TA0CLK
P7.2/PM_C1OUT/PM_TA1CLK
P7.3/PM_TA0.0
PJ.4/TDI
PJ.5/TDO/SWO
SWDIOTMS
SWCLKTCK
P9.4/UCA3STE
P9.5/UCA3CLK
P9.6/UCA3RXD/UCA3SOMI
P9.7/UCA3TXD/UCA3SIMO
P10.0/UCB3STE
Figure 4-1 shows the pinout of the 100-pin PZ package.
67
P5.3/A2
P1.6/UCB0SIMO/UCB0SDA
10
66
P5.2/A3
P1.7/UCB0SOMI/UCB0SCL
11
65
P5.1/A4
VCORE
12
64
P5.0/A5
DVCC1
13
63
P4.7/A6
VSW
14
62
P4.6/A7
DVSS1
15
61
P4.5/A8
P2.0/PM_UCA1STE
16
60
P4.4/HSMCLK/SVMHOUT/A9
P2.1/PM_UCA1CLK
17
59
P4.3/MCLK/RTCCLK/A10
P2.2/PM_UCA1RXD/PM_UCA1SOMI
18
58
P4.2/ACLK/TA2CLK/A11
P2.3/PM_UCA1TXD/PM_UCA1SIMO
19
57
P4.1/A12
P2.4/PM_TA0.1
20
56
P4.0/A13
P2.5/PM_TA0.2
21
55
P6.1/A14
P2.6/PM_TA0.3
22
54
P6.0/A15
P2.7/PM_TA0.4
23
53
P9.1/A16
P10.4/TA3.0/C0.7
24
52
P9.0/A17
P10.5/TA3.1/C0.6
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P8.7/A18
P7.4/PM_TA1.4/C0.5
A.
B.
C.
D.
E.
P8.6/A19
9
P8.5/A20
P5.4/A1
P1.5/UCB0CLK
P8.4/A21
68
P8.3/TA3CLK/A22
8
P8.2/TA3.2/A23
P5.5/A0
P1.4/UCB0STE
AVCC1
69
DCOR
7
AVSS1
P5.6/TA2.1/VREF+/VeREF+/C1.7
P1.3/UCA0TXD/UCA0SIMO
PJ.1/LFXOUT
70
PJ.0/LFXIN
6
AVSS3
P5.7/TA2.2/VREF-/VeREF-/C1.6
P1.2/UCA0RXD/UCA0SOMI
P3.7/PM_UCB2SOMI/PM_UCB2SCL
71
P3.6/PM_UCB2SIMO/PM_UCB2SDA
5
P3.5/PM_UCB2CLK
DVSS2
P1.1/UCA0CLK
P3.4/PM_UCB2STE
72
P3.3/PM_UCA2TXD/PM_UCA2SIMO
4
P3.2/PM_UCA2RXD/PM_UCA2SOMI
DVCC2
P1.0/UCA0STE
P3.1/PM_UCA2CLK
73
P3.0/PM_UCA2STE
3
P8.1/UCB3CLK/TA2.0/C0.0
P9.2/TA3.3
P10.3/UCB3SOMI/UCB3SCL
P8.0/UCB3STE/TA1.0/C0.1
74
P7.7/PM_TA1.1/C0.2
2
P7.6/PM_TA1.2/C0.3
P9.3/TA3.4
P10.2/UCB3SIMO/UCB3SDA
P7.5/PM_TA1.3/C0.4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
P10.1/UCB3CLK
The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default
mapping. See Section 6.9.2 for details.
A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-1. 100-Pin PZ Package (Top View)
8
Terminal Configuration and Functions
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Figure 4-2 shows the pinout of the 80-pin ZXH package.
P1.0 SWCLKTCK PJ.5
A1
A2
A3
P1.1 SWDIOTMS PJ.4
A.
B.
C.
D.
B3
P7.3
PJ.3
PJ.2
P6.5
P6.4
P6.2
A4
A5
A6
A7
A8
A9
P7.2
P7.0
B4
B5
B1
B2
P1.5
VCORE
P1.2
P7.1
C1
C2
C4
C5
P1.6
DVCC1
P1.4
P1.3
D1
D2
D3
D4
P1.7
VSW
P2.2
P2.0
E1
E2
E3
E4
P2.1
DVSS1
P2.4
P2.3
F1
F2
F3
F4
P2.5
P2.6
P7.7
G1
G2
G3
P2.7
P7.5
H1
H2
P7.4
J1
RSTn/NMI P6.7
B6
P6.6
P6.3
B7
B8
B9
DVSS3
P5.5
P5.7
C6
C7
C8
C9
DVCC2
AVSS2
P5.3
P5.4
P5.6
D5
D6
D7
D8
D9
AVSS3
DVSS2
P5.0
P5.1
P5.2
E5
E6
E7
E8
E9
AVSS1
AVCC1
P4.5
P4.6
P4.7
F5
F6
F7
F8
F9
P8.1
P3.2
P3.5
P4.2
P4.3
P4.4
G4
G5
G6
G7
G8
G9
P8.0
P3.1
P3.4
P3.7
P6.1
P4.1
P4.0
H3
H4
H5
H6
H7
H8
H9
P7.6
P3.0
P3.3
P3.6
PJ.0
PJ.1
DCOR
P6.0
J2
J3
J4
J5
J6
J7
J8
J9
AVCC2
A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-2. 80-Pin ZXH Package (Top View)
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
9
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
DVSS3
RSTn/NMI
AVSS2
PJ.2/HFXOUT
PJ.3/HFXIN
AVCC2
P7.0/PM_SMCLK/PM_DMAE0
P7.1/PM_C0OUT/PM_TA0CLK
P7.2/PM_C1OUT/PM_TA1CLK
P7.3/PM_TA0.0
PJ.4/TDI
PJ.5/TDO/SWO
SWDIOTMS
SWCLKTCK
Figure 4-3 shows the pinout of the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.0/UCA0STE
1
48
DVCC2
P1.1/UCA0CLK
2
47
DVSS2
P1.2/UCA0RXD/UCA0SOMI
3
46
P5.7/TA2.2/VREF-/VeREF-/C1.6
P1.3/UCA0TXD/UCA0SIMO
4
45
P5.6/TA2.1/VREF+/VeREF+/C1.7
P1.4/UCB0STE
5
44
P5.5/A0
P1.5/UCB0CLK
6
43
P5.4/A1
P1.6/UCB0SIMO/UCB0SDA
7
42
P5.3/A2
P1.7/UCB0SOMI/UCB0SCL
8
41
P5.2/A3
VCORE
9
40
P5.1/A4
DVCC1
10
39
P5.0/A5
VSW
11
38
P4.7/A6
DVSS1
12
37
P4.6/A7
A.
B.
C.
D.
E.
F.
P4.2/ACLK/TA2CLK/A11
AVCC1
DCOR
AVSS1
PJ.1/LFXOUT
PJ.0/LFXIN
AVSS3
P3.7/PM_UCB2SOMI/PM_UCB2SCL
P3.6/PM_UCB2SIMO/PM_UCB2SDA
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P3.5/PM_UCB2CLK
P4.3/MCLK/RTCCLK/A10
P2.3/PM_UCA1TXD/PM_UCA1SIMO
P3.4/PM_UCB2STE
34
P3.3/PM_UCA2TXD/PM_UCA2SIMO
15
P3.2/PM_UCA2RXD/PM_UCA2SOMI
P4.4/HSMCLK/SVMHOUT/A9
P2.2/PM_UCA1RXD/PM_UCA1SOMI
P3.1/PM_UCA2CLK
P4.5/A8
35
P3.0/PM_UCA2STE
36
14
P8.1/UCB3CLK/TA2.0/C0.0
13
P8.0/UCB3STE/TA1.0/C0.1
P2.0/PM_UCA1STE
P2.1/PM_UCA1CLK
The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default
mapping. See Section 6.9.2 for details.
A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
TI recommends connecting the thermal pad on the QFN package to DVSS.
UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-3. 64-Pin RGC Package (Top View)
10
Terminal Configuration and Functions
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
4.2
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Pin Attributes
Table 4-1 describes the attributes of the pins.
Table 4-1. Pin Attributes
PIN NO. (1)
PZ
ZXH
RGC
1
N/A
N/A
2
3
N/A
N/A
N/A
4
A1
1
5
B1
2
6
7
C4
D4
3
4
8
D3
5
9
C1
6
10
D1
7
BUFFER TYPE (5)
POWER
SOURCE (6)
RESET
STATE
AFTER POR (7)
P10.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3CLK
I/O
LVCMOS
DVCC
N/A
P10.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3SIMO
I/O
LVCMOS
DVCC
N/A
UCB3SDA
I/O
LVCMOS
DVCC
N/A
P10.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3SOMI
I/O
LVCMOS
DVCC
N/A
UCB3SCL
I/O
LVCMOS
DVCC
N/A
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
N/A
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
N/A
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
N/A
UCA0SOMI
I/O
LVCMOS
DVCC
N/A
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
N/A
UCA0SIMO
I/O
LVCMOS
DVCC
N/A
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
N/A
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
N/A
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
N/A
UCB0SDA
I/O
LVCMOS
DVCC
N/A
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
N/A
UCB0SCL
(3)
11
E1
8
I/O
LVCMOS
DVCC
N/A
12
C2
9
VCORE
–
Power
DVCC
N/A
13
D2
10
DVCC1
–
Power
N/A
N/A
14
E2
11
VSW
–
Power
N/A
N/A
15
F2
12
DVSS1
–
Power
N/A
N/A
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1STE
I/O
LVCMOS
DVCC
N/A
16
(1)
(2)
(3)
(4)
(5)
(6)
(7)
N/A
SIGNAL
TYPE (4)
SIGNAL NAME (2)
E4
13
N/A = not available on this package
(RD) indicates the reset default signal name for that pin.
To determine the pin mux encodings for each pin, see Section 6.12, Input/Output Diagrams.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
Buffer Types: see Table 4-3 for details
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
N/A = Not applicable
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
11
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-1. Pin Attributes (continued)
PIN NO.
(1)
PZ
ZXH
RGC
17
F1
14
18
E3
15
19
20
F4
F3
16
N/A
21
G1
N/A
22
G2
N/A
23
H1
N/A
24
N/A
N/A
25
26
N/A
J1
N/A
N/A
SIGNAL
TYPE (4)
BUFFER TYPE (5)
POWER
SOURCE (6)
RESET
STATE
AFTER POR (7)
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1CLK
I/O
LVCMOS
DVCC
N/A
P2.2 (RD)
SIGNAL NAME (2)
I/O
LVCMOS
DVCC
OFF
PM_UCA1RXD
I
LVCMOS
DVCC
N/A
PM_UCA1SOMI
I/O
LVCMOS
DVCC
N/A
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1TXD
O
LVCMOS
DVCC
N/A
PM_UCA1SIMO
I/O
LVCMOS
DVCC
N/A
P2.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.1
I/O
LVCMOS
DVCC
N/A
P2.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.2
I/O
LVCMOS
DVCC
N/A
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.3
I/O
LVCMOS
DVCC
N/A
P2.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.4
I/O
LVCMOS
DVCC
N/A
P10.4 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.0
I/O
LVCMOS
DVCC
N/A
C0.7
I
Analog
DVCC
N/A
P10.5 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.1
I/O
LVCMOS
DVCC
N/A
C0.6
I
Analog
DVCC
N/A
P7.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.4
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P7.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.3
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P7.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.2
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P7.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.1
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P8.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3STE
I/O
LVCMOS
DVCC
N/A
TA1.0
I/O
LVCMOS
DVCC
N/A
C0.1
I
Analog
DVCC
N/A
P8.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3CLK
I/O
LVCMOS
DVCC
N/A
TA2.0
I/O
LVCMOS
DVCC
N/A
C0.0
I
Analog
DVCC
N/A
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2STE
I/O
LVCMOS
DVCC
N/A
P3.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2CLK
I/O
LVCMOS
DVCC
N/A
C0.5
27
H2
N/A
C0.4
28
J2
N/A
C0.3
29
G3
N/A
C0.2
30
31
32
33
12
H3
G4
J3
H4
17
18
19
20
(3)
Terminal Configuration and Functions
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 4-1. Pin Attributes (continued)
PIN NO.
(1)
PZ
ZXH
RGC
34
G5
21
SIGNAL NAME (2)
P3.2 (RD)
35
36
37
38
39
J4
H5
G6
J5
H6
22
23
24
25
26
E5
27
SIGNAL
TYPE (4)
BUFFER TYPE (5)
POWER
SOURCE (6)
RESET
STATE
AFTER POR (7)
I/O
LVCMOS
DVCC
OFF
PM_UCA2RXD
I
LVCMOS
DVCC
N/A
PM_UCA2SOMI
I/O
LVCMOS
DVCC
N/A
P3.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2TXD
O
LVCMOS
DVCC
N/A
PM_UCA2SIMO
I/O
LVCMOS
DVCC
N/A
P3.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2STE
I/O
LVCMOS
DVCC
N/A
P3.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2CLK
I/O
LVCMOS
DVCC
N/A
P3.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2SIMO
I/O
LVCMOS
DVCC
N/A
PM_UCB2SDA
I/O
LVCMOS
DVCC
N/A
P3.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2SOMI
I/O
LVCMOS
DVCC
N/A
I
LVCMOS
DVCC
N/A
PM_UCB2SCL
40
(3)
AVSS3
–
Power
N/A
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
PJ.1 (RD)
I/O
LVCMOS
DVCC
OFF
LFXOUT
O
Analog
DVCC
N/A
PJ.0 (RD)
41
J6
28
42
J7
29
43
F5
30
AVSS1
–
Power
N/A
N/A
44
J8
31
DCOR
–
Analog
N/A
N/A
45
F6
32
AVCC1
–
Power
N/A
N/A
P8.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.2
I/O
LVCMOS
DVCC
N/A
46
N/A
N/A
LFXIN
A23
P8.3 (RD)
47
N/A
N/A
TA3CLK
A22
48
N/A
N/A
49
N/A
N/A
50
N/A
N/A
51
N/A
N/A
52
N/A
N/A
53
N/A
N/A
54
J9
N/A
55
H7
N/A
P8.4 (RD)
A21
P8.5 (RD)
A20
P8.6 (RD)
A19
P8.7 (RD)
A18
P9.0 (RD)
A17
P9.1 (RD)
A16
P6.0 (RD)
A15
P6.1 (RD)
A14
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
13
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
ZXH
RGC
56
H9
N/A
57
H8
N/A
58
59
60
61
62
G7
G8
G9
F7
F8
33
34
35
36
37
63
F9
38
64
E7
39
65
E8
40
66
E9
41
67
D7
42
68
D8
43
69
C8
44
70
71
14
(1)
D9
C9
45
46
SIGNAL
TYPE (4)
BUFFER TYPE (5)
POWER
SOURCE (6)
RESET
STATE
AFTER POR (7)
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
P4.2 (RD)
I/O
LVCMOS
DVCC
OFF
ACLK
O
LVCMOS
DVCC
N/A
TA2CLK
I
LVCMOS
DVCC
N/A
A11
I
Analog
DVCC
N/A
P4.3 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
N/A
RTCCLK
O
LVCMOS
DVCC
N/A
A10
I
Analog
DVCC
N/A
P4.4 (RD)
I/O
LVCMOS
DVCC
OFF
HSMCLK
O
LVCMOS
DVCC
N/A
SVMHOUT
O
LVCMOS
DVCC
N/A
A9
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
SIGNAL NAME (2)
P4.0 (RD)
A13
P4.1 (RD)
A12
P4.5 (RD)
A8
P4.6 (RD)
A7
P4.7 (RD)
A6
P5.0 (RD)
A5
P5.1 (RD)
A4
P5.2 (RD)
A3
P5.3 (RD)
A2
(3)
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
P5.6 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.1
I/O
LVCMOS
DVCC
N/A
VREF+
O
Analog
DVCC
N/A
VeREF+
I
Analog
DVCC
N/A
C1.7
I
Analog
DVCC
N/A
P5.7 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.2
I/O
LVCMOS
DVCC
N/A
VREF-
O
Analog
DVCC
N/A
VeREF-
I
Analog
DVCC
N/A
C1.6
I
Analog
DVCC
N/A
P5.4 (RD)
A1
P5.5 (RD)
A0
72
E6
47
DVSS2
–
Power
N/A
N/A
73
C6
48
DVCC2
–
Power
N/A
N/A
Terminal Configuration and Functions
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 4-1. Pin Attributes (continued)
PIN NO.
(1)
PZ
ZXH
RGC
74
N/A
N/A
75
N/A
N/A
76
A9
N/A
SIGNAL
TYPE (4)
BUFFER TYPE (5)
POWER
SOURCE (6)
RESET
STATE
AFTER POR (7)
P9.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.3
I/O
LVCMOS
DVCC
N/A
P9.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.4
I/O
LVCMOS
DVCC
N/A
P6.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
N/A
SIGNAL NAME (2)
C1.5
77
B9
N/A
I
Analog
DVCC
N/A
P6.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
N/A
C1.4
78
A8
N/A
I
Analog
DVCC
N/A
P6.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
N/A
UCB1SDA
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P6.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
N/A
UCB1SCL
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P6.6 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.3
I/O
LVCMOS
DVCC
N/A
UCB3SIMO
I/O
LVCMOS
DVCC
N/A
UCB3SDA
I/O
LVCMOS
DVCC
N/A
C1.3
79
A7
N/A
C1.2
80
B8
49
C1.1
81
B7
50
82
C7
51
83
B6
52
84
D6
53
85
A6
54
86
A5
55
87
D5
56
88
B5
57
I
Analog
DVCC
N/A
P6.7 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.4
I/O
LVCMOS
DVCC
N/A
UCB3SOMI
I/O
LVCMOS
DVCC
N/A
UCB3SCL
I/O
LVCMOS
DVCC
N/A
C1.0
I
Analog
DVCC
N/A
DVSS3
–
Power
N/A
N/A
RSTn (RD)
I
LVCMOS
DVCC
PU
NMI
I
LVCMOS
DVCC
N/A
AVSS2
–
Power
N/A
N/A
PJ.2 (RD)
I/O
LVCMOS
DVCC
OFF
HFXOUT
O
Analog
DVCC
N/A
PJ.3 (RD)
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
HFXIN
AVCC2
–
Power
N/A
N/A
P7.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_SMCLK
O
LVCMOS
DVCC
N/A
PM_DMAE0
89
C5
58
I
LVCMOS
DVCC
N/A
P7.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_C0OUT
O
LVCMOS
DVCC
N/A
PM_TA0CLK
90
B4
59
(3)
I
LVCMOS
DVCC
N/A
P7.2 (RD)
I/O
LVCMOS
DVCC
OFF
PM_C1OUT
O
LVCMOS
DVCC
N/A
PM_TA1CLK
I
LVCMOS
DVCC
N/A
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
15
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-1. Pin Attributes (continued)
PIN NO.
PZ
ZXH
RGC
91
A4
60
92
B3
61
SIGNAL
TYPE (4)
BUFFER TYPE (5)
POWER
SOURCE (6)
RESET
STATE
AFTER POR (7)
P7.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.0
I/O
LVCMOS
DVCC
N/A
PJ.4
I/O
LVCMOS
DVCC
N/A
I
LVCMOS
DVCC
PU
PJ.5
I/O
LVCMOS
DVCC
N/A
TDO (RD)
O
LVCMOS
DVCC
N/A
SIGNAL NAME (2)
TDI (RD)
(3)
93
A3
62
SWO
O
LVCMOS
DVCC
N/A
94
B2
63
SWDIOTMS
I/O
LVCMOS
DVCC
PU
95
A2
64
SWCLKTCK
I
LVCMOS
DVCC
PD
96
N/A
N/A
P9.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3STE
I/O
LVCMOS
DVCC
N/A
P9.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3CLK
I/O
LVCMOS
DVCC
N/A
P9.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3RXD
I
LVCMOS
DVCC
N/A
UCA3SOMI
I/O
LVCMOS
DVCC
N/A
P9.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3TXD
O
LVCMOS
DVCC
N/A
UCA3SIMO
I/O
LVCMOS
DVCC
N/A
P10.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3STE
I/O
LVCMOS
DVCC
N/A
QFN Pad
–
–
N/A
–
97
98
99
16
(1)
N/A
N/A
N/A
N/A
N/A
N/A
100
N/A
N/A
N/A
N/A
Pad
Terminal Configuration and Functions
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
4.3
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
ADC
Clock
(1)
(2)
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
A0
69
C8
44
I
ADC analog input A0
A1
68
D8
43
I
ADC analog input A1
A2
67
D7
42
I
ADC analog input A2
A3
66
E9
41
I
ADC analog input A3
A4
65
E8
40
I
ADC analog input A4
A5
64
E7
39
I
ADC analog input A5
A6
63
F9
38
I
ADC analog input A6
A7
62
F8
37
I
ADC analog input A7
A8
61
F7
36
I
ADC analog input A8
A9
60
G9
35
I
ADC analog input A9
A10
59
G8
34
I
ADC analog input A10
A11
58
G7
33
I
ADC analog input A11
A12
57
H8
N/A
I
ADC analog input A12
A13
56
H9
N/A
I
ADC analog input A13
A14
55
H7
N/A
I
ADC analog input A14
A15
54
J9
N/A
I
ADC analog input A15
A16
53
N/A
N/A
I
ADC analog input A16
A17
52
N/A
N/A
I
ADC analog input A17
A18
51
N/A
N/A
I
ADC analog input A18
A19
50
N/A
N/A
I
ADC analog input A19
A20
49
N/A
N/A
I
ADC analog input A20
A21
48
N/A
N/A
I
ADC analog input A21
A22
47
N/A
N/A
I
ADC analog input A22
A23
46
N/A
N/A
I
ADC analog input A23
ACLK
58
G7
33
O
ACLK clock output
DCOR
44
J8
31
–
DCO external resistor pin
HFXIN
86
A5
55
I
Input for high-frequency crystal oscillator HFXT
HFXOUT
85
A6
54
O
Output for high-frequency crystal oscillator HFXT
HSMCLK
60
G9
35
O
HSMCLK clock output
LFXIN
41
J6
28
I
Input for low-frequency crystal oscillator LFXT
LFXOUT
42
J7
29
O
Output of low-frequency crystal oscillator LFXT
MCLK
59
G8
34
O
MCLK clock output
FUNCTION
SIGNAL NAME
DESCRIPTION
N/A = not available
I = input, O = output
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
17
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-2. Signal Descriptions (continued)
FUNCTION
Comparator
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
C0.0
31
G4
18
I
Comparator_E0 input 0
C0.1
30
H3
17
I
Comparator_E0 input 1
C0.2
29
G3
N/A
I
Comparator_E0 input 2
C0.3
28
J2
N/A
I
Comparator_E0 input 3
C0.4
27
H2
N/A
I
Comparator_E0 input 4
C0.5
26
J1
N/A
I
Comparator_E0 input 5
C0.6
25
N/A
N/A
I
Comparator_E0 input 6
C0.7
24
N/A
N/A
I
Comparator_E0 input 7
C1.0
81
B7
50
I
Comparator_E1 input 0
C1.1
80
B8
49
I
Comparator_E1 input 1
C1.2
79
A7
N/A
I
Comparator_E1 input 2
C1.3
78
A8
N/A
I
Comparator_E1 input 3
C1.4
77
B9
N/A
I
Comparator_E1 input 4
C1.5
76
A9
N/A
I
Comparator_E1 input 5
C1.6
71
C9
46
I
Comparator_E1 input 6
C1.7
70
D9
45
I
Comparator_E1 input 7
SWCLKTCK
95
A2
64
I
Serial wire clock input (SWCLK)/JTAG clock input
(TCK)
SWDIOTMS
94
B2
63
I/O
Serial wire data input/output (SWDIO)/JTAG test mode
select (TMS)
SWO
93
A3
62
O
Serial wire trace output
TDI
92
B3
61
I
JTAG test data input
TDO
93
A3
62
O
JTAG test data output
P1.0
4
A1
1
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability
P1.1
5
B1
2
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P1.2
6
C4
3
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P1.3
7
D4
4
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P1.4
8
D3
5
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability
P1.5
9
C1
6
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability
P1.6
10
D1
7
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P1.7
11
E1
8
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
SIGNAL NAME
Debug
GPIO
18
Terminal Configuration and Functions
DESCRIPTION
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 4-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
P2.0
P2.1
P2.2
GPIO
(continued)
SIGNAL NO. (1)
PZ
16
17
18
ZXH
E4
F1
E3
RGC
13
14
15
SIGNAL
TYPE (2)
DESCRIPTION
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function. This I/O can be
configured for high drive operation with up to 20-mA
drive capability.
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function. This I/O can be
configured for high drive operation with up to 20-mA
drive capability.
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function. This I/O can be
configured for high drive operation with up to 20-mA
drive capability.
P2.3
19
F4
16
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function. This I/O can be
configured for high drive operation with up to 20-mA
drive capability.
P2.4
20
F3
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P2.5
21
G1
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P2.6
22
G2
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P2.7
23
H1
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P3.0
32
J3
19
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability, and with
reconfigurable port mapping secondary function
P3.1
33
H4
20
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P3.2
34
G5
21
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P3.3
35
J4
22
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P3.4
36
H5
23
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability, and with
reconfigurable port mapping secondary function
P3.5
37
G6
24
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability, and with
reconfigurable port mapping secondary function
P3.6
38
J5
25
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
P3.7
39
H6
26
I/O
General-purpose digital I/O with port interrupt and
wake-up capability and with reconfigurable port
mapping secondary function
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
19
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-2. Signal Descriptions (continued)
FUNCTION
GPIO
(continued)
20
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
P4.0
56
H9
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.1
57
H8
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.2
58
G7
33
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.3
59
G8
34
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.4
60
G9
35
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.5
61
F7
36
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.6
62
F8
37
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P4.7
63
F9
38
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.0
64
E7
39
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.1
65
E8
40
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.2
66
E9
41
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.3
67
D7
42
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.4
68
D8
43
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.5
69
C8
44
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.6
70
D9
45
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P5.7
71
C9
46
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.0
54
J9
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.1
55
H7
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.2
76
A9
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.3
77
B9
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.4
78
A8
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.5
79
A7
N/A
I/O
General-purpose digital I/O with port interrupt and
wake-up capability
P6.6
80
B8
49
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability
P6.7
81
B7
50
I/O
General-purpose digital I/O with port interrupt, wakeup, and glitch filtering capability
SIGNAL NAME
Terminal Configuration and Functions
DESCRIPTION
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 4-2. Signal Descriptions (continued)
FUNCTION
GPIO
(continued)
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
P7.0
88
B5
57
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.1
89
C5
58
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.2
90
B4
59
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.3
91
A4
60
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.4
26
J1
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.5
27
H2
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.6
28
J2
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.7
29
G3
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P8.0
30
H3
17
I/O
General-purpose digital I/O
P8.1
31
G4
18
I/O
General-purpose digital I/O
P8.2
46
N/A
N/A
I/O
General-purpose digital I/O
P8.3
47
N/A
N/A
I/O
General-purpose digital I/O
P8.4
48
N/A
N/A
I/O
General-purpose digital I/O
P8.5
49
N/A
N/A
I/O
General-purpose digital I/O
P8.6
50
N/A
N/A
I/O
General-purpose digital I/O
P8.7
51
N/A
N/A
I/O
General-purpose digital I/O
P9.0
52
N/A
N/A
I/O
General-purpose digital I/O
P9.1
53
N/A
N/A
I/O
General-purpose digital I/O
P9.2
74
N/A
N/A
I/O
General-purpose digital I/O
P9.3
75
N/A
N/A
I/O
General-purpose digital I/O
P9.4
96
N/A
N/A
I/O
General-purpose digital I/O
P9.5
97
N/A
N/A
I/O
General-purpose digital I/O
P9.6
98
N/A
N/A
I/O
General-purpose digital I/O
P9.7
99
N/A
N/A
I/O
General-purpose digital I/O
P10.0
100
N/A
N/A
I/O
General-purpose digital I/O
P10.1
1
N/A
N/A
I/O
General-purpose digital I/O
P10.2
2
N/A
N/A
I/O
General-purpose digital I/O
P10.3
3
N/A
N/A
I/O
General-purpose digital I/O
P10.4
24
N/A
N/A
I/O
General-purpose digital I/O
P10.5
25
N/A
N/A
I/O
General-purpose digital I/O
PJ.0
41
J6
28
I/O
General-purpose digital I/O
PJ.1
42
J7
29
I/O
General-purpose digital I/O
PJ.2
85
A6
54
I/O
General-purpose digital I/O
PJ.3
86
A5
55
I/O
General-purpose digital I/O
PJ.4
92
B3
61
I/O
General-purpose digital I/O
PJ.5
93
A3
62
I/O
General-purpose digital I/O
SIGNAL NAME
DESCRIPTION
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
21
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-2. Signal Descriptions (continued)
FUNCTION
I2C
22
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
UCB0SCL
11
E1
8
I/O
I2C clock – eUSCI_B0 I2C mode
UCB0SDA
10
D1
7
I/O
I2C data – eUSCI_B0 I2C mode
UCB1SCL
79
A7
N/A
I/O
I2C clock – eUSCI_B1 I2C mode
UCB1SDA
78
A8
N/A
I/O
I2C data – eUSCI_B1 I2C mode
UCB3SCL
3
N/A
N/A
I/O
I2C clock – eUSCI_B3 I2C mode
UCB3SCL
81
B7
50
I/O
I2C clock – eUSCI_B3 I2C mode
UCB3SDA
2
N/A
N/A
I/O
I2C data – eUSCI_B3 I2C mode
UCB3SDA
80
B8
49
I/O
I2C data – eUSCI_B3 I2C mode
SIGNAL NAME
Terminal Configuration and Functions
DESCRIPTION
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 4-2. Signal Descriptions (continued)
FUNCTION
Port Mapper
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
PM_C0OUT
89
C5
58
O
Default mapping: Comparator_E0 output
PM_C1OUT
90
B4
59
O
Default mapping: Comparator_E1 output
PM_DMAE0
88
B5
57
I
Default mapping: DMA external trigger input
PM_SMCLK
88
B5
57
O
Default mapping: SMCLK clock output
PM_TA0.0
91
A4
60
I/O
Default mapping: TA0 CCR0 capture: CCI0A input,
compare: Out0
PM_TA0.1
20
F3
N/A
I/O
Default mapping: TA0 CCR1 capture: CCI1A input,
compare: Out1
PM_TA0.2
21
G1
N/A
I/O
Default mapping: TA0 CCR2 capture: CCI2A input,
compare: Out2
PM_TA0.3
22
G2
N/A
I/O
Default mapping: TA0 CCR3 capture: CCI3A input,
compare: Out3
PM_TA0.4
23
H1
N/A
I/O
Default mapping: TA0 CCR4 capture: CCI4A input,
compare: Out4
PM_TA0CLK
89
C5
58
I
PM_TA1.2
28
J2
N/A
I/O
Default mapping: TA1 CCR2 capture: CCI2A input,
compare: Out2
PM_TA1.3
27
H2
N/A
I/O
Default mapping: TA1 CCR3 capture: CCI3A input,
compare: Out3
PM_TA1.4
26
J1
N/A
I/O
Default mapping: TA1 CCR4 capture: CCI4A input,
compare: Out4
PM_TA1CLK
90
B4
59
I
PM_UCA1CLK
17
F1
14
I/O
PM_UCA1RXD
18
E3
15
I
Default mapping: Receive data – eUSCI_A1 UART
mode
PM_UCA1SIMO
19
F4
16
I/O
Default mapping: Slave in, master out – eUSCI_A1
SPI mode
PM_UCA1SOMI
18
E3
15
I/O
Default mapping: Slave out, master in – eUSCI_A1
SPI mode
PM_UCA1STE
16
E4
13
I/O
Default mapping: Slave transmit enable – eUSCI_A1
SPI mode
PM_UCA1TXD
19
F4
16
O
Default mapping: Transmit data – eUSCI_A1 UART
mode
PM_UCA2CLK
33
H4
20
I/O
Default mapping: Clock signal input – eUSCI_A2 SPI
slave mode
Clock signal output – eUSCI_A2 SPI master mode
PM_UCA2RXD
34
G5
21
I
Default mapping: Receive data – eUSCI_A2 UART
mode
PM_UCA2SIMO
35
J4
22
I/O
Default mapping: Slave in, master out – eUSCI_A2
SPI mode
PM_UCA2SOMI
34
G5
21
I/O
Default mapping: Slave out, master in – eUSCI_A2
SPI mode
PM_UCA2STE
32
J3
19
I/O
Default mapping: Slave transmit enable – eUSCI_A2
SPI mode
PM_UCA2TXD
35
J4
22
O
Default mapping: Transmit data – eUSCI_A2 UART
mode
SIGNAL NAME
DESCRIPTION
Default mapping: TA0 input clock
Default mapping: TA1 input clock
Default mapping: Clock signal input – eUSCI_A1 SPI
slave mode
Clock signal output – eUSCI_A1 SPI master mode
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
23
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-2. Signal Descriptions (continued)
FUNCTION
Port Mapper
(continued)
Power
RTC
Reference
(3)
24
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
PM_UCB2CLK
37
G6
24
I/O
PM_UCB2SCL
39
H6
26
I
Default mapping: I2C clock – eUSCI_B2 I2C mode
PM_UCB2SDA
38
J5
25
I/O
Default mapping: I2C data – eUSCI_B2 I2C mode
PM_UCB2SIMO
38
J5
25
I/O
Default mapping: Slave in, master out – eUSCI_B2
SPI mode
PM_UCB2SOMI
39
H6
26
I/O
Default mapping: Slave out, master in – eUSCI_B2
SPI mode
PM_UCB2STE
36
H5
23
I/O
Default mapping: Slave transmit enable – eUSCI_B2
SPI mode
AVCC1
45
F6
32
–
Analog power supply
AVCC2
87
D5
56
–
Analog power supply
AVSS1
43
F5
30
–
Analog ground supply
AVSS2
84
D6
53
–
Analog ground supply
AVSS3
40
E5
27
–
Analog ground supply
DVCC1
13
D2
10
–
Digital power supply
DVCC2
73
C6
48
–
Digital power supply
DVSS1
15
F2
12
–
Digital ground supply
DVSS2
72
E6
47
–
Digital ground supply
DVSS3
82
C7
51
–
Must be connected to ground
VCORE (3)
12
C2
9
–
Regulated core power supply (internal use only, no
external current loading)
VSW
14
E2
11
–
DC-to-DC converter switching output
RTCCLK
59
G8
34
O
RTC_C clock calibration output
VREF+
70
D9
45
O
Internal shared reference voltage positive terminal
VREF-
71
C9
46
O
Internal shared reference voltage negative terminal
VeREF+
70
D9
45
I
Positive terminal of external reference voltage to ADC
VeREF-
71
C9
46
I
Negative terminal of external reference voltage to ADC
(recommended to connect to onboard ground)
SIGNAL NAME
DESCRIPTION
Default mapping: Clock signal input – eUSCI_B2 SPI
slave mode
Clock signal output – eUSCI_B2 SPI master mode
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 4-2. Signal Descriptions (continued)
FUNCTION
SPI
System
Thermal
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
UCA0CLK
5
B1
2
I/O
Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_A0 SPI master mode
UCA0SIMO
7
D4
4
I/O
Slave in, master out – eUSCI_A0 SPI mode
UCA0SOMI
6
C4
3
I/O
Slave out, master in – eUSCI_A0 SPI mode
UCA0STE
4
A1
1
I/O
Slave transmit enable – eUSCI_A0 SPI mode
UCA3CLK
97
N/A
N/A
I/O
Clock signal input – eUSCI_A3 SPI slave mode
Clock signal output – eUSCI_A3 SPI master mode
UCA3SIMO
99
N/A
N/A
I/O
Slave in, master out – eUSCI_A3 SPI mode
UCA3SOMI
98
N/A
N/A
I/O
Slave out, master in – eUSCI_A3 SPI mode
UCA3STE
96
N/A
N/A
I/O
Slave transmit enable – eUSCI_A3 SPI mode
UCB0CLK
9
C1
6
I/O
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
UCB0SIMO
10
D1
7
I/O
Slave in, master out – eUSCI_B0 SPI mode
UCB0SOMI
11
E1
8
I/O
Slave out, master in – eUSCI_B0 SPI mode
UCB0STE
8
D3
5
I/O
Slave transmit enable – eUSCI_B0 SPI mode
UCB1CLK
77
B9
N/A
I/O
Clock signal input – eUSCI_B1 SPI slave mode
Clock signal output – eUSCI_B1 SPI master mode
UCB1SIMO
78
A8
N/A
I/O
Slave in, master out – eUSCI_B1 SPI mode
UCB1SOMI
79
A7
N/A
I/O
Slave out, master in – eUSCI_B1 SPI mode
UCB1STE
76
A9
N/A
I/O
Slave transmit enable – eUSCI_B1 SPI mode
UCB3CLK
1
N/A
N/A
I/O
Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3CLK
31
G4
18
I/O
Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3SIMO
2
N/A
N/A
I/O
Slave in, master out – eUSCI_B3 SPI mode
UCB3SIMO
80
B8
49
I/O
Slave in, master out – eUSCI_B3 SPI mode
UCB3SOMI
3
N/A
N/A
I/O
Slave out, master in – eUSCI_B3 SPI mode
UCB3SOMI
81
B7
50
I/O
Slave out, master in – eUSCI_B3 SPI mode
UCB3STE
30
H3
17
I/O
Slave transmit enable – eUSCI_B3 SPI mode
UCB3STE
100
N/A
N/A
I/O
Slave transmit enable – eUSCI_B3 SPI mode
NMI
83
B6
52
I
External nonmaskable interrupt
RSTn
83
B6
52
I
External reset (active low)
SVMHOUT
60
G9
35
O
SVMH output
QFN Pad
N/A
N/A
Pad
–
QFN package exposed thermal pad. TI recommends
connection to VSS.
SIGNAL NAME
DESCRIPTION
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
25
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 4-2. Signal Descriptions (continued)
FUNCTION
Timer
UART
26
SIGNAL NO. (1)
PZ
ZXH
RGC
SIGNAL
TYPE (2)
PM_TA1.1
29
G3
N/A
I/O
Default mapping: TA1 CCR1 capture: CCI1A input,
compare: Out1
TA1.0
30
H3
17
I/O
TA1 CCR0 capture: CCI0A input, compare: Out0
TA2.0
31
G4
18
I/O
TA2 CCR0 capture: CCI0A input, compare: Out0
TA2.1
70
D9
45
I/O
TA2 CCR1 capture: CCI1A input, compare: Out1
TA2.2
71
C9
46
I/O
TA2 CCR2 capture: CCI2A input, compare: Out2
TA2.3
80
B8
49
I/O
TA2 CCR3 capture: CCI3A input, compare: Out3
TA2.4
81
B7
50
I/O
TA2 CCR4 capture: CCI4A input, compare: Out4
TA2CLK
58
G7
33
I
TA3.0
24
N/A
N/A
I/O
TA3 CCR0 capture: CCI0A input, compare: Out0
TA3.1
25
N/A
N/A
I/O
TA3 CCR1 capture: CCI1A input, compare: Out1
TA3.2
46
N/A
N/A
I/O
TA3 CCR2 capture: CCI2A input, compare: Out2
TA3.3
74
N/A
N/A
I/O
TA3 CCR3 capture: CCI3A input, compare: Out3
TA3.4
75
N/A
N/A
I/O
TA3 CCR4 capture: CCI4A input, compare: Out4
TA3CLK
47
N/A
N/A
I
TA3 input clock
UCA0RXD
6
C4
3
I
Receive data – eUSCI_A0 UART mode
UCA0TXD
7
D4
4
O
Transmit data – eUSCI_A0 UART mode
UCA3RXD
98
N/A
N/A
I
Receive data – eUSCI_A3 UART mode
UCA3TXD
99
N/A
N/A
O
Transmit data – eUSCI_A3 UART mode
SIGNAL NAME
Terminal Configuration and Functions
DESCRIPTION
TA2 input clock
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
4.4
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.12.
4.5
Buffer Types
Table 4-3 describes the buffer types that are referenced in Table 4-1.
Table 4-3. Buffer Type
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
Analog (1)
3.0 V
N
N/A
N/A
N/A
HVCMOS
13.0 V
Y
N/A
N/A
See Typical
Characteristics
LVCMOS
3.0 V
Y (2)
Programmable
See GeneralPurpose I/Os
See Typical
Characteristics
Power (DVCC) (3)
3.0 V
N
N/A
N/A
N/A
Power (AVCC) (3)
3.0 V
N
N/A
N/A
N/A
Power (DVSS and
AVSS) (3)
0V
N
N/A
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
(2)
(3)
OTHER
CHARACTERISTICS
See analog modules in
Specifications for details
SVSMH enables hysteresis
on DVCC
This is a switch, not a buffer.
Only for input pins
This is supply input, not a buffer.
4.6
Connection for Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection for Unused Pins (1)
PIN
POTENTIAL
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
Set to port function, output direction, and leave unconnected on the PC board
RSTn/NMI
DVCC or VCC
47-kΩ pullup with 1.1-nF pulldown.
PJ.4/TDI
Open
The JTAG TDI pin is shared with general-purpose I/O function (PJ.4). If not being used, this pin
should be set to port function, output direction. When used as JTAG TDI pin, it should remain open.
PJ.5/TDO/SWO
DVCC or VCC
The JTAG TDO/SWO pin is shared with general-purpose I/O function (PJ.5). If not being used, this
pin should be set to port function, output direction. When used as JTAG TDO/SWO pin, it should be
pulled down externally.
SWDIOTMS
DVCC or VCC
This pin should be pulled up externally.
SWCLKTCK
DVSS or VSS
This pin should be pulled down externally.
(1)
COMMENT
For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Copyright © 2015–2017, Texas Instruments Incorporated
27
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5 Specifications
Absolute Maximum Ratings (1)
5.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
UNIT
–0.3
4.17
V
±0.3
V
–0.3
VCC + 0.3 V
(4.17 V MAX)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(4)
–40
Maximum junction temperature, TJ
(1)
(2)
(3)
(4)
±2
mA
125
°C
95
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
(2)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
All pins except DVSS3 pass HBM up to ±1000 V. The DVSS3 pin is used for TI internal test purposes. Connect the DVSS3 pin to supply
ground on the customer application board.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN
Supply voltage range at all DVCC and
AVCC pins (1) (2) (3)
VCC
3.7
Normal operation with internal VCC
supervision
1.71
3.7
Normal operation without internal VCC
supervision
1.62
3.7
Supply voltage on all DVSS and AVSS pins
IINRUSH
Inrush current into the VCC pins (4)
fMCLK
Frequency of the CPU and AHB clock in the system (5)
TA
Operating free-air temperature
TJ
Operating junction temperature
–40
(2)
(3)
(4)
(5)
28
MAX
1.71
VSS
(1)
NOM
At power-up (with internal VCC
supervision)
0
UNIT
V
V
100
mA
0
48
MHz
–40
85
°C
85
°C
TI recommends powering AVCC and DVCC from the same source. A maximum difference of ±0.1 V between AVCC and DVCC can be
tolerated during power up and operation. See Section 5.4 for decoupling capacitor recommendations.
Supply voltage must not change faster than 1 V/ms. Faster changes can cause the VCCDET to trigger a reset even within the
recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
Does not include I/O currents (driven by application requirements).
Operating frequency may require the flash to be accessed with wait states. See Section 5.8 for further details.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Recommended External Components (1)
5.4
CDVCC
Capacitor on DVCC pin
CVCORE
(2) (3)
MIN
TYP
For DC-DC operation (4)
3.3
4.7
For LDO-only operation
3.3
4.7
1.54
4.7
9
µF
70
100
9000
nF
For DC-DC operation, including
capacitor tolerance
Capacitor on VCORE pin
For LDO-only operation, including
capacitor tolerance
MAX
UNIT
µF
CAVCC
Capacitor on AVCC pin
3.3
4.7
LVSW
Inductor between VSW and VCORE pins for DC-DC
3.3
4.7
13
µH
RLVSW-DCR
Allowed DCR for LVSW
150
350
mΩ
ISAT-LVSW
LVSW saturation current
(1)
(2)
(3)
(4)
5.5
µF
700
mA
For optimum performance, select the component value to match the typical value given in the table.
See the section on board guidelines for further details on component selection, placement as well as related PCB design guidelines.
Tolerance of the capacitance and inductance values should be taken into account when choosing a component, to ensure that the MIN
and MAX limits are never exceeded.
CDVCC should not be smaller than CVCORE.
Operating Mode VCC Ranges
over operating free-air temperature (unless otherwise noted)
PARAMETER
VCC_LDO
OPERATING MODE
AM_LDO_VCORE0
AM_LF_VCORE0
LPM0_LDO_VCORE0
LPM0_LF_VCORE0
LPM3_VCORE0
LPM4_VCORE0
LPM3.5
AM_LDO_VCORE1
AM_LF_VCORE1
LPM0_LDO_VCORE1
LPM0_LF_VCORE1
LPM3_VCORE1
LPM4_VCORE1
(1) (2)
TEST CONDITIONS
MIN
MAX
LDO active, SVSMH disabled
1.62
3.7
LDO active, SVSMH enabled
1.71
3.7
UNIT
V
VCC_DCDC_DF0
AM_DCDC_VCORE0
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
LPM0_DCDC_VCORE1
DC-DC active, DC-DC operation not forced
(DCDC_FORCE = 0), SVSMH enabled or
disabled (3)
2.0
3.7
V
VCC_DCDC_DF1
AM_DCDC_VCORE0
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
LPM0_DCDC_VCORE1
DC-DC active, DC-DC operation forced
(DCDC_FORCE = 1), SVSMH enabled or
disabled
1.8
3.7
V
LDO disabled, SVSMH disabled
1.62
3.7
LDO disabled, SVSMH enabled
1.71
3.7
VCC_VCORE_OFF
(1)
(2)
(3)
(4)
(4)
LPM4.5
V
Flash remains active only in active modes and LPM0 modes.
Low-frequency active, low-frequency LPM0, LPM3, LPM4, and LPM3.5 modes are based on LDO only.
When VCC falls below the specified MIN value, the DC-DC operation switches to LDO automatically, as long as the VCC drop is slower
than the rate that is reliably detected. See Table 5-19 for more details.
Core voltage is off in LPM4.5 mode.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
29
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Operating Mode CPU Frequency Ranges (1)
5.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OPERATING MODE
fMCLK
DESCRIPTION
MIN
MAX
UNIT
fAM_LDO_VCORE0
AM_LDO_VCORE0
Normal performance mode with LDO as the active
regulator
0
24
MHz
fAM_LDO_VCORE1
AM_LDO_VCORE1
High performance mode with LDO as the active
regulator
0
48
MHz
fAM_DCDC_VCORE0
AM_DCDC_VCORE0
Normal performance mode with DC-DC as the active
regulator
0
24
MHz
fAM_DCDC_VCORE1
AM_DCDC_VCORE1
High performance mode with DC-DC as the active
regulator
0
48
MHz
fAM_LF_VCORE0
AM_LF_VCORE0
Low-frequency mode with LDO as the active regulator
0
128
kHz
fAM_LF_VCORE1
AM_LF_VCORE1
Low-frequency mode with LDO as the active regulator
0
128
kHz
MIN
MAX
UNIT
Peripheral frequency range in LDO or DC-DC
based active or LPM0 modes for VCORE0
0
12
MHz
Peripheral frequency range in LDO or DC-DC
based active or LPM0 modes for VCORE1
0
24
MHz
Peripheral frequency range in low-frequency
active or low frequency LPM0 modes for
VCORE0 and VCORE1
0
128
kHz
LPM3_VCORE1
Peripheral frequency in LPM3 mode for VCORE0
and VCORE1
0
32.768
kHz
LPM3.5
Peripheral frequency in LPM3.5 mode
0
32.768
kHz
(1)
DMA can be operated at the same frequency as CPU.
5.7
Operating Mode Peripheral Frequency Ranges
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OPERATING MODE
DESCRIPTION
AM_LDO_VCORE0
fAM_LPM0_VCORE0
AM_DCDC_VCORE0
LPM0_LDO_VCORE0
LPM0_DCDC_VCORE0
AM_LDO_VCORE1
fAM_LPM0_VCORE1
AM_DCDC_VCORE1
LPM0_LDO_VCORE1
LPM0_DCDC_VCORE1
AM_LF_VCORE0
fAM_LPM0_LF
AM_LF_VCORE1
LPM0_LF_VCORE0
LPM0_LF_VCORE1
LPM3_VCORE0
fLPM3 (1)
fLPM3.5 (1)
(1)
30
Only RTC and WDT can be active.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
5.8
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Operating Mode Execution Frequency vs Flash Wait-State Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
NUMBER OF
FLASH WAIT
STATES
FLASH READ
MODE
fMAX_NRM_FLWAIT0
0
fMAX_NRM_FLWAIT1
PARAMETER
MAXIMUM SUPPORTED MCLK FREQUENCY (1)
(2)
AM_LDO_VCORE0,
AM_DCDC_VCORE0
AM_LDO_VCORE1,
AM_DCDC_VCORE1
UNIT
Normal read
mode
16
24
MHz
1
Normal read
mode
24
48
MHz
fMAX_ORM_FLWAIT0
0
Other read
modes (3)
8
12
MHz
fMAX_ORM_FLWAIT1
1
Other read
modes (3)
16
24
MHz
fMAX_ORM_FLWAIT2
2
Other read
modes (3)
24
36
MHz
fMAX_ORM_FLWAIT3
3
Other read
modes (3)
24
48
MHz
(1)
(2)
(3)
Violation of the maximum frequency limitation for a given wait-state configuration results in nondeterministic data or instruction fetches
from the flash memory.
In low-frequency active modes, the flash can always be accessed with zero wait states, because the maximum MCLK frequency is
limited to 128 kHz.
Other read modes refers to Read Margin 0, Read Margin 1, Program Verify, and Erase Verify.
5.9
Current Consumption During Device Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IRESET
(1)
(2)
(3)
VCC
Current during device reset
MIN
(1) (2) (3)
TYP
2.2 V
510
3.0 V
600
MAX
850
UNIT
µA
Device held in reset through RSTn/NMI pin.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted) (1)
PARAMETER
EXECUTION
MEMORY
MCLK = 1 MHz MCLK = 8 MHz
VCC
(2) (3) (4) (5)
MCLK =
16 MHz
MCLK =
24 MHz
MCLK =
32 MHz
MCLK =
40 MHz
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
5300
5800
6500
7100
7700
8400
3650
4020
4470
4900
5280
5760
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM_LDO_VCORE0,Flash (6)
(7) (8)
Flash
3.0 V
490
625
1500
1700
2650
2950
3580
3900
IAM_LDO_VCORE1,Flash (6)
(7) (8)
Flash
3.0 V
510
685
1650
1900
2970
3300
4260
4700
IAM_LDO_VCORE0,SRAM (9)
SRAM
3.0 V
435
565
1070
1240
1800
2010
2530
2800
IAM_LDO_VCORE1,SRAM (9)
SRAM
3.0 V
450
620
1160
1370
1980
2250
2800
3120
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
UNIT
µA
µA
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
All SRAM banks kept active.
All peripherals are inactive.
Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
31
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.11 Current Consumption in DC-DC-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted) (1)
EXECUTION
MEMORY
PARAMETER
MCLK = 1 MHz MCLK = 8 MHz
VCC
TYP
MAX
(2) (3) (4) (5)
MCLK =
16 MHz
MCLK =
24 MHz
MCLK =
32 MHz
MCLK =
40 MHz
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
3290
3700
4020
4500
4720
5300
2200
2480
2670
3000
3050
3420
TYP
MAX
TYP
MAX
TYP
MAX
IAM_DCDC_VCORE0,Flash (6)
(7) (8)
Flash
3.0 V
400
475
925
1050
1530
1720
2060
2300
IAM_DCDC_VCORE1,Flash (6)
(7) (8)
Flash
3.0 V
430
550
1100
1280
1880
2140
2650
3000
IAM_DCDC_VCORE0,SRAM (9)
SRAM
3.0 V
370
450
680
780
1040
1180
1410
1600
IAM_DCDC_VCORE1,SRAM (9)
SRAM
3.0 V
390
510
790
940
1250
1440
1720
1960
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
UNIT
µA
µA
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
All SRAM banks are active.
All peripherals are inactive.
Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
IAM_LF_VCORE0,
Flash
IAM_LF_VCORE1,
Flash
IAM_LF_VCORE0,
SRAM
IAM_LF_VCORE1,
SRAM
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
32
(6) (7) (8)
(6) (7) (8)
(9)
(9)
EXECUTION
MEMORY
Flash
Flash
SRAM
SRAM
VCC
–40°C
TYP
MAX
25°C
TYP
2.2 V
75
80
3.0 V
78
83
2.2 V
78
85
3.0 V
81
88
2.2 V
68
73
3.0 V
71
76
2.2 V
70
77
3.0 V
73
90
60°C
MAX
TYP
(2) (3) (4) (5)
85°C
MAX
TYP
95
115
98
118
105
125
108
128
90
105
92
93
108
98
117
102
101
120
100
110
MAX
200
245
190
235
UNIT
μA
μA
μA
μA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
MCLK, HSMCLK, and SMCLK sourced by REFO at 128 kHz
All peripherals are inactive.
SRAM banks 0 and 1 enabled for execution from flash, and SRAM banks 0 to 3 enabled for execution from SRAM.
Flash configured to 0 wait states.
Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
8
8
AM_LDO_VCORE0
AM_LDO_VCORE1
7
6
Current (mA)
Current (mA)
6
5
4
3
5
4
3
2
2
1
1
0
0
1
8
15
22
29
Frequency (MHz)
Flash Execution
36
43
1
50
8
15
D030
VCC = 3 V
TA = 25°C
22
29
Frequency (MHz)
SRAM Execution
Figure 5-1. Frequency vs Current Consumption
36
43
50
D031
VCC = 3 V
TA = 25°C
Figure 5-2. Frequency vs Current Consumption
8
8
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
6
Current (mA)
6
Current (mA)
AM_LDO_VCORE0
AM_LDO_VCORE1
7
5
4
3
5
4
3
2
2
1
1
0
0
1
8
Flash Execution
15
22
29
Frequency (MHz)
36
VCC = 3 V
43
50
1
8
15
D032
TA = 25°C
Figure 5-3. Frequency vs Current Consumption
SRAM Execution
22
29
Frequency (MHz)
VCC = 3 V
36
43
50
D033
TA = 25°C
Figure 5-4. Frequency vs Current Consumption
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
33
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
8
8
AM_LDO_VCORE0
AM_LDO_VCORE1
7
6
Current (mA)
Current (mA)
6
5
4
3
5
4
3
2
2
1
1
0
0
1
8
15
22
29
Frequency (MHz)
Flash Execution
36
43
50
1
VCC = 3 V
TA = 25°C
15
22
29
Frequency (MHz)
SRAM Execution
36
43
50
D035
VCC = 3 V
TA = 25°C
Figure 5-6. Frequency vs Current Consumption
8
8
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
6
Current (mA)
6
Current (mA)
8
D034
Figure 5-5. Frequency vs Current Consumption
5
4
3
5
4
3
2
2
1
1
0
0
1
8
Flash Execution
15
22
29
Frequency (MHz)
VCC = 3 V
36
43
50
Specifications
1
8
15
D036
TA = 25°C
Figure 5-7. Frequency vs Current Consumption
34
AM_LDO_VCORE0
AM_LDO_VCORE1
7
SRAM Execution
22
29
Frequency (MHz)
VCC = 3 V
36
43
50
D037
TA = 25°C
Figure 5-8. Frequency vs Current Consumption
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
8
8
AM_LDO_VCORE0
AM_LDO_VCORE1
7
6
Current (mA)
Current (mA)
6
5
4
3
5
4
3
2
2
1
1
0
0
1
8
15
22
29
Frequency (MHz)
Flash Execution
36
43
50
1
8
15
D038
VCC = 3 V
TA = 25°C
22
29
Frequency (MHz)
SRAM Execution
Figure 5-9. Frequency vs Current Consumption
36
43
50
D039
VCC = 3 V
TA = 25°C
Figure 5-10. Frequency vs Current Consumption
8
8
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
6
Current (mA)
6
Current (mA)
AM_LDO_VCORE0
AM_LDO_VCORE1
7
5
4
3
5
4
3
2
2
1
1
0
0
1
8
Flash Execution
15
22
29
Frequency (MHz)
36
VCC = 3 V
43
50
1
8
15
D040
TA = 25°C
Figure 5-11. Frequency vs Current Consumption
SRAM Execution
22
29
Frequency (MHz)
VCC = 3 V
36
43
50
D041
TA = 25°C
Figure 5-12. Frequency vs Current Consumption
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
35
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.16 Typical Characteristics of Active Mode Currents for While(1) Program
8
8
AM_LDO_VCORE0
AM_LDO_VCORE1
7
6
Current (mA)
Current (mA)
6
5
4
3
5
4
3
2
2
1
1
0
0
1
8
15
22
29
Frequency (MHz)
Flash Execution
36
43
1
50
VCC = 3 V
TA = 25°C
15
22
29
Frequency (MHz)
SRAM Execution
36
43
50
D043
VCC = 3 V
TA = 25°C
Figure 5-14. Frequency vs Current Consumption
8
8
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
AM_DCDC_VCORE0
AM_DCDC_VCORE1
7
6
Current (mA)
6
Current (mA)
8
D042
Figure 5-13. Frequency vs Current Consumption
5
4
3
5
4
3
2
2
1
1
0
0
1
8
Flash Execution
15
22
29
Frequency (MHz)
VCC = 3 V
36
43
50
Specifications
1
8
15
D044
TA = 25°C
Figure 5-15. Frequency vs Current Consumption
36
AM_LDO_VCORE0
AM_LDO_VCORE1
7
SRAM Execution
22
29
Frequency (MHz)
VCC = 3 V
36
43
50
D045
TA = 25°C
Figure 5-16. Frequency vs Current Consumption
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
100
100
AM_LF_VCORE0
AM_LF_VCORE1
AM_LF_VCORE0
AM_LF_VCORE1
96
Current (µA)
Current (µA)
96
92
88
84
80
2.2
92
88
84
2.3
Flash Execution
2.4
2.5
2.6
2.7
Supply Voltage (V)
2.8
TA = 25°C
2.9
3
80
2.2
2.3
2.4
D046
MCLK = 128 kHz
Figure 5-17. Supply Voltage vs Current Consumption
SRAM Execution
2.5
2.6
2.7
Supply Voltage (V)
TA = 25°C
2.8
2.9
3
D046
MCLK = 128 kHz
Figure 5-18. Supply Voltage vs Current Consumption
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
37
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.18 Current Consumption in LDO-Based LPM0 Modes
over recommended operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0_LDO_VCORE0
ILPM0_LDO_VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
VCC
MCLK =
1 MHz
MCLK =
8 MHz
MCLK =
16 MHz
(2) (3) (4) (5) (6)
MCLK =
24 MHz
MCLK =
32 MHz
TYP
MAX
MCLK =
40 MHz
TYP
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
2.2 V
355
485
465
605
590
735
710
860
3.0 V
355
485
465
605
590
735
710
860
2.2 V
365
530
495
665
640
820
775
970
965
1160
1130
1330
1235
1450
3.0 V
365
530
495
665
640
820
775
970
965
1160
1130
1330
1230
1450
UNIT
MAX
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off. Flash and SRAM not accessed.
All SRAM banks are active.
All peripherals are inactive.
5.19 Current Consumption in DC-DC-Based LPM0 Modes
over recommended operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0_DCDC_VCORE0
ILPM0_DCDC_VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
VCC
MCLK =
1 MHz
MCLK =
8 MHz
MCLK =
16 MHz
(2) (3) (4) (5) (6)
MCLK =
24 MHz
MCLK =
32 MHz
TYP
MAX
MCLK =
40 MHz
TYP
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
2.2 V
330
425
400
510
485
600
570
690
3.0 V
325
400
380
460
440
530
510
610
2.2 V
350
485
445
590
555
710
660
820
810
970
935
1110
1020
1200
3.0 V
345
450
420
530
500
620
585
720
700
830
800
940
870
1020
UNIT
MAX
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off. Flash and SRAM not accessed.
All SRAM banks are active.
All peripherals are inactive.
5.20 Current Consumption in Low-Frequency LPM0 Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0_LF_VCORE0
ILPM0_LF_VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
38
VCC
–40°C
TYP
25°C
MAX
TYP
2.2 V
58
63
3.0 V
61
66
2.2 V
60
66
3.0 V
63
69
60°C
MAX
TYP
82
90
(2) (3) (4) (5) (6)
85°C
MAX
TYP
78
94
81
97
84
104
87
107
MAX
180
220
UNIT
μA
μA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
MCLK, HSMCLK, and SMCLK sourced by REFO at 128 kHz.
All peripherals are inactive.
Bank 0 of SRAM kept active. Rest of the banks are powered down.
CPU is off. Flash and SRAM not accessed.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.21 Current Consumption in LPM3, LPM4 Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM3_VCORE0_RTCLF
(7) (8)
ILPM3_VCORE0_RTCREFO
ILPM3_VCORE1_RTCLF
ILPM4_VCORE0
(10)
ILPM4_VCORE1
(10)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(9) (8)
(7) (8)
ILPM3_VCORE1_RTCREFO
–40°C
VCC
(9) (8)
TYP
25°C
MAX
TYP
2.2 V
0.52
0.64
3.0 V
0.54
0.66
2.2 V
0.85
1.07
3.0 V
0.95
1.16
2.2 V
0.72
0.93
3.0 V
0.75
0.95
2.2 V
1.04
1.3
3.0 V
1.14
1.4
2.2 V
0.37
0.48
3.0 V
0.4
0.5
2.2 V
0.54
0.7
3.0 V
0.56
0.72
60°C
MAX
TYP
85°C
MAX
TYP
1.11
2.43
1.13
2.46
1.55
2.89
1.64
2.98
1.47
2.95
1.5
2.98
1.87
3.34
1.96
3.44
0.92
2.19
0.65
0.94
2.2
1.2
2.58
0.98
1.23
2.6
0.85
1.35
1.35
1.7
(2) (3) (4) (5) (6)
MAX
5
5.6
6
6.5
4.8
5.6
UNIT
μA
μA
μA
μA
μA
μA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off, and flash is powered down.
Bank 0 of SRAM retained, all other banks are powered down.
See Table 5-47 for details on additional current consumed for each extra Bank that is enabled for retention.
SVSMH is disabled.
RTC sourced by LFXT. Effective load capacitance of LF crystal is 3.7 pF.
WDT module is disabled.
RTC sourced by REFO.
RTC and WDT modules disabled.
5.22 Current Consumption in LPM3.5, LPM4.5 Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM3.5_RTCLF
(3) (4) (5) (6) (7)
ILPM3.5_RTCREFO
ILPM4.5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(9) (7)
(3) (4) (8) (6) (7)
–40°C
VCC
TYP
25°C
MAX
TYP
2.2 V
0.48
0.6
3.0 V
0.5
0.63
2.2 V
0.82
1.03
3.0 V
0.92
1.12
2.2 V
10
20
3.0 V
15
25
60°C
MAX
0.81
1.3
35
TYP
(2)
85°C
MAX
TYP
1.07
2.36
1.1
2.38
1.52
2.81
1.61
2.9
45
125
50
150
MAX
4.9
5.5
300
UNIT
μA
μA
nA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU and flash are powered down.
Bank 0 of SRAM retained, all other banks powered down.
RTC sourced by LFXT. Effective load capacitance of LF crystal is 3.7 pF.
WDT module is disabled.
SVSMH is disabled.
RTC sourced by REFO.
No core voltage. CPU, flash, and all banks of SRAM are powered down.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
39
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.23 Current Consumption of Digital Peripherals
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
ITIMER_A
Timer_A configured as PWM timer with 50% duty cycle
5
µA/MHz
ITIMER32
Timer32 enabled
3.5
µA/MHz
IUART
eUSCI_A configured in UART mode
6.5
µA/MHz
ISPI
eUSCI_A configured in SPI master mode
5
µA/MHz
2
II2C
eUSCI_B configured in I C master mode
5
µA/MHz
IWDT_A
WDT_A configured in interval timer mode
6
µA/MHz
IRTC_C
RTC_C enabled and sourced from 32-kHz LFXT
IAES256
ICRC32
(1)
100
nA
AES256 active
19
µA/MHz
CRC32 active
2
µA/MHz
Measured with VCORE = 1.2 V
5.24 Thermal Resistance Characteristics
THERMAL METRICS (1)
PACKAGE
(3)
VALUE (2)
UNIT
RθJA
Junction-to-ambient thermal resistance, still air
50.9
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance (4)
9.7
°C/W
RθJB
Junction-to-board thermal resistance (5)
27.2
°C/W
ΨJB
Junction-to-board thermal characterization parameter
26.9
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (6)
N/A
°C/W
RθJA
Junction-to-ambient thermal resistance, still air (3)
58.1
°C/W
26.1
°C/W
22.6
°C/W
22.0
°C/W
LQFP-100 (PZ)
(4)
RθJC(TOP)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance (5)
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
0.5
°C/W
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (6)
N/A
°C/W
RθJA
Junction-to-ambient thermal resistance, still air (3)
29.4
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance (4)
14.8
°C/W
8.3
°C/W
8.2
°C/W
0.2
°C/W
1.0
°C/W
(5)
RθJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
RθJC(BOTTOM)
(1)
(2)
(3)
(4)
(5)
(6)
40
NFBGA-80 (ZXH)
Junction-to-case (bottom) thermal resistance
VQFN-64 (RGC)
(6)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
N/A = not applicable
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.25 Timing and Switching Characteristics
5.25.1 Reset Timing
Table 5-1 lists the latencies to recover from different types of resets.
Table 5-1. Reset Recovery Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
(1)
MAX
UNIT
5
MCLK
cycles
Latency from release of hard reset to release of soft reset
25
MCLK
cycles
tPOR
Latency from release of device POR to release of hard reset
15
25
µs
tCOLDPWR,100 nF
Latency from a cold power-up condition to release of device
POR, CVCORE = 100 nF
300
400
µs
tCOLDPWR,4.7 µF
Latency from a cold power-up condition to release of device
POR, CVCORE = 4.7 µF
400
500
µs
tSOFT
Latency from release of soft reset to first CPU instruction fetch
tHARD
(1)
See Section 6.8.1 for details on the various classes of resets on the device
Table 5-2 lists the latencies to recover from an external reset applied on RSTn pin.
Table 5-2. External Reset Recovery Latencies (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tAM_RSTn
External reset applied when device is in LDO or DC-DC based active modes,
MCLK = 1 to 48 MHz
tAMLF_RSTn, 128 kHz
MIN
MAX
UNIT
5
ms
External reset applied when device is in low-frequency active modes,
MCLK = 128 kHz
5.5
ms
tAMLF_RSTn, 32 kHz
External reset applied when device is in low-frequency active modes,
MCLK = 32.768 kHz
6.5
ms
tLPM0_RSTn
External reset applied when device is in LDO or DC-DC based LPM0 modes,
MCLK = 1 to 48 MHz
5
ms
tLPM0LF_RSTn, 128 kHz
External reset applied when device is in low-frequency LPM0 modes,
MCLK = 128 kHz
5.5
ms
tLPM0LF_RSTn, 32 kHz
External reset applied when device is in low-frequency LPM0 modes,
MCLK = 32.768 kHz
6.5
ms
tLPM3_LPM4_RSTn
External reset applied when device is in LPM3 or LPM4 modes,
MCLK = 24 or 48 MHz while entering LPM3 or LPM4 modes
5
ms
tLPMx.5_RSTn
External reset applied when device is in LPM3.5 or LPM4.5 modes
5
ms
(1)
External reset is applied on RSTn pin, and the latency is measured from release of external reset to start of user application code.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
41
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.25.2 Mode Transition Timing
Table 5-3 lists the latencies required to change between different active modes.
Table 5-3. Active Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ORIGINAL
OPERATING MODE
FINAL OPERATING
MODE
TEST CONDITIONS
Power Off
AM_LDO_VCORE0
From VCC reaching 1.71 V to start of
user application code
tAMLDO0_AMLDO1
AM_LDO_VCORE0
AM_LDO_VCORE1
Transition from AM_LDO_VCORE0
to AM_LDO_VCORE1
MCLK frequency = 24 MHz
tAMLDO1_AMLDO0
AM_LDO_VCORE1
AM_LDO_VCORE0
tAMLDO0_AMDCDC0
AM_LDO_VCORE0
PARAMETER
tOFF_AMLDO0
TYP
MAX
UNIT
6
ms
300
350
µs
Transition from AM_LDO_VCORE1
to AM_LDO_VCORE0
MCLK frequency = 24 MHz
4
5
µs
Transition from AM_LDO_VCORE0
AM_DCDC_VCORE0 to AM_DCDC_VCORE0
MCLK frequency = 24 MHz
20
30
µs
10
15
µs
20
30
µs
Transition from
AM_DCDC_VCORE1 to
AM_LDO_VCORE1
MCLK frequency = 48 MHz
10
15
µs
tAMDCDC0_AMLDO0
AM_DCDC_VCORE0
tAMLDO1_AMDCDC1
AM_LDO_VCORE1
tAMDCDC1_AMLDO1
AM_DCDC_VCORE1
AM_LDO_VCORE1
AM_LDO_VCORE0
AM_LF_VCORE0
Transition from AM_LDO_VCORE0
to AM_LF_VCORE0
SELM = 2, REFO frequency =
128 kHz
90
100
µs
AM_LDO_VCORE0
Transition from AM_LF_VCORE0 to
AM_LDO_VCORE0
SELM = 2, REFO frequency =
128 kHz
50
60
µs
AM_LF_VCORE1
Transition from AM_LDO_VCORE1
to AM_LF_VCORE1
SELM = 2, REFO frequency =
128 kHz
90
100
µs
AM_LDO_VCORE1
Transition from AM_LF_VCORE1 to
AM_LDO_VCORE1
SELM = 2, REFO frequency =
128 kHz
50
60
µs
tAMLDO0_AMLF0
tAMLF0_AMLDO0
tAMLDO1_AMLF1
tAMLF1_AMLDO1
42
Specifications
AM_LF_VCORE0
AM_LDO_VCORE1
AM_LF_VCORE1
AM_LDO_VCORE0
Transition from
AM_DCDC_VCORE0 to
AM_LDO_VCORE0
MCLK frequency = 24 MHz
Transition from AM_LDO_VCORE1
AM_DCDC_VCORE1 to AM_DCDC_VCORE1
MCLK frequency = 48 MHz
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-4 lists the latencies required to change between different active and LPM0 modes.
Table 5-4. LPM0 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tAMLDOx_LPM0LDOx
(1)
tLPM0LDOx_AMLDOx (2)
tAMDCDCx_LPM0DCDCx (1)
tLPM0DCDCx_AMDCDCx (2)
tAMLFx_LPM0LFx
(1)
tLPM0LFx_AMLFx (2)
(1)
(2)
ORIGINAL OPERATING
MODE
AM_LDO_VCOREx
LPM0_LDO_VCOREx
AM_DCDC_VCOREx
LPM0_DCDC_VCOREx
AM_LF_VCOREx
LPM0_LF_VCOREx
FINAL OPERATING
MODE
TEST CONDITIONS
TYP
LPM0_LDO_VCOREx
Transition from
AM_LDO_VCORE0 or
AM_LDO_VCORE1 to
LPM0_LDO_VCORE0 or
LPM0_LDO_VCORE1
1
AM_LDO_VCOREx
Transition from
LPM0_LDO_VCORE0 or
LPM0_LDO_VCORE1 to
AM_LDO_VCORE0 or
AM_LDO_VCORE1
through I/O interrupt
3
LPM0_DCDC_VCOREx
Transition from
AM_DCDC_VCORE0 or
AM_DCDC_VCORE1 to
LPM0_DCDC_VCORE0
or
LPM0_DCDC_VCORE1
1
AM_DCDC_VCOREx
Transition from
LPM0_DCDC_VCORE0
or
LPM0_DCDC_VCORE1
to AM_DCDC_VCORE0
or AM_DCDC_VCORE1
through I/O interrupt
3
Transition from
AM_LF_VCORE0 or
AM_LF_VCORE1 to
LPM0_LF_VCORE0 or
LPM0_LF_VCORE1
1
Transition from
LPM0_LF_VCORE0 or
LPM0_LF_VCORE1 to
AM_LF_VCORE0 or
AM_LF_VCORE1 through
I/O interrupt
3
LPM0_LF_VCOREx
AM_LF_VCOREx
MAX
UNIT
MCLK
cycles
4
MCLK
cycles
MCLK
cycles
4
MCLK
cycles
MCLK
cycles
4
MCLK
cycles
This is the latency between execution of WFI instruction by CPU to assertion of SLEEPING signal at CPU output.
This is the latency between I/O interrupt event to deassertion of SLEEPING signal at CPU output.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
43
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-5 lists the latencies required to change between different active modes and LPM3 or LPM4
modes.
Table 5-5. LPM3, LPM4 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ORIGINAL
OPERATING MODE
PARAMETER
tAMLDO0_LPMx0
(1)
tLPMx0_AMLDO0_NORIO
(2)
tLPMx0_AMLDO0_GFLTIO
tAMLDO1_LPMx1
(1)
tLPMx1_AMLDO1_NORIO
tLPMx1_AMLDO1_GFLTIO
tAMLFx_LPMx_128k
tAMLFx_LPMx_32k
(2)
(1)
(1)
tLPMx_AMLFx_NORIO_128k
tLPMx_AMLFx_NORIO_32k
(1)
(2)
44
(2)
(2)
TYP
MAX
UNIT
SELM = 3.
DCO frequency =
24 MHz
22
24
µs
AM_LDO_VCORE0
Transition from LPM3 or
LPM4 at VCORE0 to
AM_LDO_VCORE0 through
wake-up event from
nonglitch filter type I/O
SELM = 3.
DCO frequency =
24 MHz
8
9
µs
AM_LDO_VCORE0
Transition from LPM3 or
LPM4 at VCORE0 to
AM_LDO_VCORE0 through
wake-up event from glitch
filter type I/O, GLTFLT_EN
= 1
SELM = 3.
DCO frequency =
24 MHz
9
10
µs
Transition from
LPM3_LPM4_VCORE1 AM_LDO_VCORE1 to
LPM3 or LPM4 at VCORE1
SELM = 3.
DCO frequency =
48 MHz
21
23
µs
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1 through
wake-up event from
nonglitch filter type I/O
SELM = 3.
DCO frequency =
48 MHz
7.5
8
µs
LPM3_LPM4_VCORE1
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1 through
wake-up event from glitch
filter type I/O, GLTFLT_EN
= 1
SELM = 3.
DCO frequency =
48 MHz
8
9
µs
AM_LF_VCOREx
LPM3_LPM4_VCOREx
Transition from
AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM3
or LPM4 at VCORE0/1
SELM = 2. REFO
frequency = 128
kHz
240
260
µs
AM_LF_VCOREx
LPM3_LPM4_VCOREx
Transition from
AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM3
or LPM4 at VCORE0/1
SELM = 0. LFXT
frequency =
32.768 kHz
880
900
µs
AM_LF_VCOREx
Transition from LPM3 or
LPM4 at VCORE0/1 to
AM_LF_VCORE0 or
AM_LF_VCORE1 through
wake-up event from
nonglitch filter type I/O
SELM = 2. REFO
frequency = 128
kHz
45
50
µs
AM_LF_VCOREx
Transition from LPM3 or
LPM4 at VCORE0/1 to
AM_LF_VCORE0 or
AM_LF_VCORE1 through
wake-up event from
nonglitch filter type I/O
SELM = 0. LFXT
frequency =
32.768 kHz
150
170
µs
LPM3_LPM4_VCORE0
LPM3_LPM4_VCORE0
AM_LDO_VCORE1
(2)
TEST CONDITIONS
Transition from
LPM3_LPM4_VCORE0 AM_LDO_VCORE0 to
LPM3 or LPM4 at VCORE0
AM_LDO_VCORE0
(2)
FINAL OPERATING
MODE
LPM3_LPM4_VCORE1
LPM3_LPM4_VCOREx
LPM3_LPM4_VCOREx
This is the latency from WFI instruction execution by CPU to LPM3 or LPM4 entry.
This is the latency from I/O wake-up event to MCLK clock start at device pin.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-6 lists the latencies required to change to and from LPM3.5 and LPM4.5 modes.
Table 5-6. LPM3.5, LPM4.5 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ORIGINAL
OPERATING MODE
FINAL OPERATING
MODE
tAMLDOx_LPM3.5 (1)
AM_LDO_VCOREx
LPM3.5
tAMDCDCx_LPM3.5 (1)
AM_DCDC_VCOREx
PARAMETER
TYP
MAX
Transition from AM_LDO_VCORE0 or
AM_LDO_VCORE1 to LPM3.5
25
30
µs
LPM3.5
Transition from AM_DCDC_VCORE0 or
AM_DCDC_VCORE1 to LPM3.5
35
50
µs
AM_LF_VCOREx
LPM3.5
Transition from AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM3.5
225
250
µs
tAMLDOx_LPM4.5 (2)
AM_LDO_VCOREx
LPM4.5
Transition from AM_LDO_VCORE0 or
AM_LDO_VCORE1 to LPM4.5
25
30
µs
tAMDCDCx_LPM4.5 (2)
AM_DCDC_VCOREx
LPM4.5
Transition from AM_DCDC_VCORE0 or
AM_DCDC_VCORE1 to LPM4.5
35
50
µs
AM_LF_VCOREx
LPM4.5
Transition from AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM4.5
250
270
µs
tLPM3.5_AMLDO0 (3)
LPM3.5
AM_LDO_VCORE0
Transition from LPM3.5 to
AM_LDO_VCORE0
0.7
0.8
ms
tLPM4.5_AMLDO0_SVSMON, 100 nF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH enabled while in LPM4.5,
CVCORE = 100 nF
0.8
0.9
ms
tLPM4.5_AMLDO0_SVSMON, 4.7 µF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH enabled while in LPM4.5,
CVCORE = 4.7 µF
0.9
1
ms
tLPM4.5_AMLDO0_SVSMOFF, 100 nF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH disabled while in LPM4.5,
CVCORE = 100 nF
1
1.1
ms
tLPM4.5_AMLDO0_SVSMOFF, 4.7 µF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH disabled while in LPM4.5,
CVCORE = 4.7 µF
1.1
1.2
ms
tAMLFx_LPM3.5 (1)
tAMLFx_LPM4.5 (2)
(1)
(2)
(3)
TEST CONDITIONS
UNIT
This is the latency from WFI instruction execution by CPU to LPM3.5 mode entry.
This is the latency from WFI instruction execution by CPU to LPM4.5 mode entry.
This is the latency from I/O wake-up event to start of user application code.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
45
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.25.3 Clock Specifications
Table 5-7 lists the input requirement for the low-frequency crystal oscillator, LFXT.
Table 5-7. Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
16
40
65
kΩ
CLFXT
Capacitance from LFXT input to ground and from
LFXT output to ground (1)
7.4
12
24
pF
CSHUNT
Crystal shunt capacitance
0.6
0.8
1.6
pF
Cm
Crystal motional capacitance
1
2
10
fF
ESR
Crystal equivalent series resistance
(1)
fOSC = 32.768 kHz
UNIT
Does not include board parasitics. Package and board add additional capacitance to CLFXT.
Table 5-8 lists the characteristics of the low-frequency crystal oscillator, LFXT.
Table 5-8. Low-Frequency Crystal Oscillator, LFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IVCC,LFXT
Current consumption
TEST CONDITIONS
(1)
VCC
MIN
100
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
CL,eff = 6 pF, Typical ESR and CSHUNT
120
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
CL,eff = 9 pF, Typical ESR and CSHUNT
fLFXT
LFXT oscillator crystal
frequency
LFXTBYPASS = 0 (2)
DCLFXT
LFXT oscillator duty cycle
fLFXT = 32.768 kHz (2)
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1
DCLFXT,
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
(1)
(2)
(3)
(4)
(5)
46
Oscillation allowance for
LF crystals (5)
MAX
3.0 V
UNIT
nA
150
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
CL,eff = 12 pF, Typical ESR and CSHUNT
SW
TYP
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
CL,eff = 3.7 pF, Typical ESR and CSHUNT
170
32.768
30%
(3) (4)
10
kHz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32.768 kHz, CL,eff = 6 pF
200
240
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32.768 kHz, CL,eff = 12 pF
300
340
kΩ
Total current measured on both AVCC and DVCC supplies.
Measured at ACLK pin.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-8. Low-Frequency Crystal Oscillator, LFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
CLFXIN
Integrated load capacitance at
LFXIN terminal (6) (7)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (6) (7)
2
pF
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
CL,eff = 3.7 pF,
Typical ESR and CSHUNT,
FCNTLF_EN = 0 (2)
tSTART,LFXT Start-up time (8)
fFault,LFXT
Oscillator fault frequency (9)
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
CL,eff = 12 pF,
Typical ESR and CSHUNT,
FCNTLF_EN = 0 (2)
1.1
3.0 V
s
1.3
(10)
1
3
kHz
(6)
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT
are the total capacitance at the LFXIN and LFXOUT terminals, respectively.
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF. Because the
PCB adds additional capacitance, it must also be considered in the overall capacitance. TI recommends verifying that the recommended
effective load capacitance of the selected crystal is met.
(8) Does not include programmable start-up counter.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition will set the fault flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-9 lists the input requirements for the high-frequency crystal oscillator, HFXT.
Table 5-9. High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ESR
TEST CONDITIONS
Crystal equivalent series resistance
TYP
MAX
fOSC = 1 MHz to ≤4 MHz
MIN
75
150
UNIT
fOSC = >4 MHz to ≤8 MHz
75
150
fOSC = >8 MHz to ≤16 MHz
40
80
fOSC = >16 MHz to ≤24 MHz
30
60
fOSC = >24 MHz to ≤32 MHz
20
40
fOSC = >32 MHz to ≤48 MHz
15
30
36
pF
Ω
CHFXT
Capacitance from HFXT input to ground and
from HFXT output to ground
fOSC = 1 MHz to 48 MHz
28
32
CSHUNT
Crystal shunt capacitance
fOSC = 1 MHz to 48 MHz
1
3
7
pF
Cm
Crystal motional capacitance
fOSC = 1 MHz to 48 MHz
3
7
30
fF
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
47
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-10 lists the characteristics of the high-frequency crystal oscillator, HFXT.
Table 5-10. High-Frequency Crystal Oscillator, HFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDVCC,HFXT
TEST CONDITIONS
HFXT oscillator crystal current
HF mode at typical ESR
HFXT oscillator crystal
frequency, crystal mode
fHFXT
60
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1, CL,eff = 16 pF,
Typical ESR and CSHUNT
100
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 2, CL,eff = 16 pF,
Typical ESR and CSHUNT
180
fOSC = 40 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 5, CL,eff = 16 pF,
Typical ESR and CSHUNT
480
fOSC = 48 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 6, CL,eff = 16 pF,
Typical ESR and CSHUNT
550
HFXTBYPASS = 0, HFFREQ = 0
(1)
1
HFXTBYPASS = 0, HFFREQ = 1
(1)
4.01
8
HFXTBYPASS = 0, HFFREQ = 2
(1)
8.01
16
HFXTBYPASS = 0, HFFREQ = 3
(1)
16.01
24
HFXTBYPASS = 0, HFFREQ = 4
(1)
24.01
32
HFXTBYPASS = 0, HFFREQ = 5
(1)
32.01
40
HFXTBYPASS = 0, HFFREQ = 6
(1)
40.01
48
HFXTBYPASS = 1 (1) (2)
48
260
320
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
UNIT
µA
fOSC = 32 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 4, CL,eff = 16 pF,
Typical ESR and CSHUNT
fHFXT,SW
(1)
(2)
MAX
3.0 V
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 3, CL,eff = 16 pF,
Typical ESR and CSHUNT
Measured at MCLK or HSMCLK,
fHFXT = 1 MHz to 48 MHz
HFXT oscillator logic-level
square-wave input duty cycle
TYP
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT
HFXT oscillator duty cycle
SW
MIN
40
DCHFXT
DCHFXT,
VCC
fOSC = 1 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT
40%
4
50%
MHz
60%
0.8
48
HFXTBYPASS = 1,
External clock used as a direct source to
MCLK or HSMCLK with no divider
(DIVM = 0 or DIVHS = 0).
45%
55%
HFXTBYPASS = 1,
External clock used as a direct source to
MCLK or HSMCLK with divider (DIVM > 0
or DIVHS > 0) or not used as a direct
source to MCLK or HSMCLK.
40%
60%
MHz
Maximum frequency of operation of the entire device cannot be exceeded.
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-10. High-Frequency Crystal Oscillator, HFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OAHFXT
(3)
Oscillation allowance for
HFXT crystals (3)
MIN
TYP
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 0,
fHFXT,HF = 1 MHz, CL,eff = 16 pF
TEST CONDITIONS
VCC
1225
5000
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 0,
fHFXT,HF = 4 MHz, CL,eff = 16 pF
640
1250
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1,
fHFXT,HF = 8 MHz, CL,eff = 16 pF
360
750
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 2,
fHFXT,HF = 16 MHz, CL,eff = 16 pF
200
425
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 3,
fHFXT,HF = 24 MHz, CL,eff = 16 pF
135
275
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 4,
fHFXT,HF = 32 MHz, CL,eff = 16 pF
110
225
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 5
fHFXT,HF = 40 MHz, CL,eff = 16 pF
105
160
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 6,
fHFXT,HF = 48 MHz, CL,eff = 16 pF
80
140
MAX
UNIT
Ω
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
49
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-10. High-Frequency Crystal Oscillator, HFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,HFXT
TEST CONDITIONS
Start-up time (4)
VCC
MIN
TYP
fOSC = 1 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
4
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
1.8
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
0.7
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 2, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
0.6
MAX
UNIT
ms
3.0 V
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 3, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
450
fOSC = 32 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 4, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
300
fOSC = 40 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 5, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
250
fOSC = 48 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 6, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
250
µs
CHFXIN
Integrated load capacitance at
HFXIN terminal (5) (6)
2
pF
CHFXOUT
Integrated load capacitance at
HFXOUT terminal (5) (6)
2
pF
fFault,HFXT
Oscillator fault frequency (7)
(4)
(5)
(6)
(7)
(8)
50
(8)
400
700
kHz
Does not include programable start-up counter.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT
is the total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. Because the PCB adds
additional capacitance, it must also be considered in the overall capacitance. TI recommends verifying that the recommended effective
load capacitance of the selected crystal is met.
Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX might set the flag. A static
condition or stuck at fault condition will set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-11 lists the characteristics of the DCO.
Table 5-11. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fRSEL0_CTR
fRSEL1_CTR
fRSEL2_CTR
fRSEL3_CTR
fRSEL4_CTR
fRSEL5_CTR
dfDCO/dT
MIN
TYP
MAX
DCO center frequency
accuracy for range 0
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 0, DCOTUNE = 0
TEST CONDITIONS
1.443
1.5
1.557
External resistor mode,
DCORSEL = 0, DCOTUNE = 0
1.482
1.5
1.518
DCO center frequency
accuracy for range 1
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 1, DCOTUNE = 0
2.885
3
3.115
External resistor mode,
DCORSEL = 1, DCOTUNE = 0
2.964
3
3.036
DCO center frequency
accuracy for range 2
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 2, DCOTUNE = 0
5.77
6
6.23
External resistor mode,
DCORSEL = 2, DCOTUNE = 0
5.928
6
6.072
DCO center frequency
accuracy for range 3
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 3, DCOTUNE = 0
11.541
12
12.459
External resistor mode,
DCORSEL = 3, DCOTUNE = 0
11.856
12
12.144
DCO center frequency
accuracy for range 4
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 4, DCOTUNE = 0
23.082
24
24.918
External resistor mode,
DCORSEL = 4, DCOTUNE = 0
23.712
24
24.288
DCO center frequency
accuracy for range 5
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 5, DCOTUNE = 0
46.164
48
49.836
External resistor mode,
DCORSEL = 5, DCOTUNE = 0
47.424
48
48.576
DCO frequency drift with
temperature (1)
VCC, TA
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
Internal resistor mode,
At fixed voltage
1.62 V to 3.7 V
250
External resistor mode (2)
At fixed voltage
1.62 V to 3.7 V
40
–40°C to 85 °C
0.1
%/V
ppm/°C
dfDCO/dVCC
DCO frequency voltage
drift with voltage (3)
At fixed temperature, applicable for
both DCO Internal and External
resistor modes
fRSEL0
DCO frequency range 0
DCORSEL = 0
DCO internal or external resistor
mode
3.0 V, 25℃
0.98
2.26
MHz
fRSEL1
DCO frequency range 1
DCORSEL = 1
DCO internal or external resistor
mode
3.0 V, 25℃
1.96
4.51
MHz
fRSEL2
DCO frequency range 2
DCORSEL = 2
DCO internal or external resistor
mode
3.0 V, 25℃
3.92
9.02
MHz
fRSEL3
DCO frequency range 3
DCORSEL = 3
DCO internal or external resistor
mode
3.0 V, 25℃
7.84
18.04
MHz
fRSEL4
DCO frequency range 4
DCORSEL = 4
DCO internal or external resistor
mode
3.0 V, 25℃
15.68
36.07
MHz
fRSEL5
DCO frequency range 5
DCORSEL = 5
DCO internal or external resistor
mode
3.0 V, 25℃
31.36
52
MHz
fDCO_DC
Duty cycle
(1)
(2)
(3)
47%
50%
53%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Does not include temperature coefficient of external resistor.
Recommended value of external resistor at DCOR pin: 91 kΩ, 0.1%, ±25 ppm/℃.
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
51
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-11. DCO (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tDCO_JITTER
TEST CONDITIONS
DCO period jitter
TYP
MAX
DCORSEL = 5, DCOTUNE = 0
VCC, TA
MIN
50
90
DCORSEL = 4, DCOTUNE = 0
80
120
DCORSEL = 3, DCOTUNE = 0
115
170
DCORSEL = 2, DCOTUNE = 0
160
240
DCORSEL = 1, DCOTUNE = 0
225
340
450
550
DCORSEL = 0, DCOTUNE = 0
UNIT
ps
TDCO_STEP
Step size
Step size of the DCO.
tDCO_SETTLE_RANGE
DCO settling from worst
case DCORSELn to
DCORSELm
DCO settled to within 1.5% of
steady state frequency
10
µs
tDCO_SETTLE_TUNE
DCO settling worst case
DCOTUNEn to
DCOTUNEm within any
DCORSEL setting
DCO settled to within 1.5% of
steady state frequency
10
µs
tSTART
DCO start-up time (4)
DCO settled to within 0.5% of
steady state frequency
(4)
0.2%
5
µs
The maximum parasitic capacitance at the DCO external resistance pin (DCOR) should not exceed 5 pF to ensure the specified DCO
start-up time.
Table 5-12 lists the overall tolerance of the DCO.
Table 5-12. DCO Overall Tolerance
over operating free-air temperature range (unless otherwise noted)
RESISTOR OPTION
Internal resistor
External resistor
with 25-ppm TCR
52
Specifications
TEMPERATURE
CHANGE
TEMPERATURE
DRIFT (%)
VOLTAGE
CHANGE
VOLTAGE DRIFT
(%)
OVERALL DRIFT
(%)
OVERALL
ACCURACY (%)
–40°C to 85 °C
±3.125
1.62 V to 3.7 V
±0.2
±3.325
±3.825
0°C
0
1.62 V to 3.7 V
±0.2
±0.2
±0.7
–40°C to 85 °C
±3.125
0V
0
±3.125
±3.625
–40°C to 85 °C
±0.5
1.62 V to 3.7 V
±0.2
±0.7
±1.2
0°C
0
1.62 V to 3.7 V
±0.2
±0.2
±0.7
–40°C to 85 °C
±0.5
0V
0
±0.5
±1
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-13 lists the characteristics of the internal very-low-power low-frequency oscillator (VLO).
Table 5-13. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption (1)
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift (2)
dfVLO/dVCC
VLO frequency supply voltage drift (3)
DCVLO
Duty cycle
(1)
(2)
(3)
MIN
TYP
MAX
50
6
nA
9.4
14
0.1
kHz
%/°C
0.2
40%
UNIT
%/V
50%
60%
Current measured on DVCC supply
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Table 5-14 lists the characteristics of the internal-reference low-frequency oscillator (REFO) in 32.768‑kHz
mode.
Table 5-14. Internal-Reference Low-Frequency Oscillator (REFO) in 32.768-kHz Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
REFO frequency calibrated
fREFO
REFO absolute tolerance calibrated
dfREFO/dT
REFO frequency temperature drift (3)
dfREFO/dVCC
REFO frequency supply voltage drift (4)
DCREFO
REFO duty cycle
(1)
(2)
(3)
(4)
TYP
REFO current consumption (2)
IREFO
MAX
µA
32.768
kHz
TA = –40°C to 85°C
TA = 25°C
UNIT
0.6
±3%
3V
±1.5%
0.012
%/°C
0.2
%/V
40%
50%
60%
REFO is configured to 32.768-kHz mode with REFOFSEL = 0.
Total current measured on both AVCC and DVCC supplies.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Table 5-15 lists the characteristics of the internal-reference low-frequency oscillator (REFO) in 128‑kHz
mode.
Table 5-15. Internal-Reference Low-Frequency Oscillator (REFO) in 128-kHz Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
REFO
TEST CONDITIONS
VCC
MIN
REFO current consumption (2)
REFO absolute tolerance calibrated
±6%
3V
±1.5%
(3)
REFO frequency temperature drift
dfREFO/dVCC
REFO frequency supply voltage drift (4)
DCREFO
REFO duty cycle
kHz
TA = –40°C to 85°C
TA = 25°C
UNIT
µA
128
dfREFO/dT
(1)
(2)
(3)
(4)
MAX
1
REFO frequency calibrated
fREFO
TYP
0.018
%/°C
0.4
40%
50%
%/V
60%
REFO is configured to 128-kHz mode with REFOFSEL = 1.
Total current measured on both AVCC and DVCC supplies.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
53
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-16 lists the characteristics of the module oscillator (MODOSC).
Table 5-16. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IMODOSC
Current consumption (1)
fMODOSC
MODOSC frequency
dfMODOSC/dT
MODOSC frequency temperature
drift (2)
dfMODOSC/dV
CC
MODOSC frequency supply voltage
drift (3)
DCMODOSC
Duty cycle
(1)
(2)
(3)
VCC
MIN
TYP
MAX
50
23
40%
25
UNIT
µA
27
MHz
0.02
%/℃
0.3
%/V
50%
60%
Total current measured on both AVCC and DVCC supplies.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Table 5-17 lists the characteristics of the system oscillator (SYSOSC).
Table 5-17. System Oscillator (SYSOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISYSOSC
Current consumption (1)
fSYSOSC
SYSOSC frequency
dfSYSOSC/ dT
SYSOSC frequency temperature
drift (2)
dfSYSOSC/
dVCC
SYSOSC frequency supply voltage
drift (3)
DCSYSOSC
Duty cycle
(1)
(2)
(3)
54
VCC
MIN
TYP
MAX
30
4.25
40%
5.0
UNIT
µA
5.75
MHz
0.03
%/℃
0.5
%/V
50%
60%
Current measured on AVCC supply.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.25.4 Power Supply System
Table 5-18 lists the LDO VCORE regulator characteristics.
Table 5-18. VCORE Regulator (LDO) Characteristics
MIN
TYP
MAX
UNIT
VCORE0-HP
Static VCORE voltage Level 0
in active and LPM0 modes
PARAMETER
Device power modes AM_LDO_VCORE0,
LPM0_LDO_VCORE0
TEST CONDITIONS
1.12
1.2
1.28
V
VCORE1-HP
Static VCORE voltage Level 1
in active and LPM0 modes
Device power modes AM_LDO_VCORE1,
LPM0_LDO_VCORE1
1.31
1.4
1.49
V
VCORE0-LF
Static VCORE voltage Level 0
in low-frequency active and low Device power modes AM_LF_VCORE0
frequency LPM0 modes
1.12
1.2
1.28
V
VCORE1-LF
Static VCORE voltage Level 1
in low-frequency active and low Device power modes AM_LF_VCORE1
frequency LPM0 modes
1.31
1.4
1.49
V
VCORE0-LPM34
Static VCORE voltage Level 0
in LPM3 and LPM4 modes
Device power modes LPM3, LPM4
1.08
1.2
1.32
V
VCORE1-LPM34
Static VCORE voltage Level 1
in LPM3 and LPM4 modes
Device power modes LPM3, LPM4
1.27
1.4
1.53
V
VCORE0-LPM35
Static VCORE voltage Level 0
in LPM3.5 mode
Device power mode LPM3.5
1.08
1.2
1.32
V
IINRUSH-ST
Inrush current at start-up
Device power-up
200
mA
IPEAK-LDO
Peak current drawn by LDO
from DVCC
350
mA
ISC-coreLDO
Short circuit current limit for
core LDO
300
mA
Measured when output is shorted to ground
Table 5-19 lists the DC-DC VCORE regulator characteristics.
Table 5-19. VCORE Regulator (DC-DC) Characteristics
PARAMETER
DVCC-DCDC
VDCDC_SO
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Allowed DVCC range for DC-DC
operation
DCDC_FORCE = 1
1.8
3.7
V
DC-DC to LDO switch over
voltage
dDVCC/dt = 1 V/ms, DCDC_FORCE = 0
1.8
2.0
V
VCORE0-DCDC
Device power modes
Static VCORE voltage Level 0 in
AM_DCDC_VCORE0,
DC-DC high-performance modes
LPM0_DCDC_VCORE0
1.12
1.2
1.28
V
VCORE1-DCDC
Device power modes
Static VCORE voltage Level 1 in
AM_DCDC_VCORE1,
DC-DC high-performance modes
LPM0_DCDC_VCORE1
1.31
1.4
1.49
V
IPEAK-DCDC
Peak current drawn by DC-DC
from DVCC
300
mA
ISC-DCDC
Short circuit current limit for DCDC
500
mA
(1)
Measured when output is shorted to
ground
When DVCC falls below this voltage, internally the regulator switches over to LDO from DC-DC.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
55
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-20 lists the VCCDET characteristics.
Table 5-20. PSS, VCCDET
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VVCC_VCCDET-
VCCDET power-down level
dDVCC/dt < 3 V/s (1)
- trip point with falling VCC
0.64
1.12
1.55
V
VVCC_VCCDET+
VCCDET power-up level trip point with rising VCC
0.70
1.18
1.59
V
VVCC_VCC_hys
VCCDET hysteresis
30
65
100
mV
(1)
TEST CONDITIONS
dDVCC/dt < 3 V/s (1)
The VCCDET levels are measured with a slow-changing supply. Faster slopes can result in different levels.
Table 5-21 lists the SVSMH characteristics.
Table 5-21. PSS, SVSMH
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISVSMH
VSVSMH-,HP
VSVSMH+,HP
56
TEST CONDITIONS
SVSMH current consumption,
low-power mode
SVSMH current consumption,
high-performance mode
SVSMH threshold level during
high-performance mode
(falling DVCC)
SVSMH threshold level; High
Performance Mode [rising
DVCC]
Specifications
MIN
TYP
MAX
UNIT
SVSMHOFF = 0, SVSMHLP = 1
200
400
nA
SVSMHOFF = 0, SVSMHLP = 0
7
10
μA
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 0,
DC (dDVCC/dt < 1V/s)
1.59
1.64
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 1,
DC (dDVCC/dt < 1V/s)
1.59
1.64
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 2,
DC (dDVCC/dt < 1V/s)
1.59
1.64
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 3,
DC (dDVCC/dt < 1V/s)
2.0
2.06
2.12
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 4,
DC (dDVCC/dt < 1V/s)
2.2
2.26
2.32
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 5,
DC (dDVCC/dt < 1V/s)
2.4
2.47
2.54
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 6,
DC (dDVCC/dt < 1V/s)
2.7
2.79
2.88
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 7,
DC (dDVCC/dt < 1V/s)
2.9
3.0
3.1
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 0,
DC (dDVCC/dt < 1V/s)
1.6
1.66
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 1,
DC (dDVCC/dt < 1V/s)
1.6
1.66
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 2,
DC (dDVCC/dt < 1V/s)
1.6
1.66
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 3,
DC (dDVCC/dt < 1V/s)
2.02
2.07
2.14
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 4,
DC (dDVCC/dt < 1V/s)
2.22
2.27
2.34
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 5,
DC (dDVCC/dt < 1V/s)
2.42
2.48
2.56
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 6,
DC (dDVCC/dt < 1V/s)
2.72
2.8
2.9
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 7,
DC (dDVCC/dt < 1V/s)
2.92
3.01
3.12
V
V
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-21. PSS, SVSMH (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VSVSMH-,LP
VSVSMH_hys
tPD,SVSMH
t(SVSMH)
(1)
TEST CONDITIONS
SVSMH threshold level; Low
Power Mode [falling DVCC]
MIN
TYP
MAX
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 0,
DC (dDVCC/dt < 1V/s)
1.55
1.62
1.71
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 1,
DC (dDVCC/dt < 1V/s)
1.55
1.62
1.71
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 2,
DC (dDVCC/dt < 1V/s)
1.55
1.62
1.71
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 3,
DC (dDVCC/dt < 1V/s)
2.0
2.09
2.18
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 4,
DC (dDVCC/dt < 1V/s)
2.2
2.3
2.4
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 5,
DC (dDVCC/dt < 1V/s)
2.4
2.51
2.62
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 6,
DC (dDVCC/dt < 1V/s)
2.7
2.83
2.94
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 7,
DC (dDVCC/dt < 1V/s)
2.87
3.0
3.13
15
30
SVSMH hysteresis
UNIT
V
SVSH propagation delay,
high-performance mode
SVSMHOFF = 0, SVSMHLP = 0,
very fast dVDVCC/dt
3
10
SVSH propagation delay, lowpower mode
SVSMHOFF = 0, SVSMHLP = 1,
very fast dVDVCC/dt
25
100
SVSMH on or off delay time
SVSMHOFF = 1 → 0, SVSMHLP = 0
17
40
mV
μs
(1)
μs
If the SVSMH is kept disabled in active mode and is enabled before entering a low-power mode of the device (LPM3, LPM4, LPM3.5, or
LPM4.5) care should be taken that sufficient time has elapsed since enabling of the module before entry into the device low-power
mode to allow for successful wake up of the SVSMH module per the SVSMH on or off delay time specification. Otherwise, SVSMH may
trip, causing the device to reset and wake up from the low-power mode.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
57
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.25.5 Digital I/Os
Table 5-22 lists the characteristics of the digital inputs.
Table 5-22. Digital Inputs (Applies to Both Normal and High-Drive I/Os)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
0.99
TYP
MAX
1.65
3V
1.35
2.25
2.2 V
0.55
1.21
3V
0.75
1.65
2.2 V
0.32
0.84
3V
0.4
1.0
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins shared with
analog functions
VIN = VSS or VCC
5
pF
Ilkg,ndio
Normal I/O high-impedance input leakage
current
See
(1) (2)
2.2 V, 3 V
±20
nA
Ilkg,hdio
High-drive I/O high-impedance input leakage
current
See
(1) (2)
2.2 V, 3 V
±20
nA
tint
tRST
(1)
(2)
(3)
(4)
(5)
58
External interrupt timing (external trigger
pulse duration to set interrupt flag)
External reset pulse duration on RSTn pin (5)
20
Ports with interrupt capability and
without glitch filter (3)
2.2 V, 3 V
20
Ports with interrupt capability and
with glitch filter but glitch filter
disabled (GLTFLT_EN = 0) (3)
2.2 V, 3 V
20
Ports with interrupt capability and
with glitch filter, glitch filter enabled
(GLTFTL_EN = 1) (4)
2.2 V, 3 V
0.25
2.2 V, 3 V
1
30
40
V
V
V
kΩ
ns
1
µs
µs
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration tint is met. It may be set by trigger signals
shorter than tint.
A trigger pulse duration less than the MIN value is always filtered, and a trigger pulse duration more than the MAX value is always
passed. The trigger pulse may or may not be filtered if the duration is between the MIN and MAX values.
Not applicable if RSTn/NMI pin configured as NMI.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
Table 5-23 lists the characteristics of the normal-drive digital outputs. See Figure 5-19 through Figure 5-22
for the typical characteristics graphs.
Table 5-23. Digital Outputs, Normal I/Os
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
I(OHmax) = –1 mA (1)
VOH
2.2 V
I(OHmax) = –3 mA (2)
High-level output voltage
I(OHmax) = –2 mA (1)
3.0 V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
VOL
2.2 V
I(OLmax) = 3 mA (2)
Low-level output voltage
I(OLmax) = 2 mA (1)
3.0 V
I(OLmax) = 6 mA (2)
Port output frequency (with RC
load) (3)
fPx.y
dPx.y
fPort_CLK
dPort_CLK
trise,dig
tfall,dig
trise,ana
tfall,ana
(1)
(2)
(3)
(4)
(5)
(6)
(7)
VCORE = 1.4 V, CL = 20 pF, RL
Port output duty cycle (with RC
Load)
VCORE = 1.4 V, CL = 20 pF, RL
Clock output frequency (3)
VCORE = 1.4 V, CL = 20 pF (5)
Clock output duty cycle
VCORE = 1.4 V, CL = 20 pF
Port output rise time, digital only
port pins
Port output fall time, digital only
port pins
Port output rise time, port pins
with shared analog functions
Port output fall time, port pins
with shared analog functions
CL = 20 pF
CL = 20 pF
CL = 20 pF
CL = 20 pF
(6)
(7)
(6)
(7)
(5)
(4) (5)
(4) (5)
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
40%
60%
2.2 V
40%
60%
3.0 V
45%
55%
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
40%
60%
2.2 V
40%
60%
3.0 V
45%
55%
UNIT
V
V
MHz
MHz
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit - it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 3.2kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 20% and 80% VCC at the specified toggle frequency.
Measured between 20% of VCC to 80% of VCC.
Measured between 80% of VCC to 20% of VCC.
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
59
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
Table 5-24 lists the characteristics of the high-drive digital outputs. See Figure 5-23 through Figure 5-26
for the typical characteristics graphs.
Table 5-24. Digital Outputs, High-Drive I/Os
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
I(OHmax) = –5 mA (1)
VOH
2.2 V
I(OHmax) = –15 mA (2)
High-level output voltage
I(OHmax) = –10 mA (1)
3.0 V
I(OHmax) = –20 mA (2)
I(OLmax) = 5 mA (1)
VOL
2.2 V
I(OLmax) = 15 mA (2)
Low-level output voltage
I(OLmax) = 10 mA (1)
3.0 V
I(OLmax) = 20 mA (2)
Port output frequency (with RC
load) (3)
fPx.y
Port output duty cycle (with RC
Load)
dPx.y
fPort_CLK
dPort_CLK
trise
(2)
(3)
(4)
(5)
(6)
(7)
Clock output duty cycle
Port output rise time
tfall
(1)
Clock output frequency (3)
Port output fall time
VCORE = 1.4 V, CL = 80 pF, RL
VCORE = 1.4 V, CL = 80 pF, RL
(4) (5)
(4) (5)
VCORE = 1.4 V, CL = 80 pF (5)
VCORE = 1.4 V, CL = 80 pF
CL = 80 pF
CL = 80 pF
(5)
(6)
(7)
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.50
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.50
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
45%
55%
2.2 V
45%
55%
3.0 V
45%
55%
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
45%
55%
2.2 V
45%
55%
3.0 V
45%
55%
UNIT
V
V
MHz
MHz
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit, and it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 3.2 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 80 pF is connected to the output to VSS.
The output voltage reaches at least 20% and 80% VCC at the specified toggle frequency.
Measured between 20% of VCC to 80% of VCC.
Measured between 80% of VCC to 20% of VCC.
Table 5-25 lists the frequencies of the pin-oscillator ports. See Figure 5-27 and Figure 5-28 for the typical
characteristics graphs.
Table 5-25. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foPx.y
(1)
60
Pin-oscillator frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Px.y, CL = 10 pF (1)
3.0 V
1900
kHz
Px.y, CL = 20 pF (1)
3.0 V
1150
kHz
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
Specifications
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
18
30
16
27
Low-Level Output Current (mA)
Low-Level Output Current (mA)
5.25.5.1 Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
14
12
10
8
6
4
2
TA = 25°C
TA = 85°C
0
24
21
18
15
12
9
6
3
TA = 25°C
TA = 85°C
0
-2
-3
0
0.25
0.5
0.75
1
1.25 1.5 1.75
Low-Level Output Voltage (V)
VCC = 2.2 V
2
2.25
0
P7.0
0.6
0.9 1.2 1.5 1.8 2.1 2.4
Low-Level Output Voltage (V)
VCC = 3.0 V
Figure 5-19. Low-Level Output Voltage vs
Low-Level Output Current
2.7
3
D010
P7.0
Figure 5-20. Low-Level Output Voltage vs
Low-Level Output Current
0
0
TA = 25°C
TA = 85°C
-2
-4
-6
-8
-10
-12
-14
-6
-9
-12
-15
-18
-21
-24
-27
-16
-30
-18
-33
0
0.25
0.5
VCC = 2.2 V
TA = 25°C
TA = 85°C
-3
High-Level Output Current (mA)
High-Level Output Current (mA)
0.3
D006
0.75
1
1.25 1.5 1.75
High-Level Output Voltage (V)
2
P7.0
Figure 5-21. High-Level Output Voltage vs
High-Level Output Current
2.25
0
0.3
0.6
D004
0.9 1.2 1.5 1.8 2.1 2.4
High-Level Output Voltage (V)
VCC = 3.0 V
2.7
3
D008
P7.0
Figure 5-22. High-Level Output Voltage vs
High-Level Output Current
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
61
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.25.5.2 Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
160
100
Low-Level Output Current (mA)
Low-Level Output Current (mA)
90
80
70
60
50
40
30
20
10
TA = 25°C
TA = 85°C
0
-10
140
120
100
80
60
40
20
TA = 25°C
TA = 85°C
0
0
0.25
0.5
0.75
1
1.25 1.5 1.75
Low-Level Output Voltage (V)
VCC = 2.2 V
2
2.25
0
P2.1
0.9 1.2 1.5 1.8 2.1 2.4
Low-Level Output Voltage (V)
2.7
3
D009
P2.1
Figure 5-24. Low-Level Output Voltage vs
Low-Level Output Current
0
-5
TA = 25°C
TA = 85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0.6
VCC = 3.0 V
Figure 5-23. Low-Level Output Voltage vs
Low-Level Output Current
-15
-25
-35
-45
-55
-65
-75
-85
0
0.25
0.5
VCC = 2.2 V
0.75
1
1.25 1.5 1.75
High-Level Output Voltage (V)
2
P2.1
Figure 5-25. High-Level Output Voltage vs
High-Level Output Current
62
0.3
D005
Specifications
2.25
TA = 25°C
TA = 85°C
-20
-40
-60
-80
-100
-120
-140
-160
0
0.3
0.6
D003
0.9 1.2 1.5 1.8 2.1 2.4
High-Level Output Voltage (V)
VCC = 3.0 V
2.7
3
D007
P2.1
Figure 5-26. High-Level Output Voltage vs
High-Level Output Current
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
MSP432P401R, MSP432P401M
www.ti.com
SLAS826F – MARCH 2015 – REVISED MARCH 2017
5.25.5.3 Typical Characteristics, Pin-Oscillator Frequency
1750
TA = 25°C
TA = 85°C
1800
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
2100
1500
1200
900
600
300
10
20
30
40
50
Load Capacitance (pF)
One output active at a time
60 70 80
100
D002
VCC = 3.0 V
Figure 5-27. Load Capacitance vs Pin Oscillator Frequency
TA = 25°C
TA = 85°C
1500
1250
1000
750
500
250
10
20
30
40
50
Load Capacitance (pF)
One output active at a time
60 70 80
100
D001
VCC = 2.2 V
Figure 5-28. Load Capacitance vs Pin Oscillator Frequency
Copyright © 2015–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P401R MSP432P401M
Specifications
63
MSP432P401R, MSP432P401M
SLAS826F – MARCH 2015 – REVISED MARCH 2017
www.ti.com
5.25.6 14-Bit ADC
Table 5-26 lists the power supply and input range conditions for the ADC.
Table 5-26. 14-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V,
ADC14PWRMD = 2
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V,
ADC14PWRMD = 0
V(Ax)
Analog input voltage
range (1)
All ADC analog input pins Ax
0
VCM
Input common-mode range
All ADC analog input pins Ax (ADC14DIF = 1)
0
I(ADC14)
single-ended
mode
I(ADC14)
differential
mode
CI
RI
(1)
(2)
(3)
64
Operating supply current
into AVCC and DVCC
terminals (2)
Operating supply current
into AVCC and DVCC
terminals (2)
MAX
3.7
V
1.8
3.7
V
AVCC
V
VREF
/2
VREF
V
3.0 V
490
640
2.2 V
450
580
fADC14CLK = 5 MHz,
200 ksps (ADC14PWRMD = 2),
ADC14ON = 1, ADC14DIF = 0,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
215
270
2.2 V
210
260
fADC14CLK = 25 MHz,
1 Msps (ADC14PWRMD = 0),
ADC14ON = 1, ADC14DIF = 1,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
690
875
2.2 V
620
785
fADC14CLK = 5 MHz,
200 ksps (ADC14PWRMD = 2),
ADC14ON = 1, ADC14DIF = 1,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
275
335
2.2 V
260
320
12
15
1.8 V to
3.7 V
0.135
1
1.62 V to
工商网监
湘ICP备2023018690号
