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1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Basys 2™ FPGA Board Reference Manual Revised April 8, 2016 This manual applies to the Basys 2 rev. C Overview The Basys 2 board is a circuit design and implementation platform that anyone can use to gain experience building real digital circuits. Built around a Xilinx Spartan-3E Field Programmable Gate Array and a Atmel AT90USB2 USB controller, the Basys 2 board provides complete, ready-to-use hardware suitable for hosting circuits ranging from basic logic devices to complex controllers. A large collection of on-board I/O devices and all required FPGA support circuits are included, so countless designs can be created without the need for any other components. Full Speed USB2 Port (JTAG and data transfers) Data port 20 Platform Flash Settable Clock Source (config ROM) (25 / 50 / 100 MHz)   JTAG port  Xilinx Spartan3E-100 CP132 32 2 8 bit color 4 JA I/O Devices PS/2 Port VGA Port  4 JB 4 JC 4 JD Pmod Connectors     100,000-gate Xilinx Spartan 3E FPGA Atmel AT90USB2 Full-speed USB2 port providing board power and programming/data transfer interface Xilinx Platform Flash ROM to store FPGA configurations 8 LEDs, 4-digit 7-segment display, 4 buttons, 8 slide switches PS/2 port and 8-bit VGA port User-settable clock (25/50/100MHz), plus socket for 2nd clock Four 6-pin header expansion connectors ESD and short-circuit protection on all I/O signals. Figure 1. The Basys 2 board block diagram and features. Four standard expansion ports allow designs to grow beyond the Basys 2 board using breadboards, user-designed circuit boards, or Pmods (Pmods are inexpensive analog and digital I/O modules that offer A/D & D/A conversion, motor drivers, sensor inputs, and many other features). Signals on the 6-pin connectors are protected against ESD damage and short-circuits, ensuring a long operating life in any environment. The Basys 2 board works seamlessly with all versions of the Xilinx ISE tools, including the free WebPack. It ships with a USB cable that provides power and a programming interface, so no other power supplies or programming cables are required. The Basys 2 board can draw power and be programmed via its on-board USB2 port. Digilent’s freely available PCbased Adept software automatically detects the Basys 2 board, provides a programming interface for the FPGA and Platform Flash ROM, and allows user data transfers (see www.digilentinc.com for more information). DOC#: 502-155 Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 1 of 12 Basys2™ FPGA Board Reference Manual The Basys 2 board is designed to work with the free ISE WebPack CAD software from Xilinx. WebPack can be used to define circuits using schematics or HDLs, to simulate and synthesize circuits, and to create programming files. WebPack can be downloaded free of charge from www.xilinx.com/ise/. The Basys 2 board ships with a built-in self-test/demo stored in its ROM that can be used to test all board features. To run the test, set the Mode Jumper (see below) to ROM and apply board power. If the test is erased from the ROM, it can be downloaded and reinstalled at any time. See Basys 2 for the test project as well as further documentation, reference designs, and tutorials. 1 Board Power The Basys 2 board is typically powered from a USB cable, but a battery connector is also provided so that external supplies can be used. To use USB power, simply attach the USB cable. To power the Basys 2 using a battery or other external source, attach a 3.5V-5.5V battery pack (or other power source) to the 2-pin, 100-mil spaced battery connector (three AA cells in series make a good 4.5+/- volt supply). Voltages higher than 5.5V on either power connector may cause permanent damage. Input power is routed through the power switch (SW8) to the four 6-pin expansion connectors and to a Linear Technology LTC3545 voltage regulator. The LTC3545 produces the main 3.3V supply for the board, and it also produces 2.5V and 1.2V supply voltages required by the FPGA. Total Figure 2. Basys 2 power circuits. board current is dependent on FPGA configuration, clock frequency, and external connections. In test circuits with roughly 20K gates routed, a 50MHz clock source, and all LEDs illuminated, about 100mA of current is drawn from the 1.2V supply, 50mA from the 2.5V supply, and 50mA from the 3.3V supply. Required current will increase if larger circuits are configured in the FPGA, or if peripheral boards are attached. The Basys 2 board uses a four layer PCB, with the inner layers dedicated to VCC and GND planes. The FPGA and the other ICs on the board have large complements of ceramic bypass capacitors placed as close as possible to each VCC pin, resulting in a very clean, low-noise power supply. 2 Configuration After power-on, the FPGA on the Basys 2 board must be configured before it can perform any useful functions. During configuration, a “bit” file is transferred into memory cells within the FPGA to define the logical functions and circuit interconnects. The free ISE/WebPack CAD software from Xilinx can be used to create bit files from VHDL, Verilog, or schematic-based source files. Digilent’s PC-based program called Adept can be used to configure the FPGA with any suitable bit file stored on the computer. Adept uses the USB cable to transfer a selected bit file from the PC to the FPGA (via the FPGA’s JTAG programming port). Adept can also program a bit file into an on-board non-volatile ROM called “Platform Flash”. Once programmed, the Platform Flash can automatically transfer a stored bit file to the FPGA at a subsequent power-on or reset event if the Mode Jumper (JP3) is set to ROM. The FPGA will remain configured until it is reset by a power-cycle event. The Platform Flash ROM will retain a bit file until it is reprogrammed, regardless of powercycle events. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 2 of 12 Basys2™ FPGA Board Reference Manual 3 Atmel AT90USB2 Mode Jumper PC USB miniB connector JTAG To program the Basys 2 board, set the mode jumper to PC and attach the USB cable to the board. Start the Adept software, and wait for the FPGA and the Platform Flash ROM to be recognized. Use the browse function to associate the desired .bit file with the FPGA, and/or the desired .mcs file with the Platform Flash ROM. Right-click on the device to be programmed, and select the “program” function. The configuration file will be sent to the FPGA or Platform Flash, and the software will indicate whether programming was successful. The “Status LED” LED (LD_8) will also blink after the FPGA has been successfully configured. For further information on using Adept, please see the Adept documentation available at the Digilent website. ROM LD8 Spartan 3E FPGA XCF02 Platform Flash JTAG port Slave serial port Figure 4. Basys 2 Programming Circuits. Oscillators The Basys 2 board includes a primary, user-settable silicon oscillator that produces 25MHz, 50MHz, or 100MHz based on the position of the clock select jumper at JP4. Initially, this jumper is not loaded and must be soldered in place. A socket for a second oscillator is provided at IC6 (the IC6 socket can accommodate any 3.3V CMOS oscillator in a halfsize DIP package). The primary and secondary oscillators are connected to global clock input pins at pin B8 and pin M6 respectively. Both clock inputs can drive the clock synthesizer DLL on the Spartan 3E, allowing for a wide range if internal frequencies, from 4 times the input frequency to any integer divisor of the input frequency. Spartan-3E FPGA Linear Tech. LTC6905 Oscillator Frequency Select Jumper The primary silicon oscillator is flexible and inexpensive, but it lacks the frequency stability of a crystal oscillator. Some B8 CLK_OUT circuits that drive a VGA monitor may realize a slight improvement in image stability by using a crystal oscillator Figure 5. Basys 2 oscillator circuits. installed in the IC6 socket. For these applications, a 25MHz (or 50MHz) crystal oscillator, available from any catalog distributor, is recommended (see for example part number SG-8002JF-PCC at www.digikey.com ). Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 3 of 12 25MHz 50MHz 100MHz Basys2™ FPGA Board Reference Manual 4 User I/O Four pushbuttons and eight slide switches are provided for circuit inputs. Pushbutton inputs are normally low and driven high only when the pushbutton is pressed. Slide switches generate constant high or low inputs depending on position. Pushbuttons and slide switches all have series resistors for protection against short circuits (a short circuit would occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). Eight LEDs and a four-digit seven-segment LED display are provided for circuit outputs. LED anodes are driven from the FPGA via current-limiting resistors, so they will illuminate when a logic ‘1’ is written to the corresponding FPGA pin. A ninth LED is provided as a power-indicator LED, and a tenth LED (LD-D) illuminates any time the FPGA has been successfully programmed. 4.1 Seven-segment display Each of the four digits of the seven-segment LED display is composed of seven LED segments arranged in a “figure 8” pattern. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful. The anodes of the seven LEDs forming each digit are tied together into one common anode circuit node, but the LED cathodes remain separate. The common anode signals are available as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG (so, for example, the four “D” cathodes from the four digits are grouped together into a single circuit node called “CD”). These seven cathode signals are available as inputs to the 4-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted. A scanning display controller circuit can be used to show a four-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession, at an update rate that is faster than the human eye response. Each digit is illuminated just one-quarter of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update or “refresh” rate is slowed to a given point (around 45 hertz), then most people will begin to see the display flicker. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 4 of 12 Basys2™ FPGA Board Reference Manual Common anode AN1 AN2 AN3 AN4 A F CA CB CC CD CE CF CG DP G E B C DP Four-digit Seven Segment Display An un-illuminated seven-segment display, and nine illumination patterns corresponding to decimal digits D Individual cathodes Figure 7. Seven-segment display. For each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms (for a refresh frequency of 1KHz to Refresh period = 1ms to 16ms 60Hz). For example, in a 60Hz refresh scheme, the entire display would be refreshed once every Digit period = Refresh / 4 16ms, and each digit would be illuminated for ¼ AN0 of the refresh cycle, or 4ms. The controller must AN1 assure that the correct cathode pattern is AN2 present when the corresponding anode signal is driven. To illustrate the process, if AN1 is AN3 asserted while CB and CC are asserted, then a Cathodes Digit 0 Digit 1 Digit 2 Digit 3 “1” will be displayed in digit position 1. Then, if AN2 is asserted while CA, CB and CC are Figure 8. Multiplexed 7seg display timing. asserted, then a “7” will be displayed in digit position 2. If A1 and CB, CC are driven for 4ms, and then A2 and CA, CB, CC are driven for 4ms in an endless succession, the display will show “17” in the first two digits. Figure 8 shows an example timing diagram for a fourdigit seven-segment controller. 5 PS/2 Port The 6-pin mini-DIN connector can accommodate a PS/2 mouse or keyboard. The PS/2 connector is supplied with 5VDC. Both the mouse and keyboard use a two-wire serial bus (clock and data) to communicate with a host device. Both use 11-bit words that include a start, stop and odd parity bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in the figure. The clock and data signals are only driven when data transfers occur, and otherwise they are held in the “idle” state at logic ‘1’. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 5 of 12 Basys2™ FPGA Board Reference Manual 8 6 5 3 2 5 1 2 8 1 3 Pin1: Data Pin2: Data Pin3: GND Pin5: Vdd Pin6: Clock Pin8: Clock Spartan 3E FPGA 200 W B1 200 W C3 CLK DATA 6-pin mini-DIN 6 (bottom up) Figure 9. PS/2 connector and Basys 2 PS/2 circuit. 5.1 Keyboard The keyboard uses open-collector drivers so the keyboard or an attached host device can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports). Tck Tck Edge 0 ‘0’ start bit Edge 10 ‘1’ stop bit Thld Tsu Symbol Parameter Min PS2-style keyboards use scan codes to communicate key press Clock time 30us T CK data. Each key is assigned a code that is sent whenever the key Data-to-clock setup time 5us TSU is pressed; if the key is held down, the scan code will be sent THLD Clock-to-data hold time 5us repeatedly about once every 100ms. When a key is released, a Figure 10. PS/2 signal timing “F0” key-up code is sent, followed by the scan code of the released key. If a key can be “shifted” to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an “E0” ahead of the scan code (and they may send more than one scan code). When an extended key is released, an “E0 F0” key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host device can also send data to the keyboard. Below is a short list of some common commands a host might send. ED Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns “FA” after receiving “ED”, then host sends a byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets Num Lock; and Bit 2 sets Caps lock. Bits 3 to 7 are ignored. EE Echo (test). Keyboard returns “EE” after receiving “EE”. F3 Set scan code repeat rate. Keyboard returns “F3” on receiving “FA”, then host sends second byte to set the repeat rate. FE Resend. “FE” directs keyboard to re-send most recent scan code. FF Reset. Resets the keyboard. Max 50us 25us 25us The keyboard can send data to the host only when both the data and clock lines are high (or idle). Since the host is the “bus master”, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host pulls the clock line low, the keyboard must not send any data until the clock is released. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 6 of 12 Basys2™ FPGA Board Reference Manual The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the falling edge of the clock. ESC 76 `~ 0E 1! 16 TAB 0D F1 05 F2 06 F3 04 F4 0C 2@ 1E 3# 26 4$ 25 5% 2E Q 15 Caps Lock 58 W 1D A 1C Shift 12 S 1B Z 1Z Ctrl 14 E 24 F5 03 R 2D D 23 X 22 6^ 36 T 2C F 2B C 21 F6 0B 7& 3D Y 35 G 34 V 2A F8 0A 8* 3E U 3C H 33 B 32 Alt 11 F7 83 9( 46 I 43 J 3B N 31 F9 01 0) 45 O 44 K 42 M 3A F10 09 -_ 4E P 4D L 4B ,< 41 =+ 55 [{ 54 ;: 4C >. 49 /? 4A Space 29 Alt E0 11 F11 78 F12 07 E0 75 BackSpace 66 E0 74 ]} 5B '" 52 \| 5D Enter 5A E0 6B E0 72 Shift 59 Ctrl E0 14 Figure 11. Keyboard scan codes. 5.2 Mouse The mouse outputs a clock and data signal when it is moved; otherwise, these signals remain at logic ‘1’. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz. The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a ‘1’ indicates the button is being pressed). Mouse status byte 1 0 L R 0 Start bit 1 XS YS XY YY P Stop bit X direction byte 1 0 Y direction byte X0 X1 X2 X3 X4 X5 X6 X7 P Start bit Stop bit Idle state 1 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P Start bit 1 Stop bit Idle state Figure 12. Mouse data format. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 7 of 12 Basys2™ FPGA Board Reference Manual 6 VGA Port The Basys 2 board uses 10 FPGA signals to create a VGA port with 8-bit color and the two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync). The color signals use resistor-divider circuits that work in conjunction with the 75-ohm termination resistance of the VGA display to create eight signal levels on the red and green VGA signals, and four on blue (the human eye is less sensitive to blue levels). This circuit, shown in figure 13, produces video color signals that proceed in equal increments between 0V (fully off) and 0.7V (fully on). A video controller circuit must be created in the FPGA to drive the sync and color signals with the correct timing in order to produce a working display system. 6.2 VGA System Timing VGA signal timings are specified, published, copyrighted and sold by the VESA organization (www.vesa.org). The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode. For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website. CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains Anode (entire screen) to both CRTs and LCDs). Color CRT displays use three Cathode ray tube electron beams (one for red, one for blue, and one for Deflection coils green) to energize the phosphor that coats the inner Grid Electron guns side of the display end of a cathode ray tube (see (Red, Blue, Green) illustration). Electron beams emanate from “electron Cathode ray guns” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate R,G,B signals (to guns) called a “grid”. The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that VGA cable flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under High voltage deflection grid gun supply (>20kV) control control control the influence of the much larger electrostatic force that results from the entire phosphor-coated display Figure 14. CRT deflection system surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow. Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. As the cathode ray moves over the surface of the display, the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 8 of 12 Basys2™ FPGA Board Reference Manual Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution. Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution by producing timing pixel 0,0 pixel 0,639 signals to control the raster patterns. The 640 pixels per row are displayed controller must produce synchronizing pulses during forward beam trace at 3.3V (or 5V) to set the frequency at which current flows through the deflection coils, and Retrace - no it must ensure that video data is applied to information Display Surface displayed the electron guns at the correct time. Raster during this video displays define a number of “rows” that time corresponds to the number of horizontal pixel 479,0 pixel 479,639 passes the cathode makes over the display area, and a number of “columns” that corresponds to an area on each row that is Stable current ramp - information assigned to one “picture element” or pixel. is displayed during this time Typical displays use from 240 to 1200 rows Current and from 320 to 1600 columns. The overall waveform size of a display and the number of rows and through horizontal columns determines the size of each pixel. Total horizontal time Video data typically comes from a video refresh memory, with one or more bytes assigned to each pixel location (the Basys 2 uses three bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel. defletion coil retrace time Horizontal display time time HS A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in the table at right "front porch" Horizontal sync signal sets retrace frequency "back porch" Figure 15. VGA system signals. TS Tfp Tdisp T pw Symbol Parameter TS Sync pulse T disp Display time Tbp Horiz. Sync Vertical Sync Time Clocks Lines Time Clks 16.7ms 416,800 521 32 us 800 15.36ms 384,000 480 25.6 us 640 T pw Pulse width 64 us 1,600 2 3.84 us 96 T fp Front porch 320 us 8,000 10 640 ns 16 T bp Back porch 928 us 23,200 29 1.92 us 48 Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Figure 16. VGA system timings for 640x480 display Page 9 of 12 Basys2™ FPGA Board Reference Manual can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays. A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. This counter can be used to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and this counter can be used to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so the designer can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. 7 Expansion Connectors (6-pin Headers) The Basys 2 board provides four 6-pin peripheral module connectors. Each connector provides Vdd, GND, and four unique FPGA signals. Several 6-pin module boards that can attach to this connector are available from Digilent, including A/D converters, speaker amplifiers, microphones, H-bridge amplifiers, etc. Please see www.digilentinc.com for more information. Short-circuit protection resistors B2 A3 J3 B5 Spartan 3E FPGA 1 2 3 4 5 6 6-pin header JA ESD protection 3.3V diodes C6 B6 C5 B7 1 2 3 4 6-pin header A9 B9 A10 C9 1 2 3 4 6-pin header C12 A13 C13 D12 1 2 3 4 6-pin header JB JC JD Figure 18. Basys 2 Pmod port circuits. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 10 of 12 Basys2™ FPGA Board Reference Manual 8 FPGA Pin Definitions The table below shows all pin definitions for the Spartan-3E on the Basys 2 board. Pins in grey boxes are not available to the user. FPGA pin definition table color key Grey Not available to user Green User I/O devices Yellow Data ports Tan Pmod port signals Blue USB signals Basys 2 Spartan-3E pin definitions Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal C12 A13 A12 B12 B11 C11 C6 B6 C5 B5 C4 B4 A3 A10 C9 B9 A9 B8 C8 A7 B7 P4 JD1 JD2 NC NC NC BTN1 JB1 JB2 JB3 JA4 NC SW3 JA2 JC3 JC4 JC2 JC1 MCLK RCCLK BTN3 JB4 LD6 P11 M2 N2 M9 N9 M10 N10 M11 N11 P12 N3 M6 P6 P7 M4 N4 M5 N5 G14 G13 F12 K13 SW0 USB-DB1 USB-DB0 NC NC NC NC LD1 CD CE SW7 UCLK LD3 LD2 BTN2 LD5 LD0 LD4 GRN2 GRN1 AN0 VSYNC N14 N13 M13 M12 L14 L13 F13 F14 D12 D13 C13 C14 G12 K14 J12 J13 J14 H13 H12 J3 K3 B1 CC DP AN2 CG CA CF RED2 GRN0 JD4 RED1 JD3 RED0 BTN0 AN3 AN1 BLU2 HSYNC BLU1 CB JA3 SW2 PS2C B2 C2 C3 D1 D2 L2 L1 M1 L3 E2 F3 F2 F1 G1 G3 H1 H2 H3 B14 B13 A2 A14 JA1 USB-WRITE PS2D NC USB-WAIT USB-DB4 USB-DB3 USB-DB2 SW1 SW6 SW5 USB-ASTB USB-DSTB LD7 SW4 USB-DB6 USB-DB5 USB-DB7 TMS TCK-FPGA TDO-USB TDO-S3 P8 N7 N6 N12 P13 A1 N8 N1 P1 B3 A4 A8 C1 C7 C10 E3 E14 G2 H14 J1 K12 M3 MODE0 MODE1 MODE2 CCLK DONE PROG DIN INIT NC GND GND GND GND GND GND GND GND GND GND GND GND GND M7 P5 P10 P14 A6 B10 E13 M14 P3 M8 E1 J2 A5 E12 K1 P9 A11 D3 D14 K2 L12 P2 GND GND GND GND VDDO-3 VDDO-3 VDDO-3 VDDO-3 VDDO-3 VDDO-3 VDDO-3 VDDO-3 VDDO-2 VDDO-2 VDDO-2 VDDO-2 VDDO-1 VDDO-1 VDDO-1 VDDO-1 VDDO-1 VDDO-1 9 Built-In Self Test The Basys 2 board comes preloaded with a simple self test/demonstration project stored in its ROM. The demo project (available at the website) shows how the Xilinx CAD tools connect FPGA signals to Basys 2 circuits. Since the project is stored in ROM, it can also be used to check board functions. To run the demo, set the ROM/USB jumper (JP3) to ROM and apply power to the board; the seven-segment display will show counting digits, the switches will turn on individual LEDs, the buttons will turn off individual digits on the seven segment display, and a test pattern is driven on the VGA port. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 11 of 12 Basys2™ FPGA Board Reference Manual If the self test is not resident in the Platform Flash ROM, it can be programmed into the FPGA or reloaded into the ROM using the Adept programming software. Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 12 of 12