OP063

Datasheet: OP063 opsero.com FPGA Drive FMC Gen4 Overview Description FPGA Drive FMC Gen4 is an adapter that allows M.2 NVMe PCIe SSDs to be connected to FPGA and MPSoC based development boards. The adapter uses the FPGA Mezzanine Card (FMC) form factor for connection with FPGA and MPSoC development boards via the FMC connector. It has 2x M-key M.2 sockets and can carry M.2 PCIe SSDs of length 42mm, 60mm, 80mm or 110mm. Each M.2 socket has its own independent connection to the FPGA for maximum throughput and can support a 4-lane PCIe connection up to Gen4. Top view FPGA Drive FMC Gen4 top Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com Bottom view FPGA Drive FMC Gen4 bottom Features • • • • • • 2x M-key M.2 connectors for PCIe NVMe SSDs Support and example designs for multiple development boards Supports up to PCIe Gen4 speeds FMC pinout conforms to VITA 57.1 FMC Standard Standalone example designs PetaLinux example designs Supported development boards For a list of all the FPGA and MPSoC development boards that are compatible with the FPGA Drive FMC Gen4, please refer to the list of compatible boards. For a list of boards for which we currently have a reference design, please refer to the list of supported boards in the reference design documentation. Supported SSDs The FPGA Drive FMC Gen4 has been designed to support all standard M-key M.2 NVMe SSDs for PCIe Gen1 to Gen4. However, certain software incompatibility issues can arise when using some SSDs and can depend on the version of PetaLinux used, the version of NVMe built into the SSD, the transceiver settings in the Vivado design, Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com and other factors. To help guide your selection of SSD, the documentation for the reference designs contains a list of SSDs that have been tested with the FPGA Drive FMC Gen4. Ordering The FPGA Drive FMC Gen4 can be ordered from the vendors listed below. The links under the part number column will take you to the corresponding order page. Vendor Part name Part number Opsero FPGA Drive FMC Gen4 OP063 Digi-Key FPGA Drive FMC Gen4 OP063 Included with the FPGA Drive FMC Gen4 are: • 2x machine screws for fixing the SSDs to the mezzanine card * 2x M.2 loopback modules (PN: OP057) Note that the FPGA Drive FMC Gen4 does NOT come with SSDs. Pin Configuration Pinout table The FPGA Drive FMC Gen4 has a high pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and describes each pin’s purpose on this mezzanine card. To avoid confusion, we have chosen not to label the PCIe lanes as being TX or RX; instead we have labelled them with the direction in which the signal flows (eg. FPGA-toSSD1 means that the FPGA transmits this signal and the SSD1 receives). Pin Pin name Net Description A1 GND GND Ground A2 DP1_M2C_P SSDA2FPGA_1_P PCIe lane 1 positive (SSD1-toFPGA) A3 DP1_M2C_N SSDA2FPGA_1_N PCIe lane 1 negative (SSD1-toFPGA) Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com A4 GND GND Ground A5 GND GND Ground A6 DP2_M2C_P SSDA2FPGA_2_P PCIe lane 2 positive (SSD1-toFPGA) A7 DP2_M2C_N SSDA2FPGA_2_N PCIe lane 2 negative (SSD1-toFPGA) A8 GND GND Ground A9 GND GND Ground A10 DP3_M2C_P SSDA2FPGA_3_P PCIe lane 3 positive (SSD1-toFPGA) A11 DP3_M2C_N SSDA2FPGA_3_N PCIe lane 3 negative (SSD1-toFPGA) A12 GND GND Ground A13 GND GND Ground A14 DP4_M2C_P SSDB2FPGA_0_P PCIe lane 0 positive (SSD2-toFPGA) A15 DP4_M2C_N SSDB2FPGA_0_N PCIe lane 0 negative (SSD2-toFPGA) A16 GND GND Ground A17 GND GND Ground A18 DP5_M2C_P SSDB2FPGA_1_P PCIe lane 1 positive (SSD2-toFPGA) A19 DP5_M2C_N SSDB2FPGA_1_N PCIe lane 1 negative (SSD2-toFPGA) A20 GND GND Ground A21 GND GND Ground A22 DP1_C2M_P FPGA2SSDA_1_P PCIe lane 1 positive (FPGA-toSSD1) Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com A23 DP1_C2M_N FPGA2SSDA_1_N PCIe lane 1 negative (FPGA-toSSD1) A24 GND GND Ground A25 GND GND Ground A26 DP2_C2M_P FPGA2SSDA_2_P PCIe lane 2 positive (FPGA-toSSD1) A27 DP2_C2M_N FPGA2SSDA_2_N PCIe lane 2 negative (FPGA-toSSD1) A28 GND GND Ground A29 GND GND Ground A30 DP3_C2M_P FPGA2SSDA_3_P PCIe lane 3 positive (FPGA-toSSD1) A31 DP3_C2M_N FPGA2SSDA_3_N PCIe lane 3 negative (FPGA-toSSD1) A32 GND GND Ground A33 GND GND Ground A34 DP4_C2M_P FPGA2SSDB_0_P PCIe lane 0 positive (FPGA-toSSD2) A35 DP4_C2M_N FPGA2SSDB_0_N PCIe lane 0 negative (FPGA-toSSD2) A36 GND GND Ground A37 GND GND Ground A38 DP5_C2M_P FPGA2SSDB_1_P PCIe lane 1 positive (FPGA-toSSD2) A39 DP5_C2M_N FPGA2SSDB_1_N PCIe lane 1 negative (FPGA-toSSD2) A40 GND GND Ground B1 CLK_DIR N/C Not connected Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com B2 GND GND Ground B3 GND GND Ground B4 DP9_M2C_P N/C Not connected B5 DP9_M2C_N N/C Not connected B6 GND GND Ground B7 GND GND Ground B8 DP8_M2C_P N/C Not connected B9 DP8_M2C_N N/C Not connected B10 GND GND Ground B11 GND GND Ground B12 DP7_M2C_P SSDB2FPGA_3_P PCIe lane 3 positive (SSD2-toFPGA) B13 DP7_M2C_N SSDB2FPGA_3_N PCIe lane 3 negative (SSD2-toFPGA) B14 GND GND Ground B15 GND GND Ground B16 DP6_M2C_P SSDB2FPGA_2_P PCIe lane 2 positive (SSD2-toFPGA) B17 DP6_M2C_N SSDB2FPGA_2_N PCIe lane 2 negative (SSD2-toFPGA) B18 GND GND Ground B19 GND GND Ground B20 GBTCLK1_M2C_P REFCLKB_FPGA_P 100MHz PCIe reference clock for the FPGA B21 GBTCLK1_M2C_N REFCLKB_FPGA_N 100MHz PCIe reference clock for the FPGA B22 GND Ground GND Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com B23 GND GND Ground B24 DP9_C2M_P N/C Not connected B25 DP9_C2M_N N/C Not connected B26 GND GND Ground B27 GND GND Ground B28 DP8_C2M_P N/C Not connected B29 DP8_C2M_N N/C Not connected B30 GND GND Ground B31 GND GND Ground B32 DP7_C2M_P FPGA2SSDB_3_P PCIe lane 3 positive (FPGA-toSSD2) B33 DP7_C2M_N FPGA2SSDB_3_N PCIe lane 3 negative (FPGA-toSSD2) B34 GND GND Ground B35 GND GND Ground B36 DP6_C2M_P FPGA2SSDB_2_P PCIe lane 2 positive (FPGA-toSSD2) B37 DP6_C2M_N FPGA2SSDB_2_N PCIe lane 2 negative (FPGA-toSSD2) B38 GND GND Ground B39 GND GND Ground B40 RES0 N/C Not connected C1 GND GND Ground C2 DP0_C2M_P FPGA2SSDA_0_P PCIe lane 0 positive (FPGA-toSSD1) C3 DP0_C2M_N FPGA2SSDA_0_N PCIe lane 0 negative (FPGA-toSSD1) Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com C4 GND GND Ground C5 GND GND Ground C6 DP0_M2C_P SSDA2FPGA_0_P PCIe lane 0 positive (SSD1-toFPGA) C7 DP0_M2C_N SSDA2FPGA_0_N PCIe lane 0 negative (SSD1-toFPGA) C8 GND GND Ground C9 GND GND Ground C10 LA06_P N/C Not connected C11 LA06_N N/C Not connected C12 GND GND Ground C13 GND GND Ground C14 LA10_P N/C Not connected C15 LA10_N N/C Not connected C16 GND GND Ground C17 GND GND Ground C18 LA14_P N/C Not connected C19 LA14_N N/C Not connected C20 GND GND Ground C21 GND GND Ground C22 LA18_P_CC N/C Not connected C23 LA18_N_CC N/C Not connected C24 GND GND Ground C25 GND GND Ground C26 LA27_P N/C Not connected Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com C27 LA27_N N/C Not connected C28 GND GND Ground C29 GND GND Ground C30 SCL I2C_SCL I2C Clock (FPGA-to-PHY) C31 SDA I2C_SDA I2C Data (bidirectional) C32 GND GND Ground C33 GND GND Ground C34 GA0 GA0 EEPROM Address Bit 1 (A1) C35 12P0V_1 12V0 12VDC (Not used) C36 GND GND Ground C37 12P0V_2 12V0 12VDC (Not used) C38 GND GND Ground C39 3P3V_1 3V3 3.3VDC C40 GND GND Ground D1 PG_C2M PG Power Good (Driven by carrier) D2 GND GND Ground D3 GND GND Ground D4 GBTCLK0_M2C_P REFCLKA_FPGA_P 100MHz PCIe reference clock for the FPGA D5 GBTCLK0_M2C_N REFCLKA_FPGA_P 100MHz PCIe reference clock for the FPGA D6 GND GND Ground D7 GND GND Ground D8 LA01_P_CC N/C Not connected D9 LA01_N_CC N/C Not connected Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com D10 GND GND Ground D11 LA05_P N/C Not connected D12 LA05_N N/C Not connected D13 GND GND Ground D14 LA09_P N/C Not connected D15 LA09_N N/C Not connected D16 GND GND Ground D17 LA13_P N/C Not connected D18 LA13_N N/C Not connected D19 GND GND Ground D20 LA17_P_CC RSVD Reserved for production testing D21 LA17_N_CC RSVD Reserved for production testing D22 GND GND Ground D23 LA23_P N/C Not connected D24 LA23_N N/C Not connected D25 GND GND Ground D26 LA26_P N/C Not connected D27 LA26_N N/C Not connected D28 GND GND Ground D29 TCK N/C Not used D30 TDI TDI-TDO JTAG TDI (Connects to TDO to close JTAG chain) D31 TDO TDI-TDO JTAG TDO (Connects to TDI to close JTAG chain) D32 3P3VAUX 3V3AUX 3.3VDC Power supply for EEPROM Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com D33 TMS N/C Not used D34 TRST_L N/C Not used D35 GA1 GA1 EEPROM Address Bit 0 (A0) D36 3P3V_2 3V3 3.3VDC D37 GND GND Ground D38 3P3V_3 3V3 3.3VDC D39 GND GND Ground D40 3P3V_4 3V3 3.3VDC G1 GND GND Ground G2 CLK1_M2C_P N/C Not used G3 CLK1_M2C_N N/C Not used G4 GND GND Ground G5 GND GND Ground G6 LA00_P_CC PERST_A PCIe reset for SSD1 (active high) G7 LA00_N_CC PEDET_A PCIe detect for SSD1 G8 GND GND Ground G9 LA03_P N/C Not connected G10 LA03_N N/C Not connected G11 GND GND Ground G12 LA08_P N/C Not connected G13 LA08_N N/C Not connected G14 GND GND Ground G15 LA12_P N/C Not connected G16 LA12_N N/C Not connected Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com G17 GND GND Ground G18 LA16_P N/C Not connected G19 LA16_N N/C Not connected G20 GND GND Ground G21 LA20_P N/C Not connected G22 LA20_N N/C Not connected G23 GND GND Ground G24 LA22_P N/C Not connected G25 LA22_N N/C Not connected G26 GND GND Ground G27 LA25_P N/C Not connected G28 LA25_N N/C Not connected G29 GND GND Ground G30 LA29_P N/C Not connected G31 LA29_N N/C Not connected G32 GND GND Ground G33 LA31_P N/C Not connected G34 LA31_N N/C Not connected G35 GND GND Ground G36 LA33_P N/C Not connected G37 LA33_N N/C Not connected G38 GND GND Ground G39 VADJ_3 VADJ I/O Supply Voltage (1.2VDC) G40 GND GND Ground Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com H1 VREF_A_M2C N/C Not used H2 PRSNT_M2C_L GND Ground H3 GND GND Ground H4 CLK0_M2C_P N/C Not used H5 CLK0_M2C_N N/C Not used H6 GND GND Ground H7 LA02_P N/C Not connected H8 LA02_N N/C Not connected H9 GND GND Ground H10 LA04_P PERST_B PCIe reset for SSD2 (active high) H11 LA04_N PEDET_B PCIe detect for SSD2 H12 GND GND Ground H13 LA07_P DISABLE_SSD2_PWR Disable switching regulator for SSD2 (0=Enable,1=Disable) H14 LA07_N N/C Not used H15 GND GND Ground H16 LA11_P N/C Not connected H17 LA11_N N/C Not connected H18 GND GND Ground H19 LA15_P N/C Not connected H20 LA15_N N/C Not connected H21 GND GND Ground H22 LA19_P N/C Not connected H23 LA19_N N/C Not connected Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com H24 GND GND Ground H25 LA21_P N/C Not connected H26 LA21_N N/C Not connected H27 GND GND Ground H28 LA24_P N/C Not connected H29 LA24_N N/C Not connected H30 GND GND Ground H31 LA28_P N/C Not connected H32 LA28_N N/C Not connected H33 GND GND Ground H34 LA30_P N/C Not connected H35 LA30_N N/C Not connected H36 GND GND Ground H37 LA32_P N/C Not connected H38 LA32_N N/C Not connected H39 GND GND Ground H40 VADJ_4 VADJ I/O Supply Voltage (1.2VDC) Rows E,F,J and K of the HPC connector were left out of the above table. On the mezzanine card, these rows are left unconnected, with the exception of the ground and VADJ pins which are connected appropriately. Specifications Recommended Operating Conditions SUPPLY VOLTAGE MIN TYP MAX UNIT 12 VDC +11.4 +12 +12.6 V Copyright 2023, Opsero Electronic Design Inc. Datasheet: OP063 opsero.com 3.3 VDC +3.14 +3.3 +3.46 V VADJ 1.8VDC +1.71 +1.8 +1.89 V Power Consumption The specifications below refer to the total current draw on each of the power supplies while the FPGA Drive FMC Gen4 is connected to a development board and has 2x SSDs connected. SUPPLY UTILIZATION 12 VDC Dual write 281 mA 12 VDC Dual read 199 mA 3.3 VDC Dual write 969 mA 3.3 VDC Dual read 688 mA VADJ 1.8 VDC Dual write