ASM1182E

n e d i ASM1182e Data Sheet f n PCI Express Packet Switch o C a i d e M S A l a i t Copyright Notice: Copyright © 2008, ASMedia TECHNOLOGY INC. All Rights Reserved. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS OF ASMEDIA TECHNOLOGY INC. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN ASMEDIA’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, ASMEDIA ASSUMES NO LIABILITY WHATSOEVER, AND ASMEDIA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ASMEDIA PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Products of ASMEDIA TECHNOLOGY INC. are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. 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ASMedia and ASMedia logo are trademarks or registered trademarks of ASMedia TECHNOLOGY INC. in Taiwan and other countries. l a i t © 2008 祥碩科技股份有限公司，著作權所有，並保留一切權利 本文資料為與祥碩科技股份有限公司之產品相關。本文並未明示或默示授權任何智慧財產權予第三人。除在祥碩科技股份有限公司對該產品提供 的買賣條款及條件以外，祥碩科技股份有限公司免於擔負任何責任，且不對產品的買賣及使用做任何明示或默示的保證，包含產品適於特殊使用 目的、以及產品不侵害任何專利權、著作權或其他智慧財產權。祥碩科技股份有限公司之產品不用於醫療的、救助生命的、生命維持的、安全控 管系統或核子設施等用途之上。 祥碩科技股份有限公司可隨時不經通知，逕行增訂或修改產品規格及描述。 本文之相關專利權、申請中之專利權、商標權、著作權及其餘智慧財產權均屬祥碩科技股份有限公司所有。本文及其他資訊並未明示或默示的提 供任何專利、商標、著作權及其餘智慧財產權之授權。 請於下產品訂單前先聯絡當地的祥碩科技銷售處或代理商以取得最新的產品規格書。 本文提及之有訂單號碼之文件或其他詳細資料可參閱祥碩科技網站 www.asmedia.com.tw 或撥打+886-2-22196088 ASMEDIA 和 ASMEDIA 商標均為祥碩科技股份有限公司在台灣和其他國家的註冊商標或商標。 n e d i f n o C Office: ASMedia Technology, Inc. 6F, No.115, Minquan Rd., Xindian City, Taipei County 231, Taiwan, R.O.C. http://www.asmedia.com.tw Tel: 886-2-2219-6088 Fax: 886-2-2219-6080 M S A a i d e Environmentally hazardous materials are not used in this product. ASM1182e Data Sheet Preliminary subject to change without notice Revision History Rev. Date Description 0.1 Dec. 14, 2012 Initial Release 0.2 May. 8, 2013 Modify core power range 1.0 Oct. 9, 2013 Change version to 1.0 1.1 Dec. 4, 2013 Add Power on/off sequence 1.2 Sep 18, 2014 Add Chip temperature calculation, remove power off sequence 1.3 May 14, 2015 Add Top marking 1.4 Nov 6, 2015 M S A l a i t Add PCIe differential clock range a i d e n e d i f n o C iii ASM1182e Data Sheet Preliminary subject to change without notice Table of Contents 1. General Description ............................................................................................................. 1 2. Features ................................................................................................................................ 1 3. Package Type ....................................................................................................................... 1 4. Functional Diagram .............................................................................................................. 2 5. Pinout Diagram ..................................................................................................................... 3 6. Pin Description ..................................................................................................................... 4 7. Function Description ........................................................................................................... 6 8. Eletrical Characteristic ........................................................................................................ 7 9. Power Consumption .......................................................................................................... 10 10. Package Information ........................................................................................................ 11 l a i t M S A a i d e n e d i f n o C iv ASM1182e Data Sheet Preliminary subject to change without notice List of Figures Figure1. Function Diagram ...................................................................................................... 2 Figure2. ASM1182e Pinout....................................................................................................... 3 Figure3. Mechanical Specification – QFN48 ........................................................................ 11 l a i t M S A a i d e n e d i f n o C v ASM1182e Data Sheet Preliminary subject to change without notice This page is intentionally left blank. l a i t M S A a i d e n e d i f n o C vi ASM1182e Data Sheet Preliminary subject to change without notice 1. General Description ASM1182e, PCI express packet switch, 1 PCIe x1 Gen2 upstream port to 2 PCIe x 1 Gen2 downstream ports, enable users to extend PCIe ports on mother board or embedded system. PCIe interface of ASM1182e is PCIe Base SPEC 2.0 compliance. 2. Features l a i t General Features  Standard Compliant > PCI express base SPEC 2.0 and backward compatible with SEPC 1.1 & 1.0a > PCI Power management SPEC 1.2  Port configuration > 1 PCIe x1 lane Gen2 upstream port to 2 PCIe x1 lane Gen2 downstream ports  PCIe power management > Link state L0, L0s, L1, L2/L3 Ready and L3 > device state D0, D3 hot  Short latency delay  Integrate 100MHz PCIe differential clock buffer,no extra clock buffer needed.  Support I2C interface for debug usage  7 x 7 QFN48 RoHS package 3. Package Type M S A  7x7 QFN48 a i d e n e d i f n o C 1 ASM1182e Data Sheet Preliminary subject to change without notice 4. Functional Diagram PCIe differential clock (100MHz) PCIe Host PCIe controller Central Traffic Control & Arbitor PCIe controller M S A PCIe device l a i t n e d i f n o C Clock Buffer a i d e PCIe controller PCIe device 2 PCIe differential clock (100MHz) Figure 1: Functional Diagram 2 ASM1182e Data Sheet Preliminary subject to change without notice GPIO3 VDDA33 TXP_7 RXP_7 RXN_7 VDD12 PECLKP_7 TXN_7 28 27 26 25 VCC33 GPIO1 VCC12 PECLKN_5 PECLKP_5 VDD12 18 RXN_5 17 16 15 RXP_5 TXN_5 14 VDDA33 13 VCC12 12 TXP_5 REXT1 VDD12 2 3 VDDA33 M S A 48 PE_RST_OUT# GPIO7 47 1 GPIO6 VSUS33 GPIO5 TEST_EN VDD12 44 45 46 GPIO4 VDDA33 7 8 9 10 11 TXN_0 MSDA TXP_0 MSCL GNDA GPIO2 RXN_0 n e d i f n ASM1182e o C a i d e 4 5 6 RXP_0 l a i t 24 23 22 21 20 19 GPIO0 VDD12 37 38 39 40 41 42 43 PE_RST# REXT2 32 31 30 29 PECLKN_7 PECLKP_0 PECLKN_0 36 35 34 33 VCC12 5. Pinout Diagrams Figure 2: ASM1182e Pinout 3 ASM1182e Data Sheet Preliminary subject to change without notice 6. Pin Descriptions This section provides a detailed description of each signal. The following notations are used to describe the signal type. I/O Type I O I/O P G OD Definition Input pin Output pin Bi-directional pin Power pin Ground pin Open Drain Pin Number N REXT1 12 TXP_0 TXN_0 RXP_0 RXN_0 PECLKP_0 PECLKN_0 42 43 39 40 34 35 REXT2 37 TXP_5 TXN_5 RXP_5 RXN_5 TXP_7 TXN_7 RXP_7 RXN_7 PECLKP_5 PECLKN_5 PECLKP_7 PECLKN_7 15 16 17 18 27 28 29 30 20 21 32 33 PE_RST# PE_RST_OUT# MSCL MSDA TEST_EN GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 3 2 6 7 9 4 23 5 25 8 46 M S A I/O I l a i t n e d i f n o C Descriptions Upstream Signals External Resistor for PCIE PHY. External resistor should be connected this pin to ground. O O I I I I PCIE PCIE PCIE PCIE PCIE PCIE Upstream TX+ signal Upstream TX- signal Upstream RX+ signal Upstream RX- signal 100MHz Clock input+ 100MHz Clock input- O Downstream Signals External Resistor for PCIE PHY. External resistor should be connected this pin to ground. O O I I O O I I O O O O PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE a i d e I O I/O I/O I I/O I/O I/O I/O I/O I/O downstream lane5 TX+ signal (logic device 7) downstream lane5 TX- signal (logic device 7) downstream lane5 RX+ signal (logic device 7) downstream lane5 RX- signal (logic device 7) downstream lane7 TX+ signal (logic device 3) downstream lane7 TX- signal (logic device 3) downstream lane7 RX+ signal (logic device 3) downstream lane7 RX- signal (logic device 3) 100MHz Clock output+ 100MHz Clock output100MHz Clock output+ 100MHz Clock output- MISC Signals Chip global reset PCIE Reset for downstream port SMBus/I2C clock signal SMBus/I2C data signal Test mode enable, connect to GND General purpose input/output 0 General purpose input/output 1 General purpose input/output 2 General purpose input/output 3 General purpose input/output 4 General purpose input/output 5 4 ASM1182e Data Sheet Preliminary subject to change without notice N GPIO6 GPIO7 VSUS33 VDDA33 VDD12 VCC33 VCC12 GNDA Pin Number 47 48 1 10,14,26,44 11,19,31,38 ,45 24 13,22,36 41 M S A I/O I/O I/O P P P P P G Descriptions General purpose input/output 6 General purpose input/output 7 Power 3.3V suspend power 3.3V Power Input, for PCIE PHY 1.2V Power Input, for PCIE PHY l a i t 3.3V Power Input, for PAD 1.2V Power Input for Core Ground a i d e n e d i f n o C 5 ASM1182e Data Sheet Preliminary subject to change without notice 7. Function Description 7.1. Strapping Table Pins Function Default (internal pull) GPIO0 Clock buffer mode setting. 0: PLL mode; 1: bypass mode Pull up GPIO1 Clock buffer termination enable. 0: disable; 1: enable Pull up GPIO2 Reserved for test mode. Pull up GPIO3 Reserved for ASM1187e Pull up GPIO4 SMBus enable. Please refer to below SMBus/I2C table Pull up GPIO5 SMBus address[0]. Pull up GPIO6 SMBus address[1]. Pull up GPIO7 SMBus address[2]. Pull up MSCL I2C enable. Please refer to below SMBus/I2C table. Pull up SMBus/I2C table GPIO4 (SMBus enable) MSCL (I2C enable) Function 0 0 (MSCL, MSDA) is no function 0 1 (MSCL, MSDA) is I2C, connected to a EEPROM, chip is master 1 0 (MSCL, MSDA) is SMBus, chip is salve 1 1 (MSCL, MSDA) is SMBus, chip is salve l a i t M S A a i d e n e d i f n o C 6 ASM1182e Data Sheet Preliminary subject to change without notice 8 Electrical Characteristics 8.1 Absolute Maximum Ratings Parameter Power Supply for 1.2V Range -0.5~+1.6 Power Supply for 3.3V -0.5~+4.5 DC Input Voltage -0.5~+4.5 Output Voltage -0.5~+4.5 Storage Temperature l a i t V V V 0 -65~150 HBM ESD C +/-2 MM ESD n e d i f n o C +/-200 8.2 Recommand Operation Condition Symbols Parameter VCC33 VDDA33 3.3V IO Power Supply VCC12 1.2V Core Power Supply VDD12 PCIE 1.2V Power Supply VSUS33 TC 3.3V Suspend IO Power Supply TJ Units V PCIE 3.3V Analog Power Supply Operating Case Temperature a i d e Operating Junction Temperature KV V Min. Typ. Max. Units 3.0 3.3 3.6 V 3.0 3.3 3.6 V 1.0 1.15 1.3 V 1.0 1.15 1.3 V 3.0 3.3 3.7 0 25 95 25 120 0 8.3 DC Electrical Characteristics for GPIO/RST Pins (Temperature = 450C) Symbols VIH VIL VHYS VTH-L2H VTH-H2L RUP IIL VOH VOL IOH IOL Parameter Input High Level Input Low Level Input Hysteresis VTH of Schmitt Trigger low to high VTH of Schmitt Trigger high to low Internal Pull-up resistance while Vin=0V Internal Pull-up resistance while Vin=VCCH/2 V Input pull-up leakage current while Vin=0V Input pull-up leakage current while Vin=VCCH/2 V Output High Voltage Output Low Voltage Driving Current of Output High Driving Current of Output Low M S A 8.4 Reference Resistor Requirement Parameter REXT* External Reference Resistor V C 0 C 0.8 0.65 1.8 1.15 Units V V V V V 98.3 140 KΩ 37.85 55 77 KΩ 21.4 33.6 53.7 uA 19.5 30 47.6 uA Min. 2 Typ. 0.57 1.38 0.82 0.6 67 Max. 2.64 0.66 8 8 Value Units 12.1K+/-1% Ohm V V mA mA 7 ASM1182e Data Sheet Preliminary subject to change without notice 8.5 PCI Express Differential Reference Clock Input Ranges Symbols FIN-DIFF VIH VIL VCROSS VCROSS-DELTA VRB TSTABLE TPERIOD-AVG TPERIOD-ABS TCC-JITTER VMAX VMIN R/F Matching ZC-DC Parameter The input frequency is 100 MHz + 300 ppm and max. − 5000 including SSC-dictated variations Differential input frequency Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Absolute crossing point voltage Variation of VCROSS over all rising clock edges Ring-back Voltage Margin Time before VRB is allowed Average Clock Period Accuracy Absolute Period (including Jitter and Spread Spectrum) Cycle to Cycle Jitter Absolute Max input voltage Absolute Min input voltage Duty Cycle Rising edge rate (REFCLK+) to Falling edge rate (REFCLK-) matching Clock source DC impedance M S A a i d e Min Typ Max 100 0.6 0.6 150 250 Unit Remark MHz 4.0 4.0 -150 550 140 100 V/ns V/ns mV mV mV mV -100 500 -300 2800 mV ps ppm 9.847 10.203 ns 40 150 1.15 -0.3 60 ps V V % 20 % 60 Ω l a i t n e d i f n o C 40 8 ASM1182e Data Sheet Preliminary subject to change without notice 8.6 Power On/Off Sequence > 20ms 90% 90% IO Power3.3V > 20ms > 0us > 1us 90% Core Power1.2V l a i t > 100us PE_RST# PECLK* < 6ms < 6ms Symbols t1 t2 Parameter Min Power ramp up to 100% Power on 90% ready to PE_RST# deassertion PCI Express Reference stable Clock before PE_RST# deassertion t3 a i d e 8.7 Chip Temperature(Tj, Tc) Calculation Symbol Parameter Max Unit 6 20 ms ms 100 us Remark How to get? Ta Ambient temperature Measure temperature around chip Tj Operating junction temperature Tj = Θja * power + Ta Tc Operating case temperature Tc = Tj - Ψjt * power Junction to Ambient thermal resistance Provided by package vendor, for QFN48, it’s 30.6 Junction to top thermal characterization Provided by package vendor, for QFN48, it’s 0.1 Θja Ψjt    n e d i f n o C M S A Chip power consumption Measure chip power consumption Power Thermal test board condition, please refer to JEDEC JESD51-5 Thermal Test Method Environmental Conditions refer JESD51-2 Example: If chip power consumption is 0.8W; Ta=400C Tj = 30.6 * 0.8 + 40 = 64.480C Tc = 64.48 – 0.1 * 0.8 = 64.40C 9 ASM1182e Data Sheet Preliminary subject to change without notice 9 Power Consumption Test Item I33 Total Consumption Current for 3.3V Power I12 Total Consumption Current for 1.05V Power Total Power Consumption M S A Test State L0 Idle Suspend L0 Idle Suspend L0 Idle Suspend a i d e Min. Typ. Max. 92 92 0.05 470 450 0 800 775 0.16 94 94 0.05 480 460 0 808 786 0.16 mA mA mA mA mA mA mW mW mW n e d i f n o C l a i t 10 ASM1182e Data Sheet Preliminary subject to change without notice 10 Package Information l a i t M S A a i d e Figure 3: n e d i f n o C Mechanical Specification – QFN 48L 11 ASM1182e Data Sheet Preliminary subject to change without notice 11 Top marking Information l a i t 1 2 n e d i f n o C ASM1182e 4 3 B XXXXXXXXX 5 YYWW Figure 4: Top marking of ASM1182e a i d e 1. asmedia: ASMedia Logo 2. ASM1182e: Product Name M S A 3. B: Version of ASMedia Logo 4. XXXXXXXXX: Serial No. Reserved for Vendor 5. YYWW: Date Code 12