Precision, 500 ns Settling
BiFET Op Amp
AD744
Data Sheet
FEATURES
AC PERFORMANCE
500 ns Settling to 0.01% for 10 V Step
1.5 s Settling to 0.0025% for 10 V Step
75 V/s Slew Rate
0.0003% Total Harmonic Distortion (THD)
13 MHz Gain Bandwidth – Internal Compensation
>200 MHz Gain Bandwidth (G = 1000)
External Decompensation
>1000 pF Capacitive Load Drive Capability with
10 V/s Slew Rate – External Compensation
DC PERFORMANCE
0.5 mV max Offset Voltage (AD744B)
10 V/ⴗC max Drift (AD744B)
250 V/mV min Open-Loop Gain (AD744B)
Available in Plastic Mini-DIP, Plastic SOIC, Hermetic
Cerdip, Hermetic Metal Can Packages and Chip Form
Surface Mount (SOIC) Package Available in Tape and
Reel in Accordance with EIA-481A Standard
CONNECTION DIAGRAMS
TO-99 (H) Package
8-Lead Plastic Mini-DIP (N)
8-Lead SOIC (R) Package and
8-Lead Cerdip (Q) Packages
APPLICATIONS
Output Buffers for 12-Bit, 14-Bit and 16-Bit DACs,
ADC Buffers, Cable Drivers, Wideband
Preamplifiers and Active Filters
PRODUCT DESCRIPTION
The AD744 is a fast-settling, precision, FET input, monolithic
operational amplifier. It offers the excellent dc characteristics
of the AD711 BiFET family with enhanced settling, slew rate,
and bandwidth. The AD744 also offers the option of using
custom compensation to achieve exceptional capacitive load
drive capability.
The single-pole response of the AD744 provides fast settling:
500 ns to 0.01%. This feature, combined with its high dc precision, makes it suitable for use as a buffer amplifier for 12-bit,
14-bit or 16-bit DACs and ADCs. Furthermore, the AD744’s low
total harmonic distortion (THD) level of 0.0003% and gain bandwidth product of 13 MHz make it an ideal amplifier for demanding
audio applications. It is also an excellent choice for use in active
filters in 12-bit, 14-bit and 16-bit data acquisition systems.
The AD744 is internally compensated for stable operation as a
unity gain inverter or as a noninverting amplifier with a gain of
two or greater. External compensation may be applied to the
AD744 for stable operation as a unity gain follower. External
compensation also allows the AD744 to drive 1000 pF capacitive
loads, slewing at 10 V/µs with full stability.
Alternatively, external decompensation may be used to increase
the gain bandwidth of the AD744 to over 200 MHz at high
Rev. D
gains. This makes the AD744 ideal for use as ac preamps in
digital signal processing (DSP) front ends.
The AD744 is available in five performance grades. The AD744J
and AD744K are rated over the commercial temperature range
of 0°C to +70°C. The AD744A and AD744B are rated over
the industrial temperature range of –40°C to +85°C. The AD744T
is rated over the military temperature range of –55°C to +125°C
and is available processed to MIL-STD-883B, Rev. C.
The AD744 is available in an 8-lead plastic mini-DIP, 8-lead
small outline, 8-lead cerdip or TO-99 metal can.
PRODUCT HIGHLIGHTS
1. The AD744 is a high-speed BiFET op amp that offers excellent performance at competitive prices. It outperforms the
OPA602/OPA606, LF356 and LF400.
2. The AD744 offers exceptional dynamic response. It settles to
0.01% in 500 ns and has a 100% tested minimum slew rate
of 50 V/µs (AD744B).
3. The combination of Analog Devices’ advanced processing
technology, laser wafer drift trimming and well-matched
ionimplanted JFETs provide outstanding dc precision. Input
offset voltage, input bias current, and input offset current are
specified in the warmed-up condition; all are 100% tested.
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Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD744–SPECIFICATIONS
(@ +25ⴗC and ⴞ15 V dc, unless otherwise noted)
AD744J/A/S
Model
INPUT OFFSET VOLTAGE 1
Initial Offset
Offset
vs. Temp.
vs. Supply2
vs. Supply
Long-Term Stability
INPUT BIAS CURRENT 3
Either Input
Either Input @ T MAX =
J, K
A, B, C
S, T
Either Input
Offset Current
Offset Current @ T MAX =
J, K
A, B, C
S, T
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time to 0.01% 4
Total Harmonic
Distortion
Conditions
Min
0.3
TMIN to TMAX
TMIN to TMAX
82
82
5
95
AD744K/B/T
Max
Min
1.0
2
20
VCM = 0 V
VCM = 0 V
70°C
85°C
125°C
VCM = +10 V
VCM = 0 V
VCM = 0 V
70°C
85°C
125°C
G = –1
VO = 20 V p-p
G = –1
G = –1
f = 1 kHz
R1 ≥ 2 kΩ
VO = 3 V rms
8
45
88
88
78
76
72
70
5
100
Max
Unit
0.5
1.0
10
mV
mV
µV/°C
dB
dB
µV/month
15
30
100
30
100
pA
0.7
1.9
31
40
20
2.3
6.4
102
150
50
0.7
1.9
31
40
10
2.3
6.4
102
150
50
nA
nA
nA
pA
pA
0.4
1.3
20
1.1
3.2
52
0.2
0.6
10
1.1
3.2
52
nA
nA
nA
0.75
MHz
MHz
V/µs
µs
13
1.2
75
0.5
9
50
0.75
13
1.2
75
0.5
0.0003
0.0003
%
3 ⫻ 1012||5.5
3 ⫻ 1012||5.5
3 ⫻ 1012||5.5
3 ⫻ 1012||5.5
Ω||pF
Ω||pF
± 20
+14.5, –11.5
–11
± 20
+14.5, –11.5
+13
V
V
V
82
80
78
74
88
84
84
80
dB
dB
dB
dB
–11
VCM = ± 10 V
TMIN to TMAX
VCM = ± 11 V
TMIN to TMAX
Typ
0.25
15
INPUT IMPEDANCE
Differential
Common Mode
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range 6
Common-Mode
Rejection Ratio
Typ
+13
88
84
84
80
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
2
45
22
18
16
2
45
22
18
16
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
INPUT CURRENT NOISE
f = 1 kHz
0.01
0.01
pA/√Hz
OPEN LOOP GAIN 7
VO = ± 10 V
RLOAD ≥ 2 kΩ
TMIN to TMAX
INPUT VOLTAGE NOISE
OUTPUT CHARACTERISTICS
Voltage
Current
Capacitive Load8
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
RLOAD ≥ 2 kΩ
TMIN to TMAX
Short Circuit
Gain = –1
200
100
400
250
100
400
V/mV
V/mV
+13, –12.5
± 12
+13.9, –13.3
+13.8, –13.1
25
+13, –12.5
± 12
+13.9, –13.3
+13.8, –13.1
25
1000
V
V
mA
pF
± 15
V
V
mA
1000
± 4.5
± 15
3.5
± 18
5.0
± 4.5
3.5
± 18
4.0
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2
PSRR test conditions: +VS = 15 V, –VS = –12 V to –18 V and +VS = +12 V to +18 V, –VS = –15 V.
3
Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
4
Gain = –1, RL = 2 k, CL = 10 pF, refer to Figure 25.
5
Defined as voltage between inputs, such that neither exceeds ± 10 V from ground.
6
Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.
7
Open-Loop Gain is specified with VOS both nulled and unnulled.
8
Capacitive load drive specified for CCOMP = 20 pF with the device connected as shown in Figure 32. Under these conditions, slew rate = 14 V/µs and 0.01% settling time = 1.5 µs typical.
Refer to Table II for optimum compensation while driving a capacitive load.
Specifications subject to change without notice. All min and max specifications are guaranteed.
–2–
REV. D
AD744
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW
Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (Q, H) . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range
AD744J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD744A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD744S/T . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 seconds) . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Thermal Characteristics
8-Lead Plastic Package:
θJA = 100°C/Watt, θJC = 33°C/Watt
8-Lead Cerdip Package:
θJA = 110°C/Watt, θJC = 22°C/Watt
8-Lead Metal Can Package: θJA = 150°C/Watt, θJC = 65°C/Watt
8-Lead SOIC Package:
θJA = 160°C/Watt, θJC = 42°C/Watt
3
For supply voltages less than ± 18 V, the absolute maximum input voltage is equal
to the supply voltage.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
REV. D
–3–
AD744 –Typical Characteristics
Figure 1. Input Voltage Swing
vs. Supply Voltage
Figure 2. Output Voltage Swing
vs. Supply Voltage
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 5. Input Bias Current vs.
Temperature
Figure 7. Input Bias Current vs.
Common-Mode Voltage
Figure 8. Short Circuit Current
Limit vs. Temperature
–4–
Figure 3. Output Voltage Swing vs.
Load Resistance
Figure 6. Output Impedance vs.
Frequency
Figure 9. Gain Bandwidth
Product vs. Temperature
REV. D
AD744
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
CCOMP = 0 pF
Figure 11. Open Loop Gain and
Phase Margin vs. Frequency
CCOMP = 25 pF
Figure 13. Common-Mode and
Power Supply Rejection vs.
Frequency
Figure 14. Large Signal Frequency
Response
Figure 15. Output Swing and Error
vs. Settling Time
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Slew Rate vs. Input
Error Signal
Figure 16. Total Harmonic Distortion
vs. Frequency, Circuit of Figure 20
(G = 10)
REV. D
–5–
Figure 12. Open-Loop Gain vs.
Supply Voltage
AD744 –Typical Characteristics
Figure 19. Settling Time vs. Closed
Loop Voltage Gain
Figure 22a. Unity-Gain Follower
Figure 23a. Unity-Gain Inverter
Figure 20. THD Test Circuit
Figure 22b. Unity-Gain Follower
Large Signal Pulse Response,
CCOMP = 5 pF
Figure 23b. Unity-Gain Inverter Large
Signal Pulse Response, CCOMP = 5 pF
–6–
Figure 21. Offset Null Configuration
Figure 22c. Unity-Gain Follower
Small Signal Pulse Response,
CCOMP = 5 pF
Figure 23c. Unity-Gain Inverter Small
Signal Pulse Response, CCOMP = 0 pF
REV. D
AD744
POWER SUPPLY BYPASSING
The power supply connections to the AD744 must maintain a
low impedance to ground over a bandwidth of 10 MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor
as shown in Figure 24 placed as close as possible to the amplifier (with short lead lengths to power supply common) will
assure adequate high frequency bypassing, in most applications. A minimum bypass capacitance of 0.1 µF should be used
for any application.
The error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. A Tektronix oscilloscope preamp type
7A26 was carefully chosen because it recovers from the
approximately 0.4 V overload quickly enough to allow accurate
measurement of the AD744’s 500 ns settling time. Amplifier A2
is a very high-speed FET-input op amp; it provides a voltage
gain of 10, amplifying the error signal output of the AD744
under test.
+VS
1F
0.1F
AD744
1F
0.1F
–VS
Figure 24. Recommended Power Supply Bypassing
Figure 26. Settling Characteristics 0 to +10 V Step
Upper Trace: Output of AD744 Under Test (5 V/div.)
Lower Trace: Amplified Error Voltage (0.01%/div.)
MEASURING AD744 SETTLING TIME
The photos of Figures 26 and 27 show the dynamic response of
the AD744 while operating in the settling time test circuit of
Figure 25. The input of the settling time fixture is driven by a
flat-top pulse generator. The error signal output from the false
summing node of A1, the AD744 under test, is clamped, amplified by op amp A2 and then clamped again.
+15V
TO
TEKTRONIX
7A26
1M⍀
20pF
OSCILLOSCOPE
PREAMP
INPUT SECTION
(VIA LESS THAN 1 FT 50⍀
COAXIAL CABLE)
VERROR ⴛ 10
206⍀
+VS
COM
–15V
5pF
–VS
A2
AD3554
2X
HP2835
2X
HP2835
0.47F
+VS
0.47F
–VS
Figure 27. Settling Characteristics 0 to –10 V Step
Upper Trace: Output of AD744 Under Test (5 V/div.)
Lower Trace: Amplified Error Voltage (0.01%/div.)
10k⍀
1.1k⍀
0.2pF – 0.8pF
NULL
4.99k⍀
4.99k⍀
200⍀
FLAT-TOP
PULSE
GENERATOR
10k⍀
5pF – 18pF
VIN
AD744
10k⍀
A1
DATA
DYNAMICS
5109
OR
EQUIVALENT
5k⍀
10pF
+VS
1F
0.1F
–VS
1F
0.1F
NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
Figure 25. Settling Time Test Circuit
REV. D
–7–
AD744
EXTERNAL FREQUENCY COMPENSATION
The following section provides tables to show what C COMP values
will provide the necessary compensation for given circuit configurations
and capacitive loads. In each case, the recommended C COMP is a
minimum value. A larger CCOMP can always be used, but slew rate
and bandwidth performance will be degraded.
Even though the AD744 is useable without compensation in
most applications, it may be externally compensated for even
more flexibility. This is accomplished by connecting a capacitor
between Pins 5 and 8. Figure 28, a simplified schematic of the
AD744, shows where this capacitor is connected. This feature is
useful because it allows the AD744 to be used as a unity gain
voltage follower. It also enables the amplifier to drive capacitive
loads up to 2000 pF and greater.
Figure 30 shows the AD744 configured as a unity gain voltage
follower. In this case, a minimum compensation capacitor of
5 pF is necessary for stable operation. Larger compensation capacitors can be used for driving larger capacitive loads. Table I
outlines recommended minimum values for CCOMP based on
the desired capacitive load. It also gives the slew rate and bandwidth that will be achieved for each case.
+VS
400A
2mA
300⍀
300⍀
–IN
+IN
5pF
NULL /
COMPENSATION
+VS
OUTPUT
1F
NULL /
DECOMPENSATION
0.1F
AD744
VOUT
COMPENSATION
1k⍀
1k⍀
VIN
8k⍀
CCOMP
5pF
–VS
1F
Figure 28. AD744 Simplified Schematic
The slew rate and gain bandwidth product of the AD744 are inversely proportional to the value of the compensation capacitor,
C COMP. Therefore, when trying to maximize the speed of the
amplifier, the value of CCOMP should be minimized. CCOMP can
also be used to slow the amplifier to a point where the slew rate
is perfectly symmetrical and well controlled. Figure 29 summarizes the effect of external compensation on slew rate and
bandwidth.
Figure 30. AD744 Connected as a Unity Gain
Voltage Follower
Table I. Recommended Values of C COMP vs.
Various Capacitive Loads
100
2
10
0.2
1.0
0.02
0
10
100
SLEW RATE – V/s
GAIN BANDWIDTH – MHz
20
0.1F
–VS
Gain
Max
CLOAD
(pF)
CCOMP
(pF)
Slew Rate
(V/s)
–3 dB
Bandwidth
(MHz)
1
1
1
50
150
2000
5
10
25
37
25
12.5
6.5
4.3
2.0
Figures 31 and 32 show the AD744 as a voltage follower
with gain and as an inverting amplifier. In these cases, external
compensation is not necessary for stable operation. However, compensation may be applied to drive capacitive loads
above 50 pF. Table II gives recommended CCOMP values, along
with expected slew rates and bandwidths for a variety of load
conditions and gains for the circuits in Figures 31 and 32.
CLEAD*
0.1
1000
R1*
CCOMP – pF
R2*
+VS
Figure 29. Gain Bandwidth and Slew Rate vs. CCOMP
1F
0.1F
AD744
OPTIONAL
CCOMP
VIN
*SEE TABLE II
VOUT
1F
0.1F
–VS
Figure 31. AD744 Connected as a Voltage Follower
Operating at Gains of 2 or Greater
–8–
REV. D
AD744
Table II. Recommended Values of C COMP vs. Various Load Conditions for the Circuits of
Figures 31 and 32.
R1
(⍀)
4.99 k
4.99 k
4.99 k
4.99 k
499 Ω
499 Ω
499 Ω
R2
(⍀)
Gain
Follower
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
4.99 k
2
2
2
2
11
11
11
Gain
Inverter
Max
CLOAD
(pF)
CCOMP
(pF)
1
1
1
1
10
10
10
50
150
1000
>2000
270
390
1000
0
5
20
25
0
2
5
CLEAD
(pF)
7
7
–
–
–
–
–
Slew
Rate
(V/s)
–3 dB
Bandwidth
(MHz)
75
37
14
12.52
75
50
372
2.51
2.31
1.2
1.0
1.2
0.85
0.60
NOTES
1
Bandwidth with C LEAD adjusted for minimum settling time.
2
Into large capacitive loads the AD744’s 25 mA output current limit sets the slew rate of the amplifier, in V/ µs, equal to 0.025
amps divided by the value of C LOAD in µF. Slew rate is specified into rated max C LOAD except for cases marked 2, which are
specified with a 50 pF. load.
CLEAD*
Due to manufacturing variations in the value of the internal
C COMP , it is recommended that the amplifier’s response be
optimized for the desired gain by using a 2 to 10 pF trimmer
capacitor rather than using a fixed value.
R2*
+VS
1F
R1*
0.1F
VIN
R2*
R1*
AD744
VOUT
+VS
1F
OPTIONAL
0.1F
CCOMP
*SEE TABLE II
1F
AD744
0.1F
VOUT
–VS
\
Figure 32. AD744 Connected as an Inverting Amplifier
Operating at Gains of 1 or Greater
NOT CONNECTED
VIN
2 – 10pF
*SEE TABLE III
1F
0.1F
–VS
Using Decompensation to Extend the Gain Bandwidth
Product
When the AD744 is used in applications where the closed-loop
gain is greater than 10, gain bandwidth product may be enhanced
by connecting a small capacitor between Pins 1 and 5 (Figure
33). At low frequencies, this capacitor cancels the effects of the
chip’s internal compensation capacitor, CCOMP, effectively decompensating the amplifier.
REV. D
Figure 33. Using the Decompensation Connection to
Extend Gain Bandwidth
Table III. Performance Summary for the Circuit of Figure 33
R1
(⍀)
R2
(⍀)
1k
100
100
10 k 11
10 k 101
100 k 1001
–9–
Gain
Follower
Gain
Inverter
–3 dB
Bandwidth
Gain/BW
Product
10
100
1000
2.5 MHz
760 kHz
225 kHz
25 MHz
76 MHz
225 MHz
AD744
VCC
REF
OUT
GAIN
ADJUST
100⍀
0.1F
100⍀
BIPOLAR
OFFSET
ADJUST
20V SPAN
10V
REF
IN
AD565A
CLEAD
5k⍀
10V SPAN
9.96k⍀
19.95k⍀
+15V
10pF
1F
5k⍀
DAC OUT
REF
GND
20k⍀
8k⍀
AD744
1F
0.1F
POWER
GND
MSB
–15V
LSB
–VEE
Figure 34. ± 10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer
HIGH-SPEED OP AMP APPLICATIONS
AND TECHNIQUES
A HIGH-SPEED, 3 OP AMP INSTRUMENTATION
AMPLIFIER CIRCUIT
DAC Buffers (I-to-V Converters)
The instrumentation amplifier circuit shown in Figure 36 can
provide a range of gains from unity up to 1000 and higher. The
circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain
of 10; settling time for the entire circuit is less than 2 µs
to within 0.01% for a 10 V step, (G = 10).
Digital-to-analog converters which use bipolar transistors to
switch currents into (or out of) their outputs can achieve very
fast settling times. The AD565A, for example, is specified to
settle to 12 bits in less than 250 ns, with a current output. However, in many applications, a voltage output is desirable, and it
would be useful – perhaps essential – that this I-to-V conversion
be accomplished without increasing the settling time or without
degrading the accuracy of the DAC.
Figure 34 is a schematic of an AD565A DAC using an AD744
output buffer. The 10 pF CLEAD capacitor compensates for the
DAC’s output capacitance, plus the 5.5 pF amplifier input
capacitance.
Figure 35 is an oscilloscope photo of the AD744’s output voltage with a +10 V to 0 V step applied; this corresponds to an all
“1s” to all “0s” code change on the DAC. Since the DAC is
While the AD744 is not stable with 100% negative feedback (as
when connected as a standard voltage follower), phase margin
and therefore stability at unity gain may be increased to an acceptable level by placing the parallel combination of a resistor and a
small lead capacitor between each amplifier’s output and its
inverting input terminal.
The only penalty associated with this method is a small bandwidth reduction at low gains. The optimum value for CLEAD
may be determined from the graph of Figure 41. This technique
can be used in the circuit of Figure 36 to achieve stable operation at gains from unity to over 1000.
CIRCUIT GAIN =
20,000
+1
RG
AD744
*1.5pF – 20pF
(TRIM FOR BEST SETTLING TIME)
–IN
A1
**10k⍀
10k⍀
7.5pF
**10k⍀
7.5pF
RG
SENSE
A3
**10k⍀
10k⍀
AD744
5pF
**10k⍀
A2
REFERENCE
+IN
AD744
Figure 35. Upper Trace: AD744 Output Voltage for
a +10 V to 0 V Step, Scale: 5 mV/div.
Lower Trace: Logic Input Signal, Scale: 5 V/div.
*VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
**RATIO MATCHED 1% METAL FILM RESISTORS
+VS
+15V
1F
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV.
Output settling time for the AD565/AD744 combination is less
than 500 ns to within a 2.44 mV, 1/2 LSB error band.
PIN 7
1F
0.1F
1F
0.1F
COMM
1F
–15V
–VS
EACH
AMPLIFIER
PIN 4
FOR OPTIONAL OFFSET ADJUSTMENT:
TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
Figure 36. A High Performance, 3 Op Amp
Instrumentation Amplifier Circuit
–10–
REV. D
AD744
Table IV. Performance Summary for the 3 Op Amp
Instrumentation Amplifier Circuit
Gain
RG
Bandwidth
T Settle (0.01%)
1
2
10
100
NC
20 kΩ
2.22 kΩ
202 Ω
3.5 MHz
2.5 MHz
1 MHz
290 kHz
1.5 µs
1.0 µs
2 µs
5 µs
Equation 1 would completely describe the output of the system
if not for the op amp’s finite slew rate and other nonlinear
effects. Even considering these effects, the fine scale settling to
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