ADF4002

Phase Detector/Frequency Synthesizer ADF4002 FEATURES 400 MHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 200 MHz phase detector GENERAL DESCRIPTION The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a stand alone PFD and charge pump. APPLICATIONS Clock conditioning Clock generation IF LO generation FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP CPGND REFERENCE REFIN 14-BIT R COUNTER 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER FUNCTION LATCH N COUNTER LATCH LOCK DETECT CURRENT SETTING 1 CPI3 CPI2 CPI1 CURRENT SETTING 2 CPI6 CPI5 CPI4 HIGH Z AVDD MUX SDOUT RFINA RFINB 13-BIT N COUNTER MUXOUT PHASE FREQUENCY DETECTOR RSET CHARGE PUMP CP 22 SDOUT M3 M2 M1 ADF4002 CE AGND DGND 06052-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADF4002 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 Reference Input Section............................................................... 8 RF Input Stage............................................................................... 8 N Counter...................................................................................... 8 R Counter ...................................................................................... 8 Phase Frequency Detector (PFD) and Charge Pump.............. 8 MUXOUT and Lock Detect.........................................................9 Input Shift Register .......................................................................9 Latch Maps and Descriptions ....................................................... 10 Latch Summary........................................................................... 10 Reference Counter Latch Map.................................................. 11 N Counter Latch Map................................................................ 12 Function Latch Map................................................................... 13 Initialization Latch Map ............................................................ 14 The Function Latch.................................................................... 15 The Initialization Latch ............................................................. 16 Applications..................................................................................... 17 Very Low Jitter Encode Clock for High Speed Converters... 17 PFD............................................................................................... 18 Interfacing ................................................................................... 18 PCB Design Guidelines for Chip Scale Package .................... 18 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADF4002 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Sensitivity RF Input Frequency (RFIN) REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 2 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage ICP vs. VCP Sink and Source Current Matching ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 5 (AIDD + DIDD) IP Power-Down Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor 6 1 2 Min −10 5 20 0.8 B Version 1 Typ Max 0 400 300 VDD 10 ±100 200 Unit dBm MHz MHz V p-p pF μA MHz Test Conditions/Comments See Figure 12 for input circuit For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs For REFIN < 20 MHz, ensure SR > 50 V/μs Biased at AVDD/2 3 Programmable, see Figure 19 5 625 2.5 3.0 1 1.5 2 2 1.4 0.6 ±1 10 1.4 VDD – 0.4 100 0.4 2.7 AVDD AVDD 5.0 1 –222 3.3 5.5 6.0 0.4 11 mA μA % kΩ nA % % % V V μA pF V V μA V V V mA mA μA dBc/Hz AVDD ≤ VP ≤ 5.5 V TA = 25°C AIDD + DIDD Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 μA With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Figure 19 TA = 25°C 0.5 V ≤ VCP ≤ VP – 0.5 V 0.5 V ≤ VCP ≤ VP – 0.5 V VCP = VP/2 Operating temperature range (B version) is –40°C to +85°C. AVDD = DVDD = 3 V. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. Use of the PFD at frequencies above 104 MHz requires the minimum antibacklash pulse width enabled. 5 TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN frequency in MHz. 6 The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10logFPFD. PNSYNTH = PNTOT – 10logFPFD – 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the EVALADF4002EB1 and the HP8644B as the PLL reference. Rev. 0 | Page 3 of 24 ADF4002 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. 1 Table 2. Parameter t1 t2 t3 t4 t5 t6 1 2 Limit (B Version) 2 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Guaranteed by design, but not production tested. Operating temperature range (B version) is –40°C to +85°C. Timing Diagram t3 CLK t4 t1 DATA DB23 (MSB) DB22 t2 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 LE 06052-022 Figure 2. Timing Diagram Rev. 0 | Page 4 of 24 ADF4002 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Transistor Count CMOS Bipolar 1 Rating –0.3 V to +3.6 V –0.3 V to +0.3 V –0.3 V to +5.8 V –0.3 V to +5.8 V –0.3 V to VDD + 0.3 V –0.3 V to VP + 0.3 V –0.3 V to VDD + 0.3 V –40°C to +85°C –65°C to +125°C 150°C 215°C 220°C 6425 303 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of