Phase Detector/Frequency Synthesizer
ADF4002
Data Sheet
FEATURES
GENERAL DESCRIPTION
400 MHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase detector
The ADF4002 frequency synthesizer is used to implement local
oscillators in the upconversion and downconversion sections of
wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge
pump, a programmable reference divider, and programmable
N divider. The 14-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled
oscillator (VCO). In addition, by programming R and N to 1,
the device can be used as a standalone PFD and charge pump.
APPLICATIONS
Clock conditioning
Clock generation
IF LO generation
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RSET
CPGND
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
14
R COUNTER
LATCH
CLK
DATA
LE
24-BIT INPUT
REGISTER
22
LOCK
DETECT
FUNCTION
LATCH
CURRENT
SETTING 2
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
HIGH Z
N COUNTER
LATCH
SDOUT
CURRENT
SETTING 1
AVDD
MUXOUT
MUX
SDOUT
RFINA
RFINB
13-BIT
N COUNTER
M3 M2 M1
CE
AGND
06052-001
ADF4002
DGND
Figure 1.
Rev. D
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ADF4002
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
MUXOUT and Lock Detect.........................................................9
Applications ....................................................................................... 1
Input Shift Register .......................................................................9
General Description ......................................................................... 1
Latch Maps and Descriptions ....................................................... 10
Functional Block Diagram .............................................................. 1
Latch Summary........................................................................... 10
Revision History ............................................................................... 2
Reference Counter Latch Map .................................................. 11
Specifications..................................................................................... 3
N Counter Latch Map ................................................................ 12
Timing Characteristics ................................................................ 4
Function Latch Map ................................................................... 13
Absolute Maximum Ratings............................................................ 5
Initialization Latch Map ............................................................ 14
Thermal Characteristics .............................................................. 5
Function Latch ............................................................................ 15
ESD Caution .................................................................................. 5
Initialization Latch ..................................................................... 16
Pin Configurations and Function Descriptions ........................... 6
Applications..................................................................................... 17
Typical Performance Characteristics ............................................. 7
Very Low Jitter Encode Clock for High Speed Converters... 17
Theory of Operation ........................................................................ 8
PFD............................................................................................... 17
Reference Input Section ............................................................... 8
Interfacing ................................................................................... 17
RF Input Stage ............................................................................... 8
PCB Design Guidelines for Chip Scale Package .................... 18
N Counter ...................................................................................... 8
Outline Dimensions ....................................................................... 19
R Counter ...................................................................................... 8
Ordering Guide .......................................................................... 19
Phase Frequency Detector (PFD) and Charge Pump .............. 8
REVISION HISTORY
9/15—Rev. C to Rev. D
Changed ADSP21xx to ADSP-2181 ............................ Throughout
Changes to Table 3 ............................................................................ 5
Changes to Figure 4 .......................................................................... 6
Changes to Very Low Jitter Encode Clock for High Speed
Converters Section and Figure 20 ................................................ 17
Update Outline Dimensions ......................................................... 19
Changes to Ordering Guide .......................................................... 19
12/12—Rev. B to Rev. C
Change to Table 1 ............................................................................. 4
Added RFINA to RFINB Parameter, Table 3 .................................... 5
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
9/11—Rev. A to Rev. B
Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter
and Endnote 6, Table 1 .....................................................................4
Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 7,
Table 1 .................................................................................................4
Changes to Figure 4 and Table 5 ......................................................6
Updated Outline Dimensions ....................................................... 19
4/07—Rev. 0 to Rev. A
Changes to Features List ...................................................................1
Changes to Table 1.............................................................................3
Deleted Figure ....................................................................................7
Changes to Figure 16...................................................................... 11
4/06—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
ADF4002
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Sensitivity
RF Input Frequency (RFIN)
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity 2
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency 4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
ICP vs. VCP
Sink and Source Current Matching
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD 5 (AIDD + DIDD)
IP
Power-Down Mode
Min
B Version 1
Typ
Max
Unit
Test Conditions/Comments
See Figure 11 for input circuit
−10
5
0
400
dBm
MHz
20
0.8
300
VDD
10
±100
MHz
V p-p
pF
µA
For REFIN < 20 MHz, ensure SR > 50 V/µs
Biased at AVDD/2 3
104
MHz
ABP = 0, 0 (2.9 ns antibacklash pulse width)
Programmable, see Figure 18
mA
µA
%
kΩ
nA
%
%
%
With RSET = 5.1 kΩ
5
625
2.5
3.0
11
1
1.5
2
2
1.4
0.6
±1
10
V
V
µA
pF
100
0.4
V
V
µA
V
3.3
V
5.5
6.0
0.4
V
mA
mA
µA
1.4
VDD − 0.4
2.7
AVDD
AVDD
5.0
1
Rev. D | Page 3 of 20
For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/µs
With RSET = 5.1 kΩ
See Figure 18
TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
CMOS output chosen
IOL = 500 µA
AVDD ≤ VP ≤ 5.5 V
TA = 25°C
AIDD + DIDD
ADF4002
Data Sheet
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH) 6
Normalized 1/f Noise (PN1_f) 7
Min
B Version 1
Typ
Max
−222
−119
Unit
Test Conditions/Comments
dBc/Hz
dBc/Hz
PLL loop bandwidth = 500 kHz, measured at 100 kHz offset
10 kHz offset; normalized to 1 GHz
Operating temperature range (B version) is −40°C to +85°C.
AVDD = DVDD = 3 V.
AC coupling ensures AVDD/2 bias.
4
Guaranteed by design. Sample tested to ensure compliance.
5
TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN
frequency in MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value)
and 10 logFPFD. PNSYNTH = PNTOT – 10 logFPFD – 20 logN.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). All phase noise measurements were performed with the EV-ADF4002SD1Z and the
Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
1
2
3
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted. 1
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
1
2
Limit (B Version) 2
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Guaranteed by design, but not production tested.
Operating temperature range (B version) is −40°C to +85°C.
Timing Diagram
t3
t4
CLK
t1
DATA DB23 (MSB)
t2
DB22
DB2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
06052-022
t5
LE
Figure 2. Timing Diagram
Rev. D | Page 4 of 20
Data Sheet
ADF4002
ABSOLUTE MAXIMUM RATINGS
This device is a high performance RF integrated circuit with an
ESD rating of