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CLVC1G374QDBVRQ1

CLVC1G374QDBVRQ1

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOT23-6

  • 描述:

    IC FF D-TYPE SNGL 1BIT SOT23-6

  • 数据手册
  • 价格&库存
CLVC1G374QDBVRQ1 数据手册
SN74LVC1G374-Q1 www.ti.com SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 Single D-Type Flip-Flop with 3-State Output Check for Samples: SN74LVC1G374-Q1 FEATURES 1 • • • • • • • • • Qualified for Automotive Applications Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flipflop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DBV OR DCK PACKAGE (TOP VIEW) CLK 1 6 OE GND 2 5 VCC D 3 4 Q 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated SN74LVC1G374-Q1 SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. FUNCTION TABLE INPUTS OE CLK D L L L H ↑ ↑ H or L X L H X X OUTPUT Q L H Q Z LOGIC DIAGRAM (POSITIVE LOGIC) 6 OE CLK 1 C1 4 D 3 Q D ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V –0.5 VCC + 0.5 VO Voltage range applied to any output in the high or low state (2) (3) UNIT V IIK Input clamp current, (VI < 0) –50 mA IOK Output clamp current, (VO < 0) –50 mA IO Continuous output current Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DBV package DCK package 65 ±50 mA ±100 mA 165 °C 259 °C 150 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC (1) 2 Supply voltage Operating Data retention only MIN MAX 1.65 5.5 1.5 UNIT V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374-Q1 SN74LVC1G374-Q1 www.ti.com SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 RECOMMENDED OPERATING CONDITIONS(1) (continued) MIN VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.7 Low-level input voltage VI Input voltage VO Output voltage 0.7 – VCC 0.35 – VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V 0.3 – VCC 5.5 V 0 VCC V −4 −8 VCC = 2.3 V High-level output current −16 VCC = 3 V −24 VCC = 4.5 V −32 VCC = 5 V, TA = −40°C to 85°C −40 VCC = 1.65 V ∆t/∆v Low-level output current Input transition rise or fall rate 8 16 VCC = 3 V 24 VCC = 4.5 V 32 VCC = 5 V, TA = −40°C to 85°C 40 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374-Q1 mA ns/V 5 −40 Operating free-air temperature mA 4 VCC = 2.3 V IOL V 0 VCC = 1.65 V IOH UNIT V 2 VCC = 1.65 V to 1.95 V VIL MAX 0.65 – VCC 125 Submit Documentation Feedback °C 3 SN74LVC1G374-Q1 SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 µA VOH VOL (1) TYP TA = −40°C to 125°C MIN TYP (1) MAX VCC − 0.1 VCC − 0.1 1.65 V 1.2 1.2 IOH = −8 mA 2.3 V 1.9 1.9 1.65 V to 5.5 V IOH = −16 mA MAX 2.4 2.4 IOH = −24 mA 3V 2.3 2.3 IOH = −32 mA 4.5 V 3.8 3.8 IOH = −40 mA 5V 4.4 IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1 IOL = 4 mA 1.65 V 0.45 0.45 IOL = 8 mA 2.3 V 0.3 0.3 IOL = 16 mA 0.4 0.5 3V 0.55 0.65 IOL = 32 mA 4.5 V 0.55 0.65 5V 0.513 VI = 5.5 V or GND VO = 0 to 5.5 V Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 One input at VCC − 0.6 V, Other inputs at VCC or GND UNIT V IOL = 24 mA IOZ ΔICC MIN (1) IOH = −4 mA IOL = 40 mA II TA = −40°C to 85°C VCC V 0 to 5.5 V ±1 ±2 µA 1.65 V to 5.5 V ±5 ±12 µA 0 ±10 ±25 µA 1.65 V to 5.5 V 10 10 µA 3 V to 5.5 V 500 500 µA Ci VI = VCC or GND 3.3 V 3 3 pF Co VO = VCC or GND 3.3 V 6 6 pF All typical values are at VCC = 3.3 V, TA = 25°C. TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX MIN MAX MIN MAX MIN 150 UNIT MAX Clock frequency tw Pulse duration, CLK high or low 3.3 3 2.8 2.5 ns tsu Setup time, data before CLK↑ 3.5 2.5 2 1.5 ns th Hold time, data after CLK↑ 3.4 1.6 1.5 1.5 ns Submit Documentation Feedback 125 VCC = 5 V ± 0.5 V fclock 4 100 VCC = 3.3 V ± 0.3 V 175 MHz Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374-Q1 SN74LVC1G374-Q1 www.ti.com SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 SWITCHING CHARACTERISTICS over free-air temperature range of −40°C to 85°C, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) VCC = 1.8 V ± 0.15 V TO (OUTPUT) MIN fmax VCC = 2.5 V ± 0.2 V MAX 100 MIN VCC = 3.3 V ± 0.3 V MAX MIN 125 VCC = 5 V ± 0.5 V MAX 150 MIN UNIT MAX 175 MHz tpd CLK Q 2.7 18.3 1.8 8.2 1.6 6 1 4 ns ten OE Q 2 13 1.5 6.3 0.9 5 0.7 3.5 ns tdis OE Q 2 14 1.1 5.3 1.4 4.5 0.8 3.1 ns SWITCHING CHARACTERISTICS over free-air temperature range of −40°C to 125°C, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 1) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V FROM (INPUT) TO (OUTPUT) tpd CLK Q 2.7 18.3 1.8 10.2 1.6 7 1 5 ns ten OE Q 2 14 1.5 8.3 0.9 6.5 0.7 5.5 ns tdis OE Q 2 16 1.1 7.3 1.4 6 0.8 5.1 ns PARAMETER MIN fmax MAX 100 MIN MAX MIN 125 MAX 150 MIN UNIT MAX 175 MHz OPERATING CHARACTERISTICS, TA = 25°C PARAMETER Power dissipation Outputs enabled Cpd capacitance Outputs disabled TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 24 24 25 27 8 8 9 11 Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374-Q1 Submit Documentation Feedback UNIT pF 5 SN74LVC1G374-Q1 SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tPLH/tPHL Open tPLZ/tPZL VLOAD tPHZ/tPZH GND LOAD CIRCUIT INPUTS VCC VM VLOAD CL £2 ns VCC/2 2 × VCC £2 ns VCC/2 2 × VCC 3V £2.5 ns 1.5 V VCC £2.5 ns VCC/2 VI tr/tf 1.8 V ± 0.15 V VCC 2.5 V ± 0.2 V VCC 3.3 V ± 0.3 V 5 V ± 0.5 V RL VΔ 30 pF 1 kΩ 0.15 V 30 pF 500 Ω 0.15 V 6V 50 pF 500 Ω 0.3 V 2 × VCC 50 pF 500 Ω 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL tPLZ Output Waveform 1 S1 at VLOAD (see Note B) VLOAD/2 VM VOL + VD tPZH VM VM VM 0V tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374-Q1 SN74LVC1G374-Q1 www.ti.com SCES607B – SEPTEMBER 2004 – REVISED MAY 2013 REVISION HISTORY Changes from Revision A (April 2008) to Revision B • Page Removed Ordering Information table. ................................................................................................................................... 1 Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G374-Q1 Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CLVC1G374QDBVRQ1 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CA4O CLVC1G374QDCKRQ1 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 D4O (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
CLVC1G374QDBVRQ1 价格&库存

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CLVC1G374QDBVRQ1
  •  国内价格
  • 5+1.47053
  • 50+1.17429
  • 150+1.04728
  • 500+0.88884

库存:0