SN74LVC1G125-Q1
SGES002E – APRIL 2003 –SN74LVC1G125-Q1
REVISED AUGUST 2020
SGES002E – APRIL 2003 – REVISED AUGUST 2020
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SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output
1 Features
3 Description
•
This bus buffer gate is designed for 1.65-V to 5.5-V
VCC operation.
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to +125°C
Ambient Operating Temperature Range
– Device Human-Body Model (HBM) ESD
Classification Level 2
– Device Charged-Device Model (CDM) ESD
Classification Level C5
Available in the small 1.45-mm2
package (DRY) With 0.5-mm Pitch
Supports 5-V VCC Operation
Over-voltage tolerant inputs accept
voltages to 5.5 V
Provides down translation to VCC
Max tpd of 3.7 ns at 3.3 V
Low power consumption, 10-μA Max ICC
±24-mA Output drive at 3.3 V
Ioff supports live insertion, partial-power-down
mode, and back-drive protection
Latch-up performance exceeds 100 mA
Per JESD 78, Class II
The SN74LVC1G125-Q1 device is a single line driver
with a 3-state output. The output is disabled when the
output-enable ( OE) input is high.
The CMOS device has high output drive while
maintaining low static power dissipation over a broad
VCC operating range.
The SN74LVC1G125-Q1 device is available in a
variety of packages including the small DRY package
with a body size of 1.45 mm × 1.00 mm.
Device Information
PACKAGE(1)
BODY SIZE (NOM)
CLVC1G125QDBVRQ1
SOT-23 (5)
2.90 mm × 1.60 mm
1P1G125QDCKRQ1
SC70 (5)
2.00 mm × 1.25 mm
1P1G125QDRYRQ1
SON (6)
1.45 mm × 1.00 mm
DEVICE NAME
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
Qualified for Automotive Applications
Increase digital signal drive strength
Redrive up to 100 MHz square wave signals
Enable or disable a digital signal with highimpedance off state
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................6
6.7 Operating Characteristics........................................... 6
6.8 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Receiving Notification of Documentation Updates..13
12.2 Support Resources................................................. 13
12.3 Trademarks............................................................. 13
12.4 Electrostatic Discharge Caution..............................13
12.5 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2019) to Revision E (August 2020)
Page
• Updated device names for SC70 and SOT-23 packages in the Device Information table................................. 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
Changes from Revision C (April 2008) to Revision D (August 2019)
Page
• Changed data sheet format to new TI standard ................................................................................................ 1
• Added DRY package to Pin Configuration and Functions ................................................................................. 3
• Added Pin Functions table. ................................................................................................................................3
• Added Handling Ratings table. .......................................................................................................................... 4
• Added Thermal Information table. ..................................................................................................................... 5
• Added –40°C to 125°C Temperature range to Electrical Characteristics ...........................................................6
• Added Detailed Description section. ................................................................................................................10
• Added Application and Implementation section. .............................................................................................. 11
• Added Layout section. ..................................................................................................................................... 12
2
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5 Pin Configuration and Functions
OE
1
A
2
GND
3
5
4
VCC
OE
1
A
2
GND
3
5
VCC
4
Y
Figure 5-2. DCK package 5-pin SC70 (Top View)
Y
Figure 5-1. DBV package 5-pin SOT-23 (Top View)
OE
1
6
VCC
A
2
5
N.C.
GND
3
4
Y
N.C. – No internal connection
See mechanical drawings for dimensions.
Figure 5-3. DRY package 6-pin SON (Transparent Top View)
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DBV, DCK
DRY
OE
1
1
Input
Active low Output Enable Input
A
2
2
Input
Input A
GND
3
3
—
Ground
Y
4
4
Output
VCC
5
6
—
Positive supply
NC
–
5
—
No internal connection
Output Y
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
V
range(2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
state(2) (3)
UNIT
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
–50
VO < 0
–50
mA
±50
mA
±100
mA
150
°C
150
°C
IOK
Output clamp current
IO
Continuous output current
TJ
Junction temperature
Tstg
Storage temperature
Continuous current through VCC or GND
(1)
(2)
(3)
–65
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per AEC
HBM ESD Classification Level
Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level
UNIT
±2000
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
(1)
VCC
Operating
Supply voltage
Data retention only
1.65
5.5
1.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level input voltage
VI
Input voltage
VO
Output voltage
0.7 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
5.5
V
0
VCC
V
–4
VCC = 2.3 V
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
mA
24
VCC = 4.5 V
24
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
0
VCC = 1.65 V
IOH
V
V
2
VCC = 1.65 V to 1.95 V
VIL
UNIT
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
ns/V
5
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC1G125-Q1
THERMAL
METRIC(1)
DBV
DCK
DRY
5 PINS
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
229
278
439
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
164
93
277
°C/W
RθJB
Junction-to-board thermal resistance
62
65
271
°C/W
ψJT
Junction-to-top characterization parameter
44
2
84
°C/W
ψJB
Junction-to-board characterization parameter
62
64
271
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
–
–
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOH = –16 mA
3V
2.4
3V
2.3
4.5 V
3.8
V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
3V
0.4
3V
0.55
4.5 V
0.55
VI = 5.5 V or GND
UNIT
MAX
1.65 V to 5.5 V
IOL = 24 mA
A or OE
inputs
TYP(1)
VCC – 0.1
IOH = –4 mA
IOL = 100 μA
II
MIN
1.65 V to 5.5 V
IOH = –24 mA
VOL
–40 °C to 125 °C
VCC
V
0 to 5.5 V
±5
μA
Ioff
VI or VO = 5.5 V
0
±10
μA
IOZ
VO = 0 to 5.5 V
3.6 V
10
μA
1.65 V to 5.5 V
10
μA
3 V to 5.5 V
500
μA
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VC C or GND
IO = 0
CI
VI = VCC or GND
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
3.3 V
4
pF
6.6 Switching Characteristics
over recommended operating free-air temperature range of –40°C to 125°C, CL = 50 pF (unless otherwise
noted)
(see Figure 7-1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
Y
1
5.1
1
4.1
ns
OE
Y
1
6
1
5
ns
OE
Y
1
5
1
4.2
ns
TEST
CONDITIONS
VCC = 3.3 V
VCC = 5 V
TYP
TYP
19
21
2
4
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation
capacitance
Outputs enabled
Outputs disabled
f = 10 MHz
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UNIT
pF
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6.8 Typical Characteristics
2.5
5
TPD
2
4
1.5
3
TPD - ns
TPD - ns
TPD
1
0.5
0
-100
2
1
-50
0
50
Temperature - °C
100
150
0
0
1
D001
Figure 6-1. TPD Across Temperature at 3.3 V VCC
2
3
Vcc - V
4
5
6
D002
Figure 6-2. TPD Across VCC at 25°C
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC1G125-Q1 device contains one buffer gate device with output enable control and performs the
Boolean function Y = A. This device is fully specified for partial-power-down applications using Ioff. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
8.3 Feature Description
•
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 5.5 V
Allows down voltage translation
Inputs accept voltages to 5.5 V
Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V
8.4 Device Functional Modes
Table 8-1. Function Table
INPUTS
10
OE
A
L
H
OUTPUT
Y
H
L
L
L
H
X
Z
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G125-Q1 device is a high drive CMOS device that can be used as a output enabled buffer with a
high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5 V tolerant
allowing it to translate down to VCC.
9.2 Typical Application
Buffer Function
Basic LED Driver
VCC
VCC
uC or Logic
uC or Logic
Wired OR
uC or Logic
uC or Logic
LVC1G125
uC or Logic
LVC1G125
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
• Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
• Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
• Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
• Outputs should not be pulled above VCC.
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9.2.3 Application Curves
10
Icc
Icc
Icc
Icc
9
8
1.8V
2.5V
3.3V
5V
Icc - mA
7
6
5
4
3
2
1
0
0
20
40
Frequency - MHz
60
80
D003
Figure 9-2. ICC vs Frequency, Square wave input signal
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages
at the outside connections result in undefined operational states. Figure 11-1 shows the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is
more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Package Layout
12
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
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12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G125-Q1
13
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
1P1G125QDCKRG4Q1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CMR
Samples
1P1G125QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CMJ, CMR)
Samples
1P1G125QDRYRQ1
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FX
Samples
CLVC1G125QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C25O
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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