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DRV8304
SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
DRV8304 38-V 3-Phase Smart Gate Driver
1 Features
3 Description
•
The DRV8304 device is an integrated gate driver for
3-phase brushless DC (BLDC) motors applications for
12-V and 24-V DC rails. These applications include
field-oriented control (FOC), sinusoidal current
control, and trapezoidal current control of BLDC
motors. The device integrates three current-sense
amplifiers (CSA) for sensing the phase currents of
BLDC motors for optimum FOC and current-control
system implementation. An AUTOCAL feature
automatically calibrates the CSA offset error for
accurate current sensing.
•
•
•
•
•
•
•
•
•
6-V to 38-V, Triple Half-Bridge Gate Driver With
Integrated 3x Current Sense Amplifiers (CSA)
– 40-V Absolute Maximum Rating
– Fully Optimized for 12-V and 24-V DC Rails
– Drives High-Side and Low-Side N-Channel
MOSFETs
– Supports 100% PWM Duty Cycle
Smart Gate-Drive Architecture
– Adjustable Slew-Rate Control for Better EMI
and EMC Performance
– VGS Hand-Shake and Minimum Dead-Time
Insertion to Avoid Shoot-Through
– 15-mA to 150-mA Peak Source Current
– 30-mA to 300-mA Peak Sink Current
6x, 3x, 1x and Independent PWM Modes
– Supports 120º Sensored Operation
Integrated Gate-Driver Power Supplies
– High-Side Doubler Charge Pump
– Low-Side Linear Regulator
Integrated Triple Current-Shunt Amplifiers
– Adjustable Gain (5, 10, 20, 40 V/V)
– Bidirectional or Unidirectional Support
SPI or Hardware Device Variants
Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
Low-Power Sleep Mode
Linear Voltage Regulator, 3.3-V, 30-mA
Integrated Protection Features
– VM Undervoltage Lockout (UVLO)
– Charge Pump Undervoltage (CPUV)
– MOSFET VDS Overcurrent Protection (OCP)
– MOSFET Shoot-Through Protection
– Gate Driver Fault (GDF)
– Thermal Warning and Shutdown (OTW/OTSD)
– Fault Condition Indicator (nFAULT)
The device is based on smart gate-drive (SGD)
architecture to eliminate the need of any external
gate components (resistors and Zener diodes) while
fully protecting the external FETs. The SGD
architecture optimizes dead time to avoid any shootthrough conditions, provides flexibility in decreasing
electromagnetic interference (EMI) by gate slew-rate
control, and protects against any gate-short
conditions through VGS hand-shaking and dead time
insertion. Strong pulldown current also prevents any
dv/dt gate turnon.
Various PWM control modes (1x, 3x, 6x, and
independent) are supported for simple interfacing to
control circuits that can be powered by the 30-mA,
3.3-V internal regulator. These modes decrease the
number of output peripherals of the controller for the
specific motor-control requirements and provide
flexibility of control. The device also has a 1x mode
for sensored trapezoidal control of the BLDC motor
by using the internal block-commutation table. The
device can also be configured to drive multiple loads,
such as solenoids, in independent mode.
Device Information(1)
PART NUMBER
DRV8304
PACKAGE
VQFN (40)
Simplified Schematic
6 to 38 V
PWM
Controller
Printers
BLDC Motor Modules
White Goods
CPAPs, Fans, and Pumps
Drones, Robotics, and RC Toys
ATM and Currency Counting
SPI
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
INTERFACE
Hardware
DRV8304
ENABLE
H/W
nFAULT
Sense Output
3 Half Bridge
Smart Gate Driver
Gate
Drive
Current
Sense
N-Channel
MOSFETs
1
M
3x Shunt Amplifiers
Built-In Protection
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
DRV8304
SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
13
14
16
35
35
7.6 Register Maps ......................................................... 37
8
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application ................................................. 45
9
Power Supply Recommendations...................... 53
9.1 Bulk Capacitance Sizing ......................................... 53
10 Layout................................................................... 54
10.1 Layout Guidelines ................................................. 54
10.2 Layout Example .................................................... 55
11 Device and Documentation Support ................. 56
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
56
56
56
57
57
57
57
12 Mechanical, Packaging, and Orderable
Information ........................................................... 57
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2018) to Revision B
•
Deleted preview status from the SPI version of the device.................................................................................................... 1
Changes from Original (November 2017) to Revision A
•
2
Page
Page
Changed the data sheet from Advance Information to Production Data................................................................................ 1
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DRV8304
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SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
5 Pin Configuration and Functions
INHB
INLA
INHA
DVDD
AGND
CAL
35
34
33
32
31
CAL
31
36
AGND
32
INLB
DVDD
33
INHC
INHA
34
37
INLA
35
38
INHB
36
INLC
INLB
37
PGND
INHC
38
39
INLC
39
DRV8304S RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
40
PGND
40
DRV8304H RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
CPL
1
30
ENABLE
CPL
1
30
ENABLE
CPH
2
29
GAIN
CPH
2
29
nSCS
VCP
3
28
VDS
VCP
3
28
SCLK
VM
4
27
IDRIVE
VM
4
27
SDI
VDRAIN
5
26
MODE
VDRAIN
5
26
SDO
Thermal
Thermal
Pad
Pad
15
16
17
18
19
20
GHB
SHC
GLC
SPC
SNC
14
GHC
13
GLB
Not to scale
SHB
SOC
12
SOB
21
11
22
10
SPB
9
SNA
SNB
SPA
SOC
20
SOB
21
SNC
22
10
19
9
18
SPA
SNA
SPC
SOA
GLC
23
17
8
SHC
GLA
16
SOA
15
23
GHB
8
GHC
VREF
GLA
14
nFAULT
24
13
25
7
GLB
6
SHA
SHB
GHA
VREF
12
nFAULT
24
11
25
7
SPB
6
SHA
SNB
GHA
Not to scale
Pin Functions
PIN
NAME
TYPE (1)
NO.
DESCRIPTION
DRV8304H
DRV8304S
AGND
32
32
PWR
CAL
31
31
I
CPH
2
2
PWR
Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic
capacitor between the CPH and CPL pins.
CPL
1
1
PWR
Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic
capacitor between the CPH and CPL pins.
DVDD
33
33
PWR
3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic
capacitor between the DVDD and AGND pins. This regulator can source up to 30
mA externally.
ENABLE
30
30
I
Gate driver enable. When this pin is logic low the device enters a low power sleep
mode. An 5 to 32-µs low pulse can be used to reset fault conditions.
GAIN
29
—
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
Device analog ground. Connect to system ground.
Amplifier calibration input. Set logic high to internally short amplifier inputs and
perform offset calibration.
GHA
6
6
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
15
15
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
16
16
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
8
8
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
13
13
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
18
18
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE
27
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external
resistor.
INHA
34
34
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver (GHA).
(1)
PWR = power, I = input, O = output, OD = open-drain
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SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
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Pin Functions (continued)
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
DRV8304H
DRV8304S
INHB
36
36
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver (GHB).
INHC
38
38
I
High-side gate driver control input. This pin controls the output of the high-side gate
driver (GHC).
INLA
35
35
I
Low-side gate driver control input. This pin controls the output of the low-side gate
driver (GLA).
INLB
37
37
I
Low-side gate driver control input. This pin controls the output of the low-side gate
driver (GLB).
INLC
39
39
I
Low-side gate driver control input. This pin controls the output of the low-side gate
driver (GLC).
MODE
26
—
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT
25
25
OD
nSCS
—
29
I
PGND
40
40
PWR
SCLK
—
28
I
Serial clock input. Serial data is shifted out and captured on the corresponding
rising and falling edge on this pin.
SDI
—
27
I
Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO
—
26
OD
Fault indicator output. This pin is pulled logic low during a fault condition and
requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Device power ground. Connect to system ground.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin
requires an external pullup resistor.
SHA
7
7
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHB
14
14
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
17
17
I
High-side source sense input. Connect to the high-side power MOSFET source.
SNA
10
10
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB
11
11
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC
20
20
I
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA
23
23
O
Shunt amplifier output.
SOB
22
22
O
Shunt amplifier output.
SOC
21
21
O
Shunt amplifier output.
SPA
9
9
I
Low-side source sense and shunt amplifier input. Connect to the low-side power
MOSFET source and high-side of the current shunt resistor.
SPB
12
12
I
Low-side source sense and shunt amplifier input. Connect to the low-side power
MOSFET source and high-side of the current shunt resistor.
SPC
19
19
I
Low-side source sense and shunt amplifier input. Connect to the low-side power
MOSFET source and high-side of the current shunt resistor.
VCP
3
3
PWR
VDRAIN
5
5
I
High-side MOSFET drain sense input. Connect to the common point of the external
MOSFET drains.
VDS
28
—
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external
resistor.
VM
4
4
PWR
Gate driver power supply input. Connect to the bridge power supply. Connect a
X5R or X7R, 0.1-µF, VM-rated ceramic and greater than or equal to 10-uF local
capacitance between the VM and PGND pins.
VREF
24
24
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-μF,
6.3-V ceramic capacitor between the VREF and AGND pins.
4
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor
between the VCP and VM pins.
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SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Power supply voltage (VM)
–0.3
40
V
Voltage differential between any ground pin (AGND, DGND, PGND)
–0.5
0.5
V
Internal logic regulator voltage (DVDD)
–0.3
3.8
V
MOSFET voltage sense (VDRAIN)
–0.3
40
V
Charge pump voltage (VCP, CPH)
–0.3
VM + 13.5
V
Charge pump negative switching pin voltage (CPL)
–0.3
VM
V
Digital pin voltage (SCLK, SDI, nSCS, ENABLE, VDS, IDRIVE, MODE, GAIN, CAL
INHX, INLX)
–0.3
5.75
V
Open drain output current range (nFAULT, SDO)
0
5
mA
Continuous high-side gate pin voltage (GHX)
–2
VCP + 0.5
V
Pulsed 200 ns high-side gate pin voltage (GHX)
–5
VCP + 0.5
V
High-side gate voltage with respect to SHX (GHX)
–0.3
13.5
V
Continuous phase node pin voltage (SHX)
–2
VM + 2
V
Pulsed 200 ns phase node pin voltage (SHX)
–5
VM + 2
V
Continuous low-side gate pin voltage (GLX)
–1
13.5
V
Pulsed 200 ns low-side gate pin voltage (GLX)
–5
13.5
V
Gate pin source current (GHX, GLX)
Internally limited
Gate pin sink current (GHX, GLX)
A
Internally limited
A
Continuous shunt amplifier input pin voltage (SPX, SNX)
–1
1
V
Pulsed 200 ns shunt amplifier input pin voltage (SPX, SNX)
–2
2
V
Reference pin input voltage (VREF)
–0.3
5.75
V
Shunt amplifier output pin voltage range (SOX)
–0.3
VREF
V
Shunt amplifier output pin current range (SOX)
0
5
mA
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
UNIT
VVM
Power supply voltage range
6
38
V
VI
Logic level input voltage range
0
5.5
V
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Recommended Operating Conditions (continued)
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
UNIT
fPWM
Applied PWM signal (INHX, INLX)
200
(1)
IGATE_HS
High-side average gate drive current (GHX)
15
(1)
mA
IGATE_LS
Low-side average gate drive current (GLX)
15
(1)
mA
30
(1)
mA
mA
kHz
IDVDD
DVDD external load current
ISO
Shunt amplifier output current loading (SOX)
0
5
VOD
Open drain pull up voltage (nFAULT, SDO)
0
5.5
IOD
Open drain output current (nFAULT, SDO)
0
5
mA
TA
Operating ambient temperature
–40
125
°C
(1)
V
Power dissipation and thermal limits must be observed
6.4 Thermal Information
DRV8304
THERMAL METRIC (1)
RHA (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
35.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.6
°C/W
RθJB
Junction-to-board thermal resistance
14.9
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
14.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (DVDD, VM)
IVM
VM operating supply current
ENABLE = 1; INHX = 0 V; INLX = 0 V
5
7
mA
ENABLE = 0; VVM = 24 V; TA = 25°C
20
40
µA
100
µA
40
µs
IVMQ
VM sleep mode supply current
tRST
Reset pulse time
ENABLE = 0 V period to reset faults
tSLEEP
Sleep time
ENABLE = 0 V to driver tri-stated
tWAKE
Wake-up time
VVM > VUVLO; ENABLE = 3.3 V to output transition
VDVDD
Internal logic regulator voltage
IDVDD = 0 to 30 mA
ENABLE = 0, VVM = 24 V, TA = 125°C
(1)
15
200
µs
1
ms
2.9
3.3
3.6
V
7
10
11.5
V
CHARGE PUMP (CPH, CPL, VCP)
VM = 12 to 38 V; IVCP = 0 to 15 mA
VVCP
VCP operating voltage with
respect to VM
VM = 10 V; IVCP = 0 to 10 mA
6.5
7.5
9.5
V
VM = 8 V; IVCP = 0 to 5 mA
5
6
7.5
V
VM = 6 V; IVCP = 0 to 1 mA
3.8
4.3
6.5
V
V
LOGIC-LEVEL INPUTS (CAL, INHX, INLX, SCLK, SDI, nSCS)
VIL
Input logic low voltage
0
0.8
VIH
Input logic high voltage
1.5
5.5
VHYS
Input logic hysteresis
100
IIL
Input logic low current
VPIN (Pin Voltage) = 0 V
IIH
Input logic high current
VPIN (Pin Voltage) = 5 V
(1)
6
–1
V
mV
1
µA
100
µA
Specified by design and characterization data
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Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Pulldown Resistance to AGND
(CAL, INHX, INLX, SCLK,
SDI, nSCS)
RPD
TYP
MAX
100
UNIT
kΩ
LOGIC-LEVEL INPUTS (ENABLE)
VIL
Input logic low voltage
0
0.6
VIH
Input logic high voltage
1.5
5.5
V
VHYS
Input logic hysteresis
100
IIL
Input logic low current
VPIN (Pin Voltage) = 0 V
–10
10
µA
IIH
Input logic high current
VPIN (Pin Voltage) = 5 V
-5
5
µA
V
mV
FOUR-LEVEL INPUTS (GAIN, MODE)
VI1
Input mode 1 voltage
Tied to AGND
VI2
Input mode 2 voltage
45 kΩ ± 5% to AGND
VI3
Input mode 3 voltage
Hi-Z
VI4
Input mode 4 voltage
Tied to DVDD
0
V
1.2
V
2
V
3.3
V
SEVEN-LEVEL INPUTS (IDRIVE, VDS)
VI1
Input mode 1 voltage
Tied to AGND
VI2
Input mode 2 voltage
18 kΩ ± 5% to AGND
VI3
Input mode 3 voltage
75 kΩ ± 5% to AGND
VI4
Input mode 4 voltage
Hi-Z
VI5
Input mode 5 voltage
VI6
VI7
0
V
0.5
V
1.1
V
1.65
V
75 kΩ ± 5% to DVDD
2.2
V
Input mode 6 voltage
18 kΩ ± 5% to DVDD
2.8
V
Input mode 7 voltage
Tied to DVDD
3.3
V
OPEN-DRAIN OUTPUTS (nFAULT, SDO)
VOL
Output logic low voltage
IOD = 2 mA
IOZ
Output logic high current
VOD = 5 V
–1
0.1
V
1
µA
GATE DRIVERS (GHX, GLX, SHX)
VVM = 12 to 38 V; IHS_GATE = 0 to 15 mA
(1)
VGHS
VGSL
(1)
High-side VGS gate drive
(gate-to-source)
VVM = 10 V; IHS_GATE = 0 to 10 mA
tDEAD
Output dead time (HW Device)
tDRIVE
Peak gate drive time (SPI
Device)
tDRIVE
Peak gate drive time (HW
Device)
11.5
6.5
7.5
8.5
5
6
7
VVM = 6 V; IHS_GATE = 0 to 1 mA
3.8
4.3
6.5
VVM = 12 to 38 V; ILS_GATE = 0 to 15 mA
7.5
10
12.5
5.5
7.5
9.5
3.5
6
8.5
3
4.3
6.5
VVM = 6 V; ILS_GATE = 0 to 1 mA
Output dead time (SPI Device)
10
VVM = 8 V; IHS_GATE = 0 to 5 mA
Low-side VGS gate drive (gate- VVM = 10 V; ILS_GATE = 0 to 10 mA
to-source)
VVM = 8 V; ILS_GATE = 0 to 5 mA
tDEAD
7
DEAD_TIME = 00b
40
DEAD_TIME = 01b
120
DEAD_TIME = 10b
200
DEAD_TIME = 11b
400
120
TDRIVE = 00b
500
TDRIVE = 01b
1000
TDRIVE = 10b
2000
TDRIVE = 11b
4000
4000
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V
V
ns
ns
ns
ns
7
DRV8304
SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
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Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
Peak source gate current
(high-side and low-side) (SPI
Device)
IDRIVEP
Peak source gate current
(high-side and low-side) (HW
Device)
IDRIVEP
Peak sink gate current (highside and low-side) (SPI
Device)
IDRIVEN
TEST CONDITIONS
MIN
IDRIVEP_HS or IDRIVEP__LS = 000b
15
IDRIVEP_HS or IDRIVEP__LS = 001b
15
IDRIVEP_HS or IDRIVEP__LS = 010b
45
IDRIVEP_HS or IDRIVEP__LS = 011b
60
IDRIVEP_HS or IDRIVEP__LS = 100b
90
IDRIVEP_HS or IDRIVEP__LS = 101b
105
IDRIVEP_HS or IDRIVEP__LS = 110b
135
IDRIVEP_HS or IDRIVEP__LS = 111b
150
IDRIVE tied to AGND
15
IDRIVE 18 kΩ (±5%) to AGND
45
IDRIVE 75 kΩ (±5%) to AGND
60
IDRIVE Hi-Z ( > 500 kΩ to AGND)
Peak sink gate current (highside and low-side) (HW
Device)
MAX
105
IDRIVE 18 kΩ (±5%) to DVDD
135
IDRIVE tied to DVDD
150
IDRIVEN_HS or IDRIVEN_LS = 000b
30
IDRIVEN_HS or IDRIVEN_LS = 001b
30
IDRIVEN_HS or IDRIVEN_LS = 010b
90
IDRIVEN_HS or IDRIVEN_LS = 011b
120
IDRIVEN_HS or IDRIVEN_LS = 100b
180
IDRIVEN_HS or IDRIVEN_LS = 101b
210
IDRIVEN_HS or IDRIVEN_LS = 110b
270
IDRIVEN_HS or IDRIVEN_LS = 111b
300
UNIT
mA
90
IDRIVE 75 kΩ (±5%) to DVDD
IDRIVE tied to AGND
IDRIVEN
TYP
mA
mA
30
IDRIVE 18 kΩ (±5%) to AGND
90
IDRIVE 75 kΩ (±5%) to AGND
120
IDRIVE Hi-Z ( > 500 kΩ to AGND)
180
IDRIVE 75 kΩ (±5%) to DVDD
210
IDRIVE 18 kΩ (±5%) to DVDD
270
IDRIVE tied to DVDD
300
Source current after tDRIVE
15
Sink current after tDRIVE
30
mA
IHOLD
FET holding current
mA
ISTRONG
FET hold-off strong pulldown
GLX pull-down current during GHX tDRIVE period or
vice-versa
300
ROFF
FET gate hold-off resistor
GHX to SHX and GLX to PGND
150
tPD
Propagation delay
INHX/INLX tansition to GHX/GLX transition
180
250
mA
kΩ
ns
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, VREF)
GCSA
GCSA
8
Amplifier gain (SPI Device)
Amplifier gain (HW Device)
CSA_GAIN = 00b, VREF = 3.3 to 5 V
4.85
5
5.15
CSA_GAIN = 01b, VREF = 3.3 to 5 V
9.7
10
10.3
CSA_GAIN = 10b, VREF = 3.3 to 5 V
19.4
20
20.6
CSA_GAIN = 11b, VREF = 3.3 to 5 V
38.8
40
41.2
Tied to AGND, VREF = 3.3 to 5 V
4.85
5
5.15
9.7
10
10.3
Hi-Z, VREF = 3.3 to 5 V
19.4
20
20.6
Tied to DVDD, VREF = 3.3 to 5 V
38.8
40
41.2
45 kΩ ± 5% to AGND, VREF = 3.3 to 5 V
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V/V
V/V
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Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
tSET
(1)
Settling time to ±1%, 30 pF
VSP, COM
(1)
TEST CONDITIONS
260
STEP on SOX = 0.5 V; GCSA = 10 V/V, VREF = 3.3
to 5 V
400
STEP on SOX = 0.5 V; GCSA = 20 V/V, VREF = 3.3
to 5 V
700
STEP on SOX = 0.5 V; GCSA = 40 V/V, VREF = 3.3
to 5 V
1550
Common-mode input range
VSP = VSN = 0 V, GCSA = 10, VREF = 3.3 V ± 10%
VDRIFT
Input offset error
(1)
VLINEAR
(1)
VBIAS
Drift offset
MAX
UNIT
ns
–0.5
0.5
–5
5
mV
V
–2.5
2.5
mV
VSP = VSN = 0 V, GCSA = 20, VREF = 3.3 V ± 10%
–1.5
1.5
mV
VSP = VSN = 0 V, GCSA = 40, VREF = 3.3 V ± 10%
–1.25
1.25
mV
–7
7
mV
VSP = VSN = 0 V, GCSA = 5, VREF = 5 V ± 10%
VSP = VSN = 0 V, GCSA = 10, VREF = 5 V ± 10%
–3.5
3.5
mV
VSP = VSN = 0 V, GCSA = 20, VREF = 5 V ± 10%
–2.25
2.25
mV
VSP = VSN = 0 V, GCSA = 40, VREF = 5 V ± 10%
–1.5
1.5
mV
VSP = VSN = 0 V
SOX output voltage linear
range
SOX output voltage bias (SPI
Device)
TYP
STEP on SOX = 0.5 V; GCSA = 5 V/V, VREF = 3.3 to
5V
VSP = VSN = 0 V, GCSA = 5, VREF = 3.3 V ± 10%
VOFF
MIN
10
0.25
VSP = VSN = 0 V, VREF_DIV = 0b
VVREF –
0.3
VSP = VSN = 0 V, VREF_DIV = 1b
VVREF/2
VVREF/2
VBIAS
SOX output voltage bias (HW
Device)
VSP = VSN = 0 V
IBIAS
SPX/SNX negative input bias
current
VSP = VSN = 0 V
VREFUV
VREF undervoltage
IVREF
VREF input current
µV/°C
VVREF –
0.25
V
V
200
2.6
VREF = 5.0 V
1
V
µA
V
2
mA
PROTECTION CIRCUITS
VM falling, UVLO report
5.4
5.8
VM rising, UVLO recovery
5.6
6
VUVLO
VM undervoltage lockout
VUVLO_HYS
VM undervoltage hysteresis
tUVLO_DEG
(1)
VM undervoltage deglitch time VM falling, UVLO report
VCPUV
Charge pump undervoltage
VGS_CLAMP
VDS_OCP
Gate drive clamping voltage
VDS overcurrent trip voltage
(SPI Device)
Rising to falling threshold
With respect to VM
Positive clamping voltage
200
mV
10
µs
2.4
10.5
V
15
Negative clamping voltage
–0.6
VDS_LVL = 000b
0.15
VDS_LVL = 001b
0.24
VDS_LVL = 010b
0.4
VDS_LVL = 011b
0.51
VDS_LVL = 100b
0.6
VDS_LVL = 101b
0.9
VDS_LVL = 110b
1.8
VDS_LVL = 111b
Disabled
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Electrical Characteristics (continued)
at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER
VDS_OCP
VDS overcurrent trip voltage
(HW Device)
TEST CONDITIONS
MIN
TYP
VDS tied to AGND
0.15
VDS 18 kΩ (±5%) to AGND
0.24
VDS 75 kΩ (±5%) to AGND
0.4
VDS Hi-Z ( > 500 kΩ to AGND)
0.6
VDS 75 kΩ (±5%) to DVDD
0.9
VDS 18 kΩ (±5%) to DVDD
VSEN_OCP
VSENSE overcurrent trip
voltage (HW Device)
tOCP_DEG
VDS and VSENSE overcurrent
deglitch time
tRETRY
Overcurrent retry time (SPI
Device)
tRETRY
Overcurrent retry time (HW
Device)
(1)
TOTW
TOTSD
THYS
(1)
(1)
V
Disabled
SEN_LVL = 00b
VSENSE overcurrent trip
voltage (SPI Device)
UNIT
1.8
VDS tied to DVDD
VSEN_OCP
MAX
0.25
SEN_LVL = 01b
0.5
SEN_LVL = 10b
0.75
SEN_LVL = 11b
1
V
1
V
4.5
µs
TRETRY = 0b
4
ms
TRETRY = 1b
500
µs
4
ms
Thermal warning temperature
Die temperature (Tj)
120
140
°C
Thermal shutdown
temperature
Die temperature (Tj)
150
170
°C
Thermal hysteresis
Die temperature (Tj)
20
°C
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
SPI (nSCS, SCLK, SDI, SDO)
tREADY
SPI ready after after enable
tCLK
SCLK minimum period
200
ns
tCLKH
SCLK minimum high time
100
ns
tCLKL
SCLK minimum low time
100
ns
tSU_SDI
SDI input data setup time
40
ns
tHD_SDI
SDI input data hold time
60
tDLY_SDO
SDO output data delay time
tSU_nSCS
nSCS input setup time
100
ns
tHD_nSCS
nSCS input hold time
100
ns
tHI_nSCS
nSCS minimum high time before active low
600
ns
tEN_nSCS
nSCS enable time
nSCS low to SDO out of high impedance
20
ns
tDIS_nSCS
nSCS disable delay time
nSCS high to SDO high impedance
20
ns
10
VM > UVLO, ENABLE = 3.3 V
1
ns
SCLK high to SDO valid
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ms
60
ns
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tHI_nSCS
tSU_nSCS
tHD_nSCS
tCLK
tCLKH
X
tCLKL
MSB
LSB
tSU_SDI
Z
X
tHD_SDI
MSB
tEN_nSCS
LSB
Z
tDIS_nSCS
tDLY_SDO
Figure 1. SPI Slave-Mode Timing Diagram
8
8
7
7
6
6
Supply Current (mA)
Supply Current (mA)
6.7 Typical Characteristics
5
4
3
2
TA = 40qC
TA = 25qC
TA = 125qC
1
5
10
15
20
25
Supply Voltage (V)
30
35
4
3
2
0
-40
40
-20
0
D001
Figure 2. Supply Current Over Supply Voltage
20
40
60
80
Temperature (qC)
100
120
140
D002
Figure 3. Supply Current Over Temperature
100
100
TA = 40qC
TA = 25qC
TA = 125qC
90
80
90
80
70
Sleep Current (PA)
Sleep Current (PA)
VVM = 6 V
VVM = 12 V
VVM = 24 V
VVM = 38 V
1
0
0
5
60
50
40
30
70
60
50
40
30
20
20
10
10
0
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
VVM = 6 V
VVM = 12 V
VVM = 24 V
VVM = 38 V
0
-40
D003
Figure 4. Sleep Current Over Supply Voltage
-20
0
20
40
60
80
Temperature (qC)
100
120
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D004
Figure 5. Sleep Current Over Temperature
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3.5
3.5
3.4
3.4
3.3
3.3
3.2
3.2
DVDD Voltage (V)
DVDD Voltage (V)
Typical Characteristics (continued)
3.1
3
2.9
2.8
2.7
3
2.9
2.8
2.7
TA = 40qC
TA = 25qC
TA = 125qC
2.6
3.1
TA = 40qC
TA = 25qC
TA = 125qC
2.6
2.5
2.5
0
5
10
15
20
25
Supply Voltage (V)
30
35
40
0
IDVDD = 0 mA
10
10
8
8
VCP Voltage (V)
VCP Voltage (V)
12
6
4
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 12 V
2
30
35
40
D006
6
9
Load Current (mA)
12
6
4
VVM = 6 V
VVM = 8 V
VVM = 10 V
VVM = 12 V
2
0
15
0
-40
-20
D007
Figure 8. VCP Voltage Over Load
12
15
20
25
Supply Voltage (V)
Figure 7. DVDD Voltage Over Supply Voltage
12
3
10
IDVDD = 30 mA
Figure 6. DVDD Voltage Over Supply Voltage
0
5
D005
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0
20
40
60
80
Temperature (qC)
100
120
140
D008
Figure 9. VCP Voltage Over Temperature
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7 Detailed Description
7.1 Overview
The DRV8304 device is an integrated 6-V to 38-V gate driver for 3-phase motor-drive applications. The device
reduces system component count, cost, and complexity by integrating three independent half-bridge gate drivers,
charge pump, and linear regulator for the high-side and low-side gate-driver supply voltages. A standard serial
peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault
diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for
configuring the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 150mA source, 300-mA sink peak currents with a 15-mA average output current. The high-side gate-drive supply
voltage is generated using a doubler charge-pump architecture that regulates the VCP output to VVM + 10 V. The
low-side gate-drive supply voltage is generated using a linear regulator from the VM power supply that regulates
to 10 V. A smart gate-drive (SGD) architecture provides the ability to dynamically adjust the output gate-drive
current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This feature
allows for the removal of external gate-drive resistors and diodes reducing bill of materials (BOM) component
count, cost, and printed circuit board (PCB) area. The architecture also uses an internal state machine to protect
against gate-drive short-circuit events, control the half-bridge dead time, and protect against dV/dt parasitic
turnon of the external power MOSFET.
The DRV8304 device integrates three, bidirectional current-shunt amplifiers for monitoring the current level
through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier
can be adjusted through the SPI (DRV8304S) or hardware (DRV8304H) interface with the SPI providing
additional flexibility to adjust the output bias point.
In addition to the high level of device integration, the DRV8304 device provides a wide range of integrated
protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump
undervoltage lockout (CPUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and
overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed
information available in the SPI registers on the SPI device version.
The DRV8304 device is available in 0.5-mm pin pitch, VQFN surface-mount packages. The VQFN package size
is 6 mm × 6 mm.
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7.2 Functional Block Diagram
VM
1 …F
bulk
+
Power
1 …F
VCP
VCP
CPH
22 nF
HS
VCP
Charge
Pump
1 …F
AGND
GHA
SHA
CPL
DVDD
HS
VGLS
LS
30 mA
VM
VDRAIN
VM
LS
GLA
3.3-V LDO
Gate Driver
VGLS LDO
PGND
ENABLE
VM
VCP
INHA
HS
HS
GHB
INLA
SHB
Digital
Core
INHB
VGLS
LS
LS
GLB
INLB
Gate Driver
INHC
Control
Inputs
INLC
MODE
VM
VCP
IDRIVE
HS
VDS
HS
GHC
SHC
GAIN
VGLS
CAL
LS
GLC
Gate Driver
Outputs
nFAULT
LS
SPC
RSENSE
AV
VCC
SNC
VREF
SPB
AV
0.1 µF
SOC
SPA
SOB
SOA
RSENSE
SNB
Output Offset
Bias
AV
RSENSE
SNA
CAL
PPAD
Figure 10. Block Diagram for DRV8304H
14
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Functional Block Diagram (continued)
VM
1 …F
bulk
+
VM
Power
1 …F
VCP
VCP
CPH
22 nF
HS
VCP
Charge
Pump
1 …F
AGND
GHA
SHA
LS
DVDD
HS
VGLS
CPL
30 mA
VM
VDRAIN
VM
LS
GLA
3.3-V LDO
Gate Driver
VGLS LDO
PGND
ENABLE
VM
VCP
INHA
HS
HS
GHB
INLA
SHB
Digital
Core
INHB
INLB
VGLS
LS
Control
Inputs
LS
GLB
Gate Driver
INHC
INLC
VM
VCP
nFAULT
Outputs
HS
HS
GHC
SHC
VGLS
SCLK
LS
SPI
LS
GLC
SDI
Gate Driver
SDO
SPC
nSCS
RSENSE
AV
VCC
SNC
VREF
SPB
0.1 µF
AV
RSENSE
SNB
SOC
SPA
SOB
SOA
AV
Output Offset
Bias
RSENSE
SNA
CAL
PPAD
Figure 11. Block Diagram for DRV8304S
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7.3 Feature Description
Table 1 lists the recommended values of the external components for the gate driver.
Table 1. DRV8304 Gate-Driver External Components
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
PGND
X5R or X7R, 0.1-µF, VM-rated capacitor
CVM2
VM
PGND
≥ 10 µF, VM-rated capacitor
CVCP
VCP
VM
X5R or X7R, 16-V, 1-µF capacitor
CSW
CPH
CPL
X5R or X7R, 22-nF, VM-rated capacitor
CDVDD
DVDD
AGND
X5R or X7R, 1-µF, 6.3-V capacitor
RnFAULT
(1)
VCC
(1)
nFAULT
5.1-kΩ, Pullup resistor
RSDO
VCC (1)
SDO
5.1-kΩ, Pullup resistor, DRV8304 SPI device
RIDRIVE
IDRIVE
AGND or DVDD
DRV8304 hardware interface
RVDS
VDS
AGND or DVDD
DRV8304 hardware interface
RMODE
MODE
AGND or DVDD
DRV8304 hardware interface
RGAIN
GAIN
AGND or DVDD
DRV8304 hardware interface
CVREF
VREF
AGND or DGND
X5R or X7R, 0.1-µF, VREF-rated capacitor (Optional)
RASENSE
SPA
SNA and PGND
Sense shunt resistor based on current regulation limit
RBSENSE
SPB
SNB and PGND
Sense shunt resistor based on current regulation limit
RCSENSE
SPC
SNC and PGND
Sense shunt resistor based on current regulation limit
The VCC pin is not a pin on the DRV8304 device, but a VCC supply voltage pullup is required for the open-drain output nFAULT and
SDO. These pins can also be pulled up to DVDD.
7.3.1 3-Phase Smart Gate Drivers
The DRV8304 device integrates three, half-bridge gate drivers, each capable of driving high-side and low-side Nchannel power MOSFETs. A doubler charge pump provides the proper gate-bias voltage to the high-side
MOSFET across a wide operating-voltage range in addition to providing 100% duty-cycle support. An internal
linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge gate drivers can be
used in combination to drive a 3-phase motor or separately to drive other types of loads.
The DRV8304 device implements a smart gate-drive architecture which allows the user to dynamically adjust the
gate drive current without requiring external gate current limiting resistors. Additionally, this architecture provides
a variety of protection features for the external MOSFETs including automatic dead-time insertion, parasitic dV/dt
gate turnon prevention, and gate-fault detection.
7.3.1.1 PWM Control Modes
The DRV8304 device provides four different PWM-control modes to support various commutation and control
methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during
operation of the power MOSFETs.
7.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 2.
Table 2. 6x PWM Mode Truth Table
16
INLx
INHx
GLx
GHx
SHx
0
0
L
L
Hi-Z
0
1
L
H
H
1
0
H
L
L
1
1
L
L
Hi-Z
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7.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 3.
Table 3. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
0
X
L
L
Hi-Z
1
0
H
L
L
1
1
L
H
H
7.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV8304 device uses 6-step block commutation tables that are stored internally. This feature
allows for a 3-phase BLDC motor to be controlled using a single PWM sourced from a simple controller. The
PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode normally
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on the SPI device. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction
of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin
low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.
Table 4. Synchronous 1x PWM Mode
LOGIC AND HALL INPUTS
STATE
INHC = 0
GATE-DRIVE OUTPUTS
INHC = 1
PHASE A
INLA
INHB
INLB
INLA
INHB
INLB
GHA
PHASE B
GLA
GHB
PHASE C
GLB
GHC
GLC
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
!PWM
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
!PWM
L
H
B→C
2
1
0
0
0
1
1
PWM
!PWM
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
!PWM
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
!PWM
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
!PWM
C→A
6
0
1
0
1
0
1
L
H
PWM
!PWM
L
L
B→A
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Table 5. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
INHC = 0
STATE
GATE-DRIVE OUTPUTS
INHC = 1
PHASE A
INLA
INHB
INLB
INLA
INHB
INLB
PHASE B
GHA
GLA
GHB
PHASE C
GLB
GHC
GLC
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
L
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
L
L
H
B→C
2
1
0
0
0
1
1
PWM
L
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
L
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
L
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
L
C→A
6
0
1
0
1
0
1
L
H
PWM
L
L
L
B→A
Figure 12 and Figure 13 show the different possible configurations in 1x PWM mode.
DRV8304
DRV8304
INHA
MCU_PWM
M
PWM
INHA
MCU_PWM
INLA
MCU_GPIO
INLA
INHB
MCU_GPIO
STATE1
STATE2
STATE2
MCU_GPIO
DIR
INLC
MCU_GPIO
INLC
STATE0
STATE1
INHC
INHC
MCU_GPIO
H
H
INLB
INLB
MCU_GPIO
M
STATE0
INHB
MCU_GPIO
PWM
H
DIR
nBRAKE
nBRAKE
Figure 13. 1x PWM—Hall Sensor
Figure 12. 1x PWM—Simple Controller
7.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This
control mode allows for the DRV8304 device to drive separate high-side and low-side loads with each halfbridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side
switches. In this mode, if the system is configured in a half-bridge configuration, simultaneously turning on both
the high-side and low-side MOSFETs causes shoot-through current in external MOSFETs and can cause them
to damage.
Table 6. Independent PWM Mode Truth Table
18
INLx
INHx
GLx
0
0
L
L
0
1
L
H
1
0
H
L
1
1
H
H
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Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using the monitors if
both the high-side and low-side gate drivers of one half-bridge are split and being used is not possible. In this
case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in
Figure 14.
Disable
VDS
+
±
VM
VDRAIN
VCP
GHx
HS
INHx
Load
SHx
VGLS
INLx
GLx
LS
Load
SPx
Gate Driver
Disable
VDS
+
±
Figure 14. Independent PWM High-Side and Low-Side Drivers
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is
still possible. Connect the SHx pin as shown in Figure 15 or Figure 16. The unused gate driver and the
corresponding input can be left disconnected.
VDS
+
±
VDS
VM
+
±
VCP
VCP
GHx
GHx
INHx
HS
HS
INHx
Load
SHx
SHx
INLx
VM
VDRAIN
VDRAIN
VGLS
VGLS
INLx
GLx
GLx
LS
LS
Load
SPx
Gate Driver
SPx
Gate Driver
+
VDS ±
+
VDS ±
Figure 15. Single High-Side Driver
Figure 16. Single Low-Side Driver
7.3.1.2 Device Interface Modes
The DRV8304 device supports two different interface modes (SPI and hardware) to allow the end application to
design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different
versions to be pin-to-pin compatible. This allows for application designers to evaluate with one interface version
and potentially switch to another with minimal modifications to their design.
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7.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI device supports a serial communication bus that allows for an external controller to send and receive
data with the DRV8304 device. This bus allows for the external controller to configure device settings and read
detailed fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins.
• The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated on
SDI and SDO.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV8304 device.
For more information on the SPI, see the SPI Communication section.
7.3.1.2.2 Hardware Interface
The hardware interface device converts the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This option allows for the application designer to configure the most commonly used device
settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This configuration
removes the requirement for a SPI bus from the external controller. General fault information can still be obtained
through the nFAULT pin.
• The GAIN pin configures the current shunt-amplifier gain.
• The IDRIVE pin configures the gate-drive current strength.
• The MODE pin configures the PWM control mode.
• The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Pin Diagrams section.
DVDD
RGAIN
SCLK
SPI
DVDD
GAIN
DVDD
Hardware
Interface
DVDD
IDRIVE
SDI
DVDD
VCC
RPU
MODE
SDO
DVDD
VDS
nSCS
RVDS
Figure 18. Hardware Interface
Figure 17. SPI
7.3.1.3 Gate Driver Voltage Supplies
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM
voltage supply input. The charge pump allows the gate driver to properly bias the high-side MOSFET gate with
respect to the source across a wide input supply-voltage range. The charge pump is regulated to maintain a fixed
output voltage of VVM + 10 V and supports an average output current of 15 mA. When VVM is less than 12 V, the
charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V when unloaded. The charge
pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions. The charge pump
requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VM and VCP pins to act as the storage
capacitor. Additionally, a X5R or X7R, 22-nF, VM-rated ceramic capacitor is required between the CPH and CPL
pins to act as the flying capacitor.
20
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VM
VM
1 …F
VCP
CPH
VM
22 nF
Charge
Pump
Control
CPL
Figure 19. Charge Pump Architecture
The low-side gate-drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The linear regulator allows the gate driver to properly bias the low-side MOSFET gate with respect to
ground. The linear regulator output is fixed at 10 V and supports an output current of 15 mA.
7.3.1.4 Smart Gate-Drive Architecture
The DRV8304 gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and lowside drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the IDRIVE: MOSFET Slew-Rate Control section and TDRIVE: MOSFET Gate Drive
Control section. Figure 20 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters of
the external power MOSFET used in the system and the desired rise and fall times (see the Application and
Implementation section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
INLx
VM
GHx
Level
Shifters
150 k
SHx
Logic
VGLS
GLx
Level
Shifters
150 k
PGND
Figure 20. Gate Driver Block Diagram
7.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode
recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics
in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are predominately
determined by the rate of gate charge (or gate current) delivered during the MOSFET Qgd or Miller charging
region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external
power MOSFETs.
IDRIVE allows the DRV8304 device to dynamically switch between gate drive currents either through a register
setting on the SPI device or the IDRIVE pin on hardware interface device. The SPI and hardware devices
provide 7 IDRIVE settings ranging from 15-mA to 150-mA source and 30-mA to 300-mA sink. The gate-drive
current setting is delivered to the gate during the turnon and turnoff of the external power MOSFET for the tDRIVE
duration. After the MOSFET turnon or turnoff, the gate driver switches to a smaller hold current (IHOLD) to improve
the gate driver efficiency. Additional details on the IDRIVE settings are described in the Register Maps section for
the SPI device and in the Pin Diagrams section for the hardware interface device.
7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead-time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is the period of
time between the switching of the external high-side and low-side MOSFETs to ensure that they do not cross
conduct and cause shoot-through. The DRV8304 device uses the VGS voltage monitors to measure the MOSFET
gate-to-source voltage and determine the proper time to switch instead of relying on a fixed time value. This
feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and
variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable
through the registers on the SPI device.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown current (ISTRONG) on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown happens for the tDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
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The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair
of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it begins to monitor the gate voltage of the external MOSFET. If,
at the end of the tDRIVE period, the VGS voltage has not reached the proper threshold, the gate driver reports a
fault. To ensure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time
required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will
terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Register Maps section for SPI device and in the Pin Diagrams section for hardware interface
device.
NOTE
If the mode is set to independent PWM mode, then the IDRIVE current is automatically set
for the IHOLD period.
Figure 21 shows an example of the TDRIVE state machine in operation.
VINHx
tPD
tPD
VINLx
tDEAD
tDEAD
VGHx
IDRIVE
ISTRONG
IDRIVE
IHOLD
IHOLD
IGHx
IHOLD
ISTRONG
IHOLD
IHOLD
tDEAD
tDEAD
VGLx
IHOLD
IHOLD
IHOLD
ISTRONG
IDRIVE
tDRIVE
IHOLD
IDRIVE
ISTRONG
IGLx
IHOLD
tDRIVE
Figure 21. TDRIVE State Machine
7.3.1.4.3 Gate Drive Clamp
A clamping structure limits the gate-drive output voltage to the VGS,CLAMP voltage to help protect the external
high-side MOSFETs from gate overvoltage damage. The positive voltage clamp is realized using a series of
diodes. The negative voltage clamp uses the body diodes of the internal pulldown gate driver as shown in
Figure 22.
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VGHS
VM
IREVERSE
GHx
VGS > VCLAMP
ICLAMP
SHx
Predriver
VGS negative
VGLS
GLx
RSENSE
PGND
Figure 22. Gate Drive Clamp
7.3.1.4.4 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time comprises three parts consisting of the digital input deglitcher delay, the digital propagation
delay, and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead-time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
In order for the output to change state during normal operation, one MOSFET must first be turned off. The
MOSFET gate is ramped down according to the IDRIVE setting, and the observed propagation delay ends when
the MOSFET gate falls below the threshold voltage.
7.3.1.4.5 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins and the low-side VDS
monitors measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP
pins to the common ground point of the external half-bridges.
For the SPI device, the reference point of the low-side VDS monitor can be changed between the SPx and SNx
pins if desired with the LS_REF register setting.
24
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The VVDS_OCP threshold is programmable from 0.15 V to 1.8 V. Additional information on the VDS monitor levels
are described in the Register Maps section for the SPI device and in the Pin Diagrams section hardware
interface device.
DRV8304
High-Side VDS OCP Monitor
VDRAIN
+
VM
±
VDS,OCP
GHx
+
±
SHx
Low-Side VDS OCP Monitor
GLx
+
±
SPX
VDS,OCP
+
0
1
±
RSENSE
SNX
LS_REF
(DRV8304S only)
Figure 23. DRV8304 VDS Monitors
7.3.1.4.6 VDRAIN Sense Pin
The DRV8304 device provides a separate sense pin for the common point of the high-side MOSFET drain. This
pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors (VDRAIN) and the power supply
(VM) to remain separate and prevent noise on the VDRAIN sense line. This separation also allows for a small
filter to be implemented on the gate driver supply (VM) or to insert a boost converter to support lower voltage
operation if desired. Care must still be taken when the filter or separate supply is designed because the VM
supply is still the reference point for the VCP charge pump that supplies the high-side gate drive voltage (VGSH).
The VM supply must not drift to far from the VDRAIN supply to avoid violating the VGS voltage specification of the
external power MOSFETs.
7.3.2 DVDD Linear Voltage Regulator
A 3.3-V, 30-mA linear regulator is integrated into the DRV8304 device and is available for use by external
circuitry. This regulator can provide the supply voltage for a low-power microcontroller or other low-current
supporting circuitry. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or
X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The DVDD nominal, no-load output voltage is 3.3 V. When the DVDD load current exceeds 30 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than 30
mA.
VM
REF
+
±
DVDD
3.3 V, 30 mA
maximum
1 …F
AGND
Figure 24. DVDD Linear Regulator Block Diagram
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Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
P
VVM VDVDD u IDVDD
(1)
For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 2.
P 24 V 3.3 V u 20 mA 414 mW
(2)
7.3.3 Pin Diagrams
Figure 25 shows the input structure for the logic-level pins, INHx, INLx, CAL, nSCS, SCLK, and SDI. The input
can be driven with a voltage or external resistor.
DVDD
STATE
RESISTANCE
INPUT
VIH
Tied to DVDD
Logic High
VIL
Tied to AGND
Logic Low
RPD
Figure 25. Logic-Level Input Pin Structure (INHx, INLx, CAL, nSCS, SCLK, and SDI)
Figure 26 shows the input structure for the logic-level ENABLE pin. The input can be driven with a voltage or
external resistor. The ENABLE pin is latched when the device is powered-up.
5V
RPU2
Latch
VEXT
STATE
RESISTANCE
INPUT
RPU1
VIH
Tied to VEXT
Logic High
VIL
Tied to AGND
Logic Low
Figure 26. Logic-Level Input Pin Structure (ENABLE)
26
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Figure 27 shows the structure of the four-level input pins, MODE and GAIN, on the hardware interface device.
The input can be set with an external resistor. The MODE and GAIN pins are latched when the device is
powered-up.
MODE
GAIN
Independent
40 V/V
1x PWM
20V/V
3x PWM
10 V/V
6x PWM
5 V/V
DVDD
STATE
RESISTANCE
VI4
Tied to DVDD
VI3
Hi-Z (>500 kŸ WR
AGND)
DVDD
+
RPU
VI2
47 NŸ “5%
to AGND
VI1
Tied to AGND
±
+
RPD
±
+
±
Figure 27. Four-Level Input Pin Structure (MODE and GAIN)
Figure 28 shows the structure of the seven-level input pins, IDRIVE and VDS, on the hardware interface device.
The input can be set with an external resistor. The IDRIVE and VDS pins are latched when the device is
powered-up.
IDRIVE
VDS
150/300 mA
Disabled
135/270 mA
1.8 V
105/210 mA
0.9 V
90/180 mA
0.6 V
60/120 mA
0.4 V
45/90 mA
0.24 V
15/30 mA
0.15 V
+
STATE
RESISTANCE
VI7
Tied to DVDD
VI6
18 k ± 5%
to DVDD
VI5
75 k ± 5%
to DVDD
VI4
Hi-Z (>500 kŸ
to AGND)
VI3
75 k ± 5%
to AGND
VI2
18 NŸ “5%
to AGND
VI1
±
DVDD
DVDD
+
±
RPU
+
±
RPD
Latch
DVDD
+
±
+
Tied to AGND
±
+
±
Figure 28. Seven-Level Input Pin Structure (IDRIVE and VDS)
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Figure 29 shows the structure of the open-drain output pin, nFAULT. The open-drain output requires an external
pullup resistor to function properly.
DVDD
RPU
STATE
STATUS
No Fault
Inactive
OUTPUT
Fault
Active
Active
Inactive
Figure 29. Open-Drain Output Pin Structure
7.3.4 Low-Side Current-Shunt Amplifiers
The DRV8304 device integrates three, high-performance low-side current-shunt amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such
as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin
(VREF).
7.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8304 outputs an analog voltage equal to the voltage across the SPx and SNx pins
multiplied by the gain setting (GCSA) as shown in Figure 30. The gain setting is adjustable between four different
levels (5 V/V, 10 V/V, 20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.
VVREF
VSOx
2
I
GCSA u RSENSE
(3)
R2
R3
R4
R5
R6
SOx
I
R1
VCC
SPx
±
R1
VREF
+
0.1 …F
R2
RSENSE
SNx
½
+
R3
±
R4
R5
Figure 30. Bidirectional Current-Sense Configuration
28
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Figure 31 and Figure 32 show the detail of the amplifier operational range. In bi-directional operation, the
amplifier output for 0-V input is set at VREF / 2. Any change in the differential input results in a corresponding
change in the output times the CSA_GAIN factor. The amplifier has a defined linear region in which it can
maintain operation.
SO (V)
VREF
VREF / 2
VLINEAR
SP ± SN (V)
Figure 31. Bidirectional Current-Sense Output
I
SP
SO
R
AV
SN
SO
VREF
SP ± SN
±0.3 V
VVREF ± 0.25 V
±I × R
VSO(range±)
VSO(off)max
VOFF,
VVREF / 2
VDRIFT
0V
VSO(off)min
VSO(range+)
I×R
0.3 V
0.25 V
0V
Figure 32. Bidirectional Current Sense Regions
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7.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8304 SPI device, use the VREF_DIV bit to remove the VREF divider. In this case the shunt amplifier
operates unidirectionally and the SOx outputs an analog voltage equal to the voltage across the SPx and SNx
pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the current through the shunt resistor.
I
VVREF
0.3
VSOX
GCSA u RSENSE
(4)
R2
R3
R4
R5
R6
SOx
I
R1
SPx
±
R1
RSENSE
+
SNx
VCC
R2
0.3 V
VREF
+
0.1 …F
-
+
R3
±
R4
R5
Figure 33. Unidirectional Current-Sense Configuration
Figure 34 and Figure 35 show the detail of the amplifier operational range. In unidirectional operation, the
amplifier output for 0-V input is set at VREF – 0.3 V. In this operating mode the amplifier output only responds to
a positive current through the shunt resistor. The amplifier has a defined linear region in which it can maintain
operation.
SO (V)
VREF
VVREF ± 0.3 V
VLINEAR
SP ± SN (V)
Figure 34. Unidirectional Current-Sense Output
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I
SP
SO
R
AV
SN
SO
VREF
VVREF ± 0.25 V
VSO(off)max
VOFF,
VVREF ± 0.3 V
SP ± SN
VDRIFT
0V
VSO(off)min
VSO(range)
I×R
0.3 V
0.25 V
0V
Figure 35. Unidirectional Current-Sense Regions
7.3.4.3 Offset Calibration
The DRV8304 device provides an auto calibration feature to minimize the amplifier input offset on power up or
during an ENABLE reset pulse to account for temperature and device variation. Auto calibration is performed on
both the hardware and SPI device options. The auto calibration begins immediately after the VREF pin crosses
the minimum operational VREF voltage and completes in several µs (max 500 µs). During auto calibration, the
inputs to the amplifier are disconnected from SPX and SNX pin and shorted internally. After auto calibration the
amplifiers are ready for operation.
For the SPI device option, auto calibration can also be performed during run time by setting the AUTOCAL bit. If
the AUTOCAL bit is already set once, then the user must reset the bit and again set it to perform the autocalibration. The user must wait for at least 500 µs before another write to ensure a successful calibration. The
user is recommended not to sample CSA outputs during the AUTOCAL operation.
In addition to this, the device also supports an external calibration through the SPI registers (SPI_CAL) in SPI
device or through CAL pin in hardware device variant. When the calibration is enabled (CAL pin or SPI_CAL),
the inputs to the amplifier are shorted internally, and the amplifier voltage can be observed though SOX pin for
doing the external calibration. For the best results, perform offset calibration when the external MOSFETS are
not switching to reduce the potential noise impact to the amplifier. DC calibration can be done at any time, even
when the half-bridges are operating. Figure 36 shows a diagram of the calibration mode
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R2
R3
R4
R5
R6
SOx
CAL
SPX
±
CAL
SNX
+
RSENSE
VREF
R2
1/2
+
CAL
CAL
R3
±
R4
R5
Figure 36. Amplifier Calibration Mode
7.3.5 Gate-Driver Protection Circuits
The DRV8304 device is fully protected against VM undervoltage, charge pump undervoltage, MOSFET VDS
overcurrent, gate driver shorts, and overtemperature events.
Table 7. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
LOGIC
RECOVERY
VM
undervoltage
(UVLO)
VVM < VUVLO
—
nFAULT
Hi-Z
Disabled
Automatic:
VVM > VUVLO
Charge pump
undervoltage
(CPUV)
DIS_CPUV = 0b
nFAULT
Hi-Z
Active
VVCP < VCPUV
DIS_CPUV = 1b
None
Active
Active
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 01b
nFAULT
Hi-Z
Active
Retry:
tRETRY
OCP_MODE = 10b
nFAULT
Active
Active
No action
OCP_MODE = 11b
None
Active
Active
No action
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 01b
nFAULT
Hi-Z
Active
Retry:
tRETRY
VDS overcurrent
(VDS_OCP)
VSENSE
overcurrent
(SEN_OCP)
Gate driver fault
(GDF)
32
VDS > VVDS_OCP
VSP > VSEN_OCP
OCP_MODE = 10b
nFAULT
Active
Active
No action
OCP_MODE = 11b or
DIS_SEN = 1b
None
Active
Active
No action
DIS_GDF = 0b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, ENABLE Pulse
DIS_GDF = 1b
None
Active
Active
No action
Gate voltage stuck > tDRIVE
Thermal
warning
(OTW)
TJ > TOTW
Thermal
shutdown
(OTSD)
TJ > TOTSD
Automatic:
VVCP > VCPUV
OTW_REP = 1b
nFAULT
Active
Active
Automatic:
TJ < TOTW – THYS
OTW_REP = 0b
None
Active
Active
No action
—
nFAULT
Hi-Z
Active
Automatic:
TJ < TOTSD – THYS
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7.3.5.1 VM Supply Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VUVLO threshold, all of the external MOSFETs
are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and VM_UVLO bits
are also latched high in the registers on the SPI device. Normal operation resumes (gate driver operation and the
nFAULT pin is released) when the VM undervoltage condition is removed. The VM_UVLO bit remains set until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST).
7.3.5.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VCPUV threshold voltage of the charge
pump, all of the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and CPUV bits
are also latched high in the registers on the SPI device. Normal operation resumes (gate-driver operation and the
nFAULT pin is released) when the VCP undervoltage condition is removed. The CPUV bit remains set until
cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the DIS_CPUV bit high on the SPI
device disables this protection feature. On the hardware interface device, the CPUV protection is always
enabled.
7.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET RDS(on).
If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG deglitch
time, a VDS_OCP event is recognized and action is taken according to the OCP_MODE. On hardware interface
devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4.5 µs, and the OCP_MODE is
configured for 4-ms automatic retry. Moreover, the VDS_OCP can be disabled by tying the VDS pin to DVDD.
On SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, and the OCP_MODE bit can
operate in four different modes: VDS latched shutdown, VDS automatic retry, VDS report only, and VDS disabled.
7.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation resumes (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits remain latched until the tRETRY period expires.
7.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate normally. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
7.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SPX pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE bit. On the hardware interface device, the VSENSE threshold is fixed at 1 V, tOCP_DEG
is fixed at 4 µs, and the OCP_MODE bit for VSENSE is fixed for 4-ms automatic retry. On the SPI device, the
VSENSE threshold is set through the SEN_LVL SPI register and the OCP_MODE bit can operate in four different
modes: VSENSE latched shutdown, VSENSE automatic retry, VSENSE report only, and VSENSE disabled.
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7.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation resumes (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, SEN_OCP, and sense OCP bits remain latched until the tRETRY period expires.
7.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
7.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
7.3.5.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault might be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault might be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin is driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation resumes (gate driver
operation and the nFAULT pin is released) when the gate-driver fault condition is removed and a clear fault
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On the SPI device, setting
the DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external MOSFET
in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve a gate driver fault in these cases.
Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported because of
the MOSFET gate not turning on.
7.3.5.6 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
the SPI device. The device performs no additional action and continues to function. When the die temperature
decreases below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can
also be configured to report on the nFAULT pin by setting the OTW_REP bit to 1b through the SPI registers.
7.3.5.7 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit remains latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This
protection feature cannot be disabled.
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7.4 Device Functional Modes
7.4.1 Gate Driver Functional Modes
7.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV8304 device. When the ENABLE pin is low, the device enters a
low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are disabled, the
charge pump is disabled, the DVDD regulator is disabled, and the SPI bus is disabled. The tSLEEP time must
elapse after a falling edge on the ENABLE pin before the device enters sleep mode. The device comes out of
sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time must elapse before the device is
ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
NOTE
During power up and power down of the device through the ENABLE pin, the nFAULT pin
is held low as the internal regulators enable or disable. After the regulators have enabled
or disabled, the nFAULT pin is automatically released. The duration that the nFAULT pin
is low does not exceed the tSLEEP or tWAKE time.
7.4.1.2 Operating Mode
When the ENABLE pin is high and VVM > VUVLO, the device enters operating mode. The tWAKE time must elapse
before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD regulator,
and SPI bus are active and hardware inputs are latched.
NOTE
If the ENABLE pin is left floating, the device will be in Operating Mode.
7.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV8304 device enters a partial shutdown state to help protect the
external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on the SPI device or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the tRST time window or else the device will begin the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
7.5 Programming
This section applies only to the DRV8304 SPI device.
7.5.1 SPI Communication
7.5.1.1 SPI
On the DRV8304 SPI device, an SPI bus is used to set device configurations, operating parameters, and read
out diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input
data (SDI) word consists of a 16-bit word, with a 5-bit command and 11 bits of data. The SPI output data (SDO)
word consists of 11-bit register data. The first 5 bits are don’t care bits.
A
•
•
•
valid frame must meet the following conditions:
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
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Programming (continued)
placed in the Hi-Z state.
Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for the transaction to be valid.
If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5-bit command data.
•
•
•
•
•
7.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit B15)
• 4 address bits, A (bits B14 through B11)
• 11 data bits, D (bits B11 through B0)
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The data word is the content of
the register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
Table 8. SDI Input Data Word Format
R/W
ADDRESS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 9. SDO Output Data Word Format
DON'T CARE BITS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
Figure 37. SPI Slave Timing Diagram
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7.6 Register Maps
This section applies only to the DRV8304 SPI device.
NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 10). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller,
set the LOCK bits to lock the SPI registers.
Table 10. DRV8304S Register Map
Name
10
9
8
7
6
5
4
3
2
1
0
Type
Address
Fault Status 1
FAULT
VDS_OCP
GDF
UVLO
OTSD
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
R
0h
VGS Status 2
SA_OC
SB_OC
SC_OC
OTW
CPUV
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R
1h
Driver Control
Reserved
DIS_CPUV
DIS_GDF
OTW_REP
1PWM_COM
1PWM_DIR
COAST
BRAKE
CLR_FLT
RW
2h
Gate Drive HS
LOCK
Gate Drive LS
CBC
TDRIVE
OCP Control
TRETRY
DEAD_TIME
CSA Control
Reserved
VREF_DIV
LS_REF
Reserved
PWM_MODE
Reserved
IDRIVEP_HS
Reserved
IDRIVEN_HS
RW
3h
Reserved
IDRIVEP_LS
Reserved
IDRIVEN_LS
RW
4h
VDS_LVL
RW
5h
RW
6h
RW
7h
OCP_MODE
OCP_ACT
CSA_GAIN
DIS_SEN
Reserved
SPI_CAL
Reserved
AUTOCAL
Reserved
SEN_LVL
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7.6.1 Status Registers (DRV8304S Only)
The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for
access types in this section.
Table 11. Status Registers Access Type Codes
Access Type
Code
Description
R
Read
Read Type
R
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 Fault Status Register 1 (Address = 0x00) [reset = 0x00]
The fault status register 1 is shown in Figure 38 and described in Table 12.
Register access type: Read only
Figure 38. Fault Status Register 1
10
9
8
7
6
5
4
3
2
1
0
FAULT
VDS_OCP
GDF
UVLO
OTSD
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 12. Fault Status Register 1 Field Descriptions
38
Bit
Field
Type
Default
Description
10
FAULT
R
0b
Logic OR of FAULT status registers. Mirrors nFAULT pin.
9
VDS_OCP
R
0b
Indicates VDS monitor overcurrent fault condition
8
GDF
R
0b
Indicates gate drive fault condition
7
UVLO
R
0b
Indicates undervoltage lockout fault condition
6
OTSD
R
0b
Indicates overtemperature shutdown
5
VDS_HA
R
0b
Indicates VDS overcurrent fault on the A high-side MOSFET
4
VDS_LA
R
0b
Indicates VDS overcurrent fault on the A low-side MOSFET
3
VDS_HB
R
0b
Indicates VDS overcurrent fault on the B high-side MOSFET
2
VDS_LB
R
0b
Indicates VDS overcurrent fault on the B low-side MOSFET
1
VDS_HC
R
0b
Indicates VDS overcurrent fault on the C high-side MOSFET
0
VDS_LC
R
0b
Indicates VDS overcurrent fault on the C low-side MOSFET
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7.6.1.2 Fault Status Register 2 (Address = 0x01) [reset = 0x00]
The fault status register 2 is shown in Figure 39 and described in Table 13.
Register access type: Read only
Figure 39. Fault Status Register 2
10
9
8
7
6
5
4
3
2
1
0
SA_OC
SB_OC
SC_OC
OTW
CPUV
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
Table 13. Fault Status Register 2 Field Descriptions
Bit
Field
Type
Default
Description
10
SA_OC
R
0b
Indicates overcurrent on phase A sense amplifier (DRV8304S)
9
SB_OC
R
0b
Indicates overcurrent on phase B sense amplifier (DRV8304S)
8
SC_OC
R
0b
Indicates overcurrent on phase C sense amplifier (DRV8304S)
7
OTW
R
0b
Indicates overtemperature warning
6
CPUV
R
0b
Indicates charge pump undervoltage fault condition
5
VGS_HA
R
0b
Indicates gate drive fault on the A high-side MOSFET
4
VGS_LA
R
0b
Indicates gate drive fault on the A low-side MOSFET
3
VGS_HB
R
0b
Indicates gate drive fault on the B high-side MOSFET
2
VGS_LB
R
0b
Indicates gate drive fault on the B low-side MOSFET
1
VGS_HC
R
0b
Indicates gate drive fault on the C high-side MOSFET
0
VGS_LC
R
0b
Indicates gate drive fault on the C low-side MOSFET
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7.6.2 Control Registers (DRV8304S Only)
The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. Table 14 shows the codes that are used for
access types in this section.
Table 14. Control Registers Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
7.6.2.1 Driver Control Register (Address = 0x02) [reset = 0x00]
The driver control register is shown in Figure 40 and described in Table 15.
Register access type: Read/Write
Figure 40. Driver Control Register
10
9
8
7
Reserved
DIS
_CPUV
DIS
_GDF
OTW
_REP
R/W-0b
R/W-0b
R/W-0b
R/W-0b
6
5
4
3
PWM_MODE
1PWM
_COM
1PWM
_DIR
R/W-00b
R/W-0b
R/W-0b
2
1
0
COAST
BRAKE
CLR
_FLT
R/W-0b
R/W-0b
R/W-0b
Table 15. Driver Control Field Descriptions
Bit
Field
Type
Default
Description
10
Reserved
R/W
0b
Reserved
9
DIS_CPUV
R/W
0b
0b = Charge-pump undervoltage lockout fault is enabled
8
DIS_GDF
R/W
0b
7
OTW_REP
R/W
0b
PWM_MODE
R/W
00b
1b = Charge-pump undervoltage lockout fault is disabled
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5
00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification (diode
freewheeling)
40
3
1PWM_DIR
R/W
0b
In 1x PWM mode this bit is ORed with the INHC (DIR) input
2
COAST
R/W
0b
Write a 1b to this bit to put all MOSFETs in the Hi-Z state
1
BRAKE
R/W
0b
Write a 1b to this bit to turn on all three low-side MOSFETs in 1x
PWM mode.
This bit is ORed with the INLC (BRAKE) input.
0
CLR_FLT
R/W
0b
Write a 1b to this bit to clear latched fault bits.
This bit automatically resets after being written.
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7.6.2.2 Gate Drive HS Register (Address = 0x03) [reset = 0x377]
The gate drive HS register is shown in Figure 41 and described in Table 16.
Register access type: Read/Write
Figure 41. Gate Drive HS Register
10
9
8
7
6
5
4
3
2
1
LOCK
Reserved
IDRIVEP_HS
Reserved
IDRIVEN_HS
R/W-011b
R/W-0b
R/W-111b
R/W-0b
R/W-111b
0
Table 16. Gate Drive HS Field Descriptions
Bit
Field
Type
Default
Description
10-8
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02h bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
Reserved
R/W
0b
Reserved
IDRIVEP_HS
R/W
111b
000b = 15 mA
7
6-4
001b = 15 mA
010b = 45 mA
011b = 60 mA
100b = 90 mA
101b = 105 mA
110b = 135 mA
111b = 150 mA
3
2-0
Reserved
R/W
0b
Reserved
IDRIVEN_HS
R/W
111b
000b = 30 mA
001b = 30 mA
010b = 90 mA
011b = 120 mA
100b = 180 mA
101b = 210 mA
110b = 270 mA
111b = 300 mA
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7.6.2.3 Gate Drive LS Register (Address = 0x04) [reset = 0x777]
The gate drive LS register is shown in Figure 42 and described in Table 17.
Register access type: Read/Write
Figure 42. Gate Drive LS Register
10
9
8
7
6
5
4
3
2
1
CBC
TDRIVE
Reserved
IDRIVEP_LS
Reserved
IDRIVEN_LS
R/W-1b
R/W-11b
R/W-0b
R/W-111b
R/W-0b
R/W-111b
0
Table 17. Gate Drive LS Register Field Descriptions
Bit
Field
Type
Default
Description
10
CBC
R/W
1b
In retry OCP_MODE, for both VDS_OCP and SEN_OCP, the
fault is automatically cleared when a PWM input is given
9-8
TDRIVE
R/W
11b
00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
7
6-4
Reserved
R/W
0b
Reserved
IDRIVEP_LS
R/W
111b
000b = 15 mA
001b = 15 mA
010b = 45 mA
011b = 60 mA
100b = 90 mA
101b = 105 mA
110b = 135 mA
111b = 150 mA
3
2-0
Reserved
R/W
0b
Reserved
IDRIVEN_LS
R/W
111b
000b = 30 mA
001b = 30 mA
010b = 90 mA
011b = 120 mA
100b = 180 mA
101b = 210 mA
110b = 270 mA
111b = 300 mA
42
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7.6.2.4 OCP Control Register (Address = 0x05) [reset = 0x145]
The OCP control register is shown in Figure 43 and described in Table 18.
Register access type: Read/Write
Figure 43. OCP Control Register
10
9
8
7
6
5
4
3
2
1
TRETRY
DEAD_TIME
OCP_MODE
OCP_ACT
Reserved
VDS_LVL
R/W-0b
R/W-01b
R/W-01b
R/W-0b
R/W-00b
R/W-101b
0
Table 18. OCP Control Field Descriptions
Bit
Field
Type
Default
Description
10
TRETRY
R/W
0b
0b = VDS_OCP and SEN_OCP retry time is 4 ms
9-8
DEAD_TIME
R/W
01b
1b = VDS_OCP and SEN_OCP retry time is 50 µs
00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
7-6
OCP_MODE
R/W
01b
00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
5
OCP_ACT
R/W
0b
0b = All three half-bridges are shutdown in response to
VDS_OCP and SEN_OCP
1b = Associated half-bridge is shutdown in response to
VDS_OCP and SEN_OCP
4-3
Reserved
R/W
00b
Reserved
2-0
VDS_LVL
R/W
101b
000b = 0.15 V
001b = 0.24 V
010b = 0.40V
011b = 0.51 V
100b = 0.60 V
101b = 0.90 V
110b = 1.8 V
111b = VDS Disabled
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7.6.2.5 CSA Control Register (Address = 0x06) [reset = 0x283]
The CSA control register is shown in Figure 44 and described in Table 19.
Register access type: Read/Write
Figure 44. CSA Control Register
10
9
8
Reserved
VREF
_DIV
LS
_REF
R/W-0b
R/W-1b
R/W-0b
7
6
5
4
3
2
CSA_GAIN
DIS
_SEN
SPI
_CAL
AUTO
CAL
1
0
Reserved
SEN_LVL
R/W-10b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-11b
Table 19. CSA Control Field Descriptions
Bit
Field
Type
Default
Description
10
Reserved
R/W
0b
Reserved
9
VREF_DIV
R/W
1b
0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
8
LS_REF
R/W
0b
0b = VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6
CSA_GAIN
R/W
10b
00b = 5-V/V shunt amplifier gain
01b = 10-V/V shunt amplifier gain
10b = 20-V/V shunt amplifier gain
11b = 40-V/V shunt amplifier gain
5
DIS_SEN
R/W
0b
4
SPI_CAL
R/W
0b
3
AUTOCAL
R/W
0b
0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
0b = Disable sense amplifier CAL function
1b = Enable sense amplifier CAL function
0b = AUTOCAL operation remains disabled in run mode
1b = Perform AUTOCAL operation
2
Reserved
R/W
0b
Reserved
1-0
SEN_LVL
R/W
11b
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
44
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8304 device is primarily used in 3-phase brushless DC motor control applications. The design
procedures in the Typical Application section highlight how to use and configure the DRV8304 device.
8.2 Typical Application
8.2.1 Primary Application
In this application the amplifiers are configured to sense bi-directional currents in each of the three half-bridge
legs.
Power and Charge Pump
3.3 V, 30 mA
1 µF
DVDD
AGND
VM
GND
VM
Three Phase Inverter
GND
VM
Gate Driver
VDD
GND
Power
GP-O
GP-O
GP-I
GPIO
PWM1, PWW2
PWM
PWM3, PWM4
Module
PWM5, PWM6
SPI SCLK
SDI
(DAC and External
Resistor for H/W I/F) SDO
nSCS
Analog to Digital
Converters
3x ADC
Microcontroller
GHB
SHB
GLB
INHA, INLA
INHB,INLB
INHC, INLC
SCLK
SDI
SDO
nSCS
GHC
SHC
GLC
MODE
IDRIVE
VDS
GAIN
SOA
SOB
SOC
BLDC Motor
GHA
SHA
GLA
ENABLE
CAL
nFAULT
Smart Gate Drive
150 mA, 300 mA
(Fully Protected)
SPA, SNA
SPV, SNB
SPC, SNC
DRV8304
Figure 45. Primary Application Schematic
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Typical Application (continued)
8.2.1.1 Design Requirements
Table 20 lists the example input parameters for the system design.
Table 20. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
Nominal supply voltage
VVM
Supply voltage range
MOSFET part number
EXAMPLE VALUE
24 V
8 V to 38 V
CSD18514Q5A
MOSFET total gate charge
Qg
MOSFET gate to drain charge
Qgd
5 nC (typical)
Target output rise time
tr
100 to 300 ns
Target output fall time
tf
50 to 150 ns
ƒPWM
45 kHz
PWM frequency
Maximum motor current
Winding sense current range
Motor RMS current
Sense resistor power rating
System ambient temperature
29 nC (typical) at VVGS = 10 V
Imax
50 A
ISENSE
–20 A to +20 A
IRMS
14.14 A
PSENSE
2W
TA
–20°C to +105°C
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External MOSFET Support
The DRV8304 MOSFET support is based on the charge-pump capacity and output PWM switching frequency.
For a quick calculation of MOSFET driving capacity, use Equation 5 and Equation 6 for three phase BLDC motor
applications.
Trapezoidal 120° Commutation:IVCP > Qg ׃PWM
Sinusoidal 180° Commutation:IVCP > 3 × Qg ׃PWM
(5)
where
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
IVCP is the charge pump capacity, which depends on the VM pin voltage.
The multiplier based on the commutation control method, may vary based on implementation.
(6)
8.2.1.2.1.1 Example
If a system at VVM = 8 V (IVCP = 15 mA) uses a maximum PWM switching frequency of 45 kHz, then the charge
pump can support MOSFETs using trapezoidal commutation with a Qg < 333 nC, and MOSFETs with sinusoidal
commutation Qg < 111 nC. When the VM voltage (VVM) is 8 V, the maximum DRV8304 gate-drive voltage (VGSH)
is 7.3 V. Therefore, at 7.3-V gate drive, the target FET (part number CSD18514Q5A) only has a gate charge of
approximately 22 nC. Therefore, with this FET, the system can have an adequate margin.
8.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
the SPI device through the SPI registers. On hardware interface devices, both source and sink settings are
selected simultaneously on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge (Qgd), desired rise time (tr), and a desired fall time (tf), use
Equation 7 and Equation 8 to calculate the value of IDRIVEP and IDRIVEN (respectively).
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IDRIVEN !
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Qgd
tr
(7)
Qgd
tf
(8)
8.2.1.2.2.1 Example
Use Equation 9 and Equation 10 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain
charge of 5 nC and a rise time from 100 to 300 ns.
5 nC
IDRIVEP1
50 mA
100 ns
(9)
5 nC
IDRIVEP2
16.67 mA
300 ns
(10)
Select a value for IDRIVEP that is between 16.67 mA and 50 mA. For this example, the value of IDRIVEP was
selected as 45-mA source.
Use Equation 11 and Equation 12 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain
charge of 5 nC and a fall time from 50 to 150 ns.
5 nC
IDRIVEN1
100 mA
50 ns
(11)
5 nC
IDRIVEN2
33.33 mA
150 ns
(12)
Select a value for IDRIVEN that is between 33.33 mA and 100 mA. For this example, the value of IDRIVEN was
selected as 90-mA sink.
8.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in Equation 13.
VDS _ OCP ! Imax u RDS(on)max
(13)
8.2.1.2.3.1 Example
The goal of this example is to set the VDS monitor to trip at a current greater than 50 A. According to the
CSD18514Q5A 40 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 1.8 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 4.9 mΩ. From these values, the approximate worstcase value of RDS(on) is 1.8 × 4.9 mΩ = 8.82 mΩ.
Using Equation 13 with a value of 8.82 mΩ for RDS(on) and a worst-case motor current of 50 A, Equation 14
shows the calculated the value of the VDS monitors.
VDS _ OCP ! 50 A u 8.82 m:
VDS _ OCP ! 0.441 V
(14)
For this example, the value of VDS_OCP was selected as 0.51 V.
The deglitch time for the VDS overcurrent monitor is fixed at 4.5 µs.
8.2.1.2.4 Sense-Amplifier Bidirectional Configuration
The sense-amplifier gain and the sense-resistor value on the DRV8304 device are selected based on the target
current range, VREF voltage supply, sense-resistor power rating, and operating temperature range. In
bidirectional operation of the sense amplifier, the dynamic range at the output is approximately calculated as
shown in Equation 15.
VVREF
VO
VVREF 0.25 V
2
(15)
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Use Equation 16 to calculate the approximate value of the selected sense resistor with VO calculated using
Equation 15.
VO
R
PSENSE ! IRMS2 u R
AV u I
(16)
From Equation 15 and Equation 16, select a target gain setting based on the power rating of the target-sense
resistor.
8.2.1.2.4.1 Example
In this system example, the value of the VREF voltage is 3.3 V with a sense current from –20 to +20 A. The
linear range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range
of the sense amplifier input is –0.3 to +0.3 V (VDIFF).
3.3 V
VO
3.3 V 0.25 V
1.4 V
(17)
2
1.4 V
2
R
2 W ! 14.14 u R o R 10 m:
A V u 20 A
(18)
10 m: !
1.4 V
o AV ! 7
A V u 20 A
(19)
Therefore, the gain setting must be selected as 10 V/V or 20 V/V and the value of the sense resistor must be
less than 10 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 10 V/V. The value of the resistor and worst case current can be verified that R < 10 mΩ and Imax =
20 A does not violate the differential range specification of the sense amplifier input (VSPxD).
I
SP
SO
R
AV
SN
SO
VREF
SP ± SN
VVREF ± 0.25 V
±0.3 V
±I × R
VSO(range±)
VSO(off)max
VOFF,
VDRIFT
VVREF / 2
0V
VSO(off)min
VSO(range+)
I×R
0.25 V
0.3 V
0V
Figure 46. Sense Amplifier Configuration
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8.2.1.3 Application Curves
Figure 47. IDRIVE Maximum Setting
Figure 48. IDRIVE Minimum Setting
Figure 49. Gate Drive 80% Duty Cycle
Figure 50. Gate Drive 20% Duty Cycle
Figure 51. Motor Operation at 80% PWM Duty
Figure 52. Motor Operation at 20% PWM Duty
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Figure 53. Motor Starting With PWM Duty Change
Figure 54. Motor Starting With Supply Voltage Change
Figure 55. Motor Performance at Speed Change
Figure 56. Motor Performance at Load Change
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8.2.2 Alternative Application
In this application, a single-sense amplifier is used in unidirectional mode for a summing current-sense scheme
often used in trapezoidal or hall-based BLDC commutation control.
Power and Charge Pump
3.3 V, 30 mA
VM
GND
DVDD
AGND
1 …F
VM
Three Phase Inverter
GND
VM
Gate Driver
VDD
GND
Power
GPIO
PWM
Module
ENABLE
CAL
nFAULT
GP-O
GP-O
GP-I
PWM1, PWW2
PWM3, PWM4
PWM5, PWM6
SPI
(DAC and External
Resistor for H/W I/F)
Analog-to-Digital
Converters 1x ADC
GHB
SHB
GLB
INHA, INLA
INHB,INLB
INHC, INLC
SCLK
SDI
SDO
nSCS
SCLK
SDI
SDO
nSCS
CSA Output
SOA
SOB
SOC
Microcontroller
BLDC Motor
GHA
SHA
GLA
GHC
SHC
GLC
Smart Gate Drive
150 mA, 300 mA
(Fully Protected)
MODE
IDRIVE
VDS
GAIN
SPA, SNA
SPV, SNB
SPC, SNC
Current Sense
Single Channel
DRV8304
Figure 57. Alternative Application Schematic
8.2.2.1 Design Requirements
Table 21 lists the example design input parameters for system design.
Table 21. Design Parameters
EXAMPLE DESIGN PARAMETER
REFERENCE
EXAMPLE VALUE
ADC reference voltage
VVREF
3.3 V
Sensed current
ISENSE
0 to 20 A
IRMS
14.14 A
Motor RMS current
Sense-resistor power rating
System ambient temperature
PSENSE
3W
TA
–20°C to +125°C
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Sense-Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on the SPI device by writing a 0b to
the VREF_DIV bit.
The sense-amplifier gain and sense resistor values are selected based on the target current range, VREF,
sense-resistor power rating, and operating temperature range. In unidirectional operation of the sense amplifier,
use Equation 20 to calculate the approximate value of the dynamic range at the output.
VO
VVREF 0.25 V 0.25 V VVREF 0.5 V
(20)
Use Equation 21 to calculate the approximate value of the selected sense resistor.
VO
R
PSENSE ! IRMS2 u R
AV u I
where
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0.5 V
(21)
From Equation 20 and Equation 21, select a target gain setting based on the power rating of a target sense
resistor.
8.2.2.2.1.1 Example
In this system example, the value of VREF is 3.3 V with a sense current from 0 to 40 A. The linear range of the
SOx output for the DRV8304 device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential
range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO 3.3 V 0.5 V 2.8 V
(22)
R
2.8 V
A V u 20 A
3 W ! 14.142 u R o R 15 m:
(23)
2.8 V
15 m: !
o A V ! 9.3
A V u 20 A
(24)
Therefore, the gain setting must be selected as 10 V/V or 20 V/V and the value of the sense resistor must be
less than 15 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 15 mΩ and Imax =
20 A does not violate the differential range specification of the sense amplifier input (VSPxD).
I
SP
SO
R
AV
SN
SO
VREF
VVREF ± 0.25 V
VSO(off)max
VOFF,
VVREF ± 0.3 V
SP ± SN
VDRIFT
0V
VSO(off)min
VSO(range)
I×R
0.3 V
0.25 V
0V
Figure 58. Sense Amplifier Configuration
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9 Power Supply Recommendations
The DRV8304 device is designed to operate from an input voltage supply (VM) range from 6 V to 38 V. A 0.1-µF
ceramic capacitor rated for VM must be placed as close to the device as possible. In addition, a bulk capacitor
must be included on the VM pin but can be shared with the bulk bypass capacitance for the external power
MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs and should be
sized according to the application requirements.
9.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 59. Motor Drive Supply Parasitics Example
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10 Layout
10.1 Layout Guidelines
Bypass the VM pin to the PGND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connected to
the PGND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 22 nF, rated for
VM, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and VM pins.
This capacitor should be 1 µF, rated for 16 V, and be of type X5R or X7R.
Bypass the DVDD pin to the AGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type X5R
or X7R. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the
AGND pin.
The VDRAIN pin can be shorted directly to the VM pin. However, if a significant distance is between the device
and the external MOSFETs, use a dedicated trace to connect to the common point of the drains of the high-side
external MOSFETs. Do not connect the SNx pins directly to the PGND pin. Instead, use dedicated traces to
connect these pins to the sources of the low-side external MOSFETs. These recommendations allow for more
accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the PGND pin.
54
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SLVSE39B – NOVEMBER 2017 – REVISED JULY 2018
D
S
D
S
D
G
D
D
G
D
S
D
S
D
S
D
G
D
S
D
S
D
S
S
D
S
D
21
23
22
25
24
27
26
29
31
20
19
33
18
34
17
DRV8304RHA
35
16
36
15
Thermal Pad
37
14
38
13
GND
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
GND
10
9
8
6
7
4
CPL
CPH
VCP
VM
VDRAIN
GHA
SHA
GLA
SPA
SNA
5
12
11
2
39
40
1
DVDD
INHA
INLA
INHB
INLB
INHC
INLC
GND
32
3
CAL
AGND
DVDD
INHA
INLA
INHB
INLB
INHC
INLC
PGND
28
30
ENABLE
nSCS
SCLK
SDI
SDO
nFAULT
VREF
SOA
SOB
SOC
GND
S
D
G
D
S
D
S
D
OUTB
OUTC
SOA
SOB
SOC
G
N
D
S
GND
GND
GND
S
D
G
D
D
G
D
S
D
S
D
S
OUTA
CAL
ENABLE
nSCS
SCLK
SDI
SDO
nFAULT
VREF
10.2 Layout Example
Figure 60. Layout Example
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11 Device and Documentation Support
11.1 Device Support
Refer to the TI Design for development support:
10.8-V/30-W, >95% Efficiency, 4.3-cm2, Power Stage Reference Design for Brushless DC Servo Drive TI
Design
11.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
DRV830
(4)
(H) (RHA) (R)
Prefix
DRV83 ± Brushless-DC three-phase
Tape and Reel
R ± Tape and Reel (higher SPQ)
T ± Small Tape and Reel
Package
RHA ± 6 × 6 × 0.9 mm QFN
Series
4 ± 40 V device
Interface
S ± SPI
H ± Hardware
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, BOOSTXL-DRV8304H EVM User's Guide user's guide
• Texas Instruments, BOOSTXL-DRV8304x EVM GUI User’s Guide user's guide
• Texas Instruments, BOOSTXL-DRV8304x EVM Sensored Software User's Guide user's guide
• Texas Instruments, BOOSTXL-DRV8304x EVM Sensorless Software User's Guide user's guide
• Texas Instruments, Brushless-DC Made Simple – Sensored Motor Control TI TechNote
• Texas Instruments, Field Oriented Control (FOC) Made Easy for Brushless DC (BLDC) Motors Using TI
Smart Gate Drivers TI TechNote
• Texas Instruments, Hardware Design Considerations for an Efficient Vacuum Cleaner using BLDC Motor
application report
• Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor application
report
• Texas Instruments, Industrial Motor Drive Solution Guide
• Texas Instruments, Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, Motor Drive Protection With TI Smart Gate Drive TI TechNote
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Reduce Motor Drive BOM and PCB Area with TI Smart Gate Drive TI TechNote
• Texas Instruments, Reducing EMI Radiated Emissions with TI Smart Gate Drive TI TechNote
• Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report
• Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
56
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11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
NexFET, MSP430, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DRV8304HRHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8304H
DRV8304HRHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8304H
DRV8304SRHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DRV8304S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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