LM5070HEEVAL

User's Guide SNVA094C – November 2004 – Revised May 2013 AN-1346 LM5070 "HE" Evaluation Board 1 Introduction The LM5070 HE (high efficiency) evaluation board is designed to provide an IEEE802.3af compliant, Power over Ethernet (PoE) power supply. The power supply features the LM5070 PoE powered device (PD) interface and controller integrated circuit (IC) configured in the versatile flyback topology. General performance features of the HE evaluation board are: • Isolated 3.3V output • Input range: 38 to 60V • Output current: 0 to 3.4A • Measured converter efficiency: 90.5% at 1.5A, 90% at 3.0A • Frequency of operation: 250kHz • Board size: 1.75 x 1.25 x 0.6 inches • Programmed under-voltage lockout (UVLO) release: 38.6V • Programmed UVLO: 32.4V (6.2V Hysteresis) 2 A Note About Potentials The LM5070 is designed to work with PoE applications that are typically -48V systems. The data sheet for the LM5070 was written under the more generic, and more easily understood, positive voltage convention referenced to the VEE pin of the IC. The application board is an example of a PoE system architecture, and has pins “GND” and “-48V” for the high and low input potentials, respectively, and output pins “+3.3V” and “RTN”. For simplicity and consistency with the data sheet, this application note will be written and all measurements will be taken using the positive voltage convention, with the -48V pin connected to the bench power supply ground, and the GND pin connected to the power supply high potential. Input steering diodes prevent damage if input terminals are accidentally reversed. 3 Signature Discovery Mode To detect a powered device connected to the Ethernet cable, the Power Sourcing Equipment (PSE) will apply two different voltages between 2.8V and 10V across the input terminals of the PD. A PD will be considered present if the detected differential impedance is above 23.75kΩ and below 26.25kΩ. If the impedance is less than 15kΩ or greater than 33kΩ, a PD will be considered not present and will not receive power. Impedances between these values may or may not indicate the presence of a valid PD. The LM5070 will enable the signature resistor (R5) at an input voltage of 1.5V, and disable signature mode around 12V, measured at the input pins of the IC. The actual differential threshold voltages measured at the PD board terminals will be somewhat higher (~1V) due to the input diodes that are in series with the input pins. 4 Classification Mode To classify the PD according to power draw, the PSE will present a voltage between 14.5V and 20.5V to the PD. The LM5070 enables classification mode at a nominal input voltage of 11.7V, again measured at the input pins of the IC. An internal 1.5V linear regulator (referenced to VEE) and an external resistor connected between the RCLASS pin and VEE provide classification programming current. The following table can be used to select the proper RCLASS resistor. All trademarks are the property of their respective owners. SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback AN-1346 LM5070 "HE" Evaluation Board Copyright © 2004–2013, Texas Instruments Incorporated 1 UVLO and UVLO Hysteresis www.ti.com Class PMIN PMAX ICLASS (MIN) ICLASS (MAX) RCLASS 0 0.44W 12.95W 1 0.44W 3.84W 0mA 4mA Open 9mA 12mA 2 3.84W 150Ω 6.49W 17mA 20mA 82.5Ω 3 6.49W 12.95W 26mA 30mA 53.6Ω 4 Reserved Reserved 36mA 44mA 38.3Ω As seen on the board schematic, no resistor is needed to program class 0 (full power) because the bias current of the IC (~600µA) will be considered class 0 without any additional current draw. 5 UVLO and UVLO Hysteresis The UVLO threshold and UVLO hysteresis can be programmed completely independently of each other. UVLO hysteresis is accomplished with an internal 10uA current source that is switched on and off into the impedance of the UVLO set point resistor divider. When the UVLO pin exceeds 2.00V, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.00V threshold, the current source is turned off, causing the voltage at the UVLO pin to fall. The LM5070 UVLO thresholds cannot be programmed lower than 23V, otherwise the device would operate in classification mode with both the classification current source and the SMPS enabled. The combined power dissipation of these two functions could exceed the maximum power dissipation of the package. Without taking into account the external diodes, UVLO is programmed on the HE board to 31.4V, with 6.2V of hysteresis. UVLO will therefore release at 37.6V. The input steering diodes will add approximately 1V to each threshold, so the UVLO and UVLO release thresholds will be 32.4V and 38.6V, measured at the input pins of the board, respectively 6 Inrush Current Limiting The LM5070's default inrush current can be as high as 400mA at room temperature. With 20Ω effective series resistance in the input line, an 8V drop may occur at startup. When all tolerances are taken into consideration, it is difficult to guarantee a minimum of 8V of hysteresis while staying within the threshold limits of the IEEE specification. Also, margin between the minimum hysteresis designed and the maximum required is an important design constraint. To lessen the hysteresis requirement, one should program the inrush current to a lesser value. On the HE application board, the inrush current has been programmed to 150mA using the following equation: RCLP = 16 k: x A I inrush (A) LIMIT = 16 k: x A = 107 k: 0.150A (1) Taking 20% current programming accuracy into consideration, programming the current limit to 150mA decreases the hysteresis requirement to 3.6V, and a much more robust design is now possible. Programming the inrush current does not affect the power delivering capability during normal operation because the current limit level is switched back to the default level at the end of the inrush sequence. 7 Flyback Theory of Operation The flyback transformer is actually a coupled inductor with multiple windings wound on a single gapped core. For simplification, we refer to the first, driven winding, as the primary and the main output winding as the secondary winding of the flyback transformer. The flyback converter is a converter in which inductive energy is stored by applying a voltage across the primary in a similar manner to that of a boost converter. A second coupled winding (secondary) of the inductor transfers the energy to a secondary side synchronous rectifier after the primary voltage has been switched off. This allows the converter input and output grounds to be configured either isolated or nonisolated. A voltage / current ratio transformation is possible by altering the winding ratio between the primary and any other winding. A semi-regulated auxiliary winding can also be provided to bias primary or secondary control circuits. 2 AN-1346 LM5070 "HE" Evaluation Board SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Proper Board Connections www.ti.com The transformer’s primary inductance is typically designed as large as is practical. However, the air gap necessary to store the cycle energy lowers the obtainable inductance. The higher the primary inductance, the less input ripple current will be generated and the less input filtering will be required. As shown, the LM5070 directly drives a MOSFET switch to apply voltage across the primary. When the switch turns off, the secondary applies a forward current to the output synchronous rectifier and charges the output capacitor. In applications where the input voltage is considerably higher than the output voltage, the turns ratio between primary and secondary will reflect the input/output voltage ratio and the duty cycle. The LM5070 controller provides an internal startup regulator (VCC), soft start, and over-current protection. The controller can and will run indefinitely without the winding, but the increase in on chip power dissipation will decrease efficiency and may reduce the maximum ambient operating temperature. 8 Proper Board Connections Be sure to choose the correct wire size when connecting the source supply and load. Monitor the current into and out of the unit under test (UUT). Monitor the voltages directly at the board terminals, as resistive voltage drops along the wires may decrease measurement accuracy. These precautions are especially important during measurement of conversion efficiency. 9 Source Power To fully test the LM5070 evaluation board, a DC power supply capable of at least 60V and 1A is required. Adjusting the short circuit current limit on the power supply to ~1A may prevent board damage if an errant connection is made during evaluation. 10 Loading / Current Limiting Behavior A resistive load is optimal, but an appropriate electronic load specified for operation down to 2.0V is acceptable. The maximum load current is 3.4A, exceeding this current at low line may cause oscillatory behavior as the part will go into current limit mode. Current limit mode is triggered any time the average current through the main internal circuit breaker MOSFET exceeds 390mA. If current limit is triggered, the switching regulator is automatically disabled by discharging the softstart pin. The module is then allowed to restart, but the part will reset itself indefinitely if the condition causing the current limit to trip remains. 11 Power Up It is suggested that the load be kept reasonably low during the first power up. Check the supply current during signature and classification modes before applying full power. During signature mode, the module should have the I-V characteristics of a 25kΩ resistor in series with two diodes. During classification mode, current draw should be about 600µA at 15V as the RCLASS pin is left open to default to class 0. If the proper response is not observed during both signature and classification modes, check the connections closely. If no current is flowing it is likely the GND and -48V input terminals have been reversed. Once proper setup has been established, full power (48V) may be applied. A voltmeter across the output terminals, +3.3V and RTN, will allow direct measurement of the 3.3V output line. Because the output voltage is isolated, it cannot be measured by a meter referenced to the bench power supply ground. If 3.3V is not observed within a few seconds, turn the power supply off and review connections. A final check of efficiency is the best way to confirm that the UUT is operating properly. Few parameters can be incorrect in a switching power supply without creating additional losses and potentially damaging heat. Efficiency above 80% is expected. SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback AN-1346 LM5070 "HE" Evaluation Board Copyright © 2004–2013, Texas Instruments Incorporated 3 Performance Characteristics 12 www.ti.com Performance Characteristics 12.1 Power Up Sequence In addition to a reduction in board area, the high level of integration designed into the LM5070 allows all power sequencing communications to occur within the IC. Very little system management design is required by the design engineer. The power up sequence is as follows (note the RTN pin discussed, IC pin 8, is different from the +3.3V RTN output pin of the board): 1. Before power up, all nodes in the non-isolated section of the power supply remain at high potential until UVLO is released and the drain of the main circuit breaker internal MOSFET is pulled down to VEE (IC pin 7). 2. Once the RTN pin of the IC drops below 1.5V (referenced to VEE), the VCC regulator is released and allowed to start. This signals the assertion of the internal “Power Good” signal. The VCC regulator ramps at a rate equal to its current limit, typically 20 mA, divided by the VCC load capacitance. 3. Once the VCC regulator is within minimum regulation, about 7.9V referenced to RTN, the softstart pin is released. The softstart pin will rise at a rate equal to the softstart current source, typically 10µA, divided by the softstart pin capacitance. 4. As the switching regulator achieves regulation, the auxiliary winding will raise the VCC voltage to ~10V, thus shutting down the internal regulator and increasing efficiency. Figure 1 shows the RTN, VCC, and Softstart IC pins during a normal startup sequence. The auxiliary winding starts to supply a higher voltage to VCC as the switching regulator output voltage rises. 3 2 1 Horizontal resolution: 5 ms/Div. Trace 1: RTN pin, elevated until UVLO release 20.0 V/Div. ` Trace 2. Softstart pin, starts when VCC achieves minimum regulation, 5.0 V/Div. Trace 3: VCC, starts when RTN < 1.5V, elevated by auxiliary winding, 5.0 V/Div. Figure 1. Normal Startup Sequence Figure 2 shows a normal 3.3V line startup, along with the softstart pin for reference. 4 AN-1346 LM5070 "HE" Evaluation Board SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Performance Characteristics www.ti.com 2 1 Horizontal resolution: 1 ms/Div. Trace 1: +3.3V output line, 1.0 V/Div. Trace 2: Softstart pin, 1.0 V/Div. Figure 2. Regulator Output (+3.3 V) Startup Detail 12.2 Output Dead Short Fault Response The system should be able to survive a dead short at the output. Applying a dead short to the +3.3V line causes a number of protection mechanisms to trip sequentially. They are: 1. Feedback raises duty cycle in an attempt to maintain the output voltage. This causes a cycle-by-cycle over-current condition to exist at the programmable current sense (CS) pin of the IC. 2. The average current in the internal circuit breaker MOSFET rises until it is current limited around 390mA. Some overshoot in the current will be observed, as it takes time for the current limit amplifier to react and change the operating mode of the MOSFET. 3. Because linear current limit is accomplished by driving the MOSFET into saturation, the drain voltage (RTN pin) rises. When it reaches 2.5V with respect to VEE, the internal Power Good signal is deasserted. 4. The de-assertion of Power Good causes the discharge of the Softstart pin, which disables all switching action. 5. Once the switching action stops, the fault condition is no longer observed by the LM5070, and the system is allowed to automatically restart when Power Good is re-asserted. Automatic re-try mode due to a shorted output condition can be observed in Figure 3. The softstart pin is observed to rise quickly as the LM5070 reacts to the fault, and this is because it references RTN, while all scope measurements reference VEE. SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback AN-1346 LM5070 "HE" Evaluation Board Copyright © 2004–2013, Texas Instruments Incorporated 5 Performance Characteristics www.ti.com 3 2 1 Horizontal resolution: 2 ms/Div. Trace 1: RTN pin of the LM5070 IC, 1 V/Div. Trace 2: Softstart pin, 2.0 V/Div. Trace 3: Test board input current, 200 mA/Div Figure 3. Shorted Output Fault Condition / Automatic Re-try 12.3 Step Response Figure 4 shows the step response at VIN = 48V for an instantaneous load change from 8% to 88%. The input voltage, input current, and output voltage are shown. 2 1 3 Horizontal resolution: 50 Ps/Div. Trace 1: Input voltage, AC coupled, 0.50 V/Div. Trace 2: Output voltage, AC coupled, 200 mV/Div. Trace 3: Test board input current, 50 mA/Div Figure 4. Regulator Response to Step Load 6 AN-1346 LM5070 "HE" Evaluation Board SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Performance Characteristics www.ti.com 12.4 Ripple Voltage and Currents 2 3 1 Horizontal resolution: 2 Ps/Div. Trace 1: Output voltage, AC coupled, 20 mV/Div. Trace 2: Input current, 100 mA/Div. Trace 3: Output current, AC coupled, 20 mA/Div. Figure 5. Ripple Currents and Voltages 12.5 Flyback Transformer Waveforms 2 1 Horizontal resolution: 0.5 Ps/Div. Trace 1: Drain of synchronous rectifier MOSFET, Q3, 10 V/Div. Trace 2: Drain of main flyback MOSFET, Q1, 20 V/Div. Figure 6. Flyback Transformer Waveforms SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback AN-1346 LM5070 "HE" Evaluation Board Copyright © 2004–2013, Texas Instruments Incorporated 7 Schematic www.ti.com 13 Schematic 8 AN-1346 LM5070 "HE" Evaluation Board SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Bill of Materials www.ti.com 14 Bill of Materials Table 1. Bill of Materials Reference Part Value Mfr. Part Number Description C1 2.2µF, 100V C4532X7R2A225M CAP, CER, 2.2µF, 100V, X7R, 20%, 1812, TDK C2 2.2µF, 100V C4532X7R2A225M CAP, CER, 2.2µF, 100V, X7R, 20%, 1812, TDK C3 22µF, 63V EEV-HA1J220P C4 0.1µF, 100V C3212X7R1H104K CAP, CER, 0.1µF, 100V, X7R, 10%, 1206, TDK C5 0.22µF, 16V C2012X7R1C224K CAP, CER, 0.22µF, 16V, X7R, 10%, 0805, TDK C6 0.1µF, 100V C3212X7R1H104K CAP, CER, 0.1µF, 100V, X7R, 10%, 1206, TDK C7 0.047µF, 50V C2012X7R1H473K CAP, CER, 0.047µF, 500V, X7R, 10%, 0805, TDK C8 0.1µF, 50V C2012X7R1H104K CAP, CER, 0.1µF, 50V, X7R, 10%, 0805, TDK C9 4.7µF, 16V C3212X7R1C475M CAP, CER, 4.7µF, 16V, X7R, 20%, 1206, TDK C10 1000pF, 50V C2012COG2A102J CAP, CER, 1000PF, 100V, C0G, 5%, 0805, TDK C11 0.47µF, 25V C2012X7R1E474K CAP, CER, 0.47µF, 25V, X7R, 10%, 0805, TDK C12 0.47µF, 25V C2012X7R1E474K CAP, CER, 0.47µF, 25V, X7R, 10%, 0805, TDK C13 470pF, 50V C2012COG1H471J CAP, CER, 470PF, 50V, C0G, 5%, 0805, TDK C14 47µF, 10V C4532X5R1A476M CAP, CER, 47µF, 10V, X7R, 20%, 1812, TDK C15 330µF, 4V A700X337M0004AT CAP, AL ORGANIC, 330µF, 4V, 3018, KEMET C16 47µF, 10V C4532X5R1A476M CAP, CER, 47µF, 10V, X7R, 20%, 1812, TDK C17 0.47µF, 25V C2012X7R1E474K CAP, CER, 0.47µF, 25V, X7R, 10%, 0805, TDK C18 1000pF, 50V C2012COG1H102J CAP, CER, 1000PF, 100V, C0G, 5%, 0805, TDK C19 0.1µF, 50V C2012X7R1H104K CAP, CER, 0.1µF, 50V, X7R, 10%, 0805, TDK C20 4700pF, 100V C2012COG2A472J CAP, CER, 4700PF, 100V, C0G, 5%, 0805, TDK C21 0.01µF, 50V C2012X7R1H103K CAP, CER, 0.01µF, 50V, X7R, 10%, 0805, TDK C22 0.1µF, 50V C2012X7R1H104K CAP, CER, 0.1µF, 50V, X7R, 10%, 0805, TDK D1 1A, 200V CRH01 DIODE, ULTRAFAST, 1A, 200V, SOD-123, TOSHIBA D2 1A, 200V CRH01 DIODE, ULTRAFAST, 1A, 200V, SOD-123, TOSHIBA D3 300mA, 100V CMPD2838E DIODE, DUAL CC, 300mA, 100V, SOT-23, CENTRAL SEMI D4 300mA, 100V CMPD2838E DIODE, DUAL CC, 300mA, 100V, SOT-23, CENTRAL SEMI D5 300mA, 30V BAT54S CAP, AL ELEC, 22µF, 63V, PANASONIC DIODE, SCHOTTKY, DUAL SERIES, 300mA, 30V, SOT-23, DIODES INC L1 FERRITE BEAD, 7mΩ, 6A FC FB MJ4516HS720NT Q1 150V, 4.8A Si7898DP Q2 20V, 2.4A Si2301BDS Q3 30V, 25A Si7892 Q4 20V, 2.4A Si2301BDS R1 10 CRCW120610R0F R2 590K CRCW08055903F100 RESISTOR, TFILM, 590K, 1/10W, 1%, 0805, VISHAY R3 33.2K CRCW08053322F100 RESISTOR, TFILM, 33.2K, 1/10W, 1%, 0805, VISHAY R4 1.00K CRCW08051001F100 RESISTOR, TFILM, 1.00K, 1/10W, 1%, 0805, VISHAY R5 24.9K CRCW08052492F100 RESISTOR, TFILM, 24.9K, 1/10W, 1%, 0805, VISHAY R6 N/A N/A R7 100 CRCW08051000F100 SNVA094C – November 2004 – Revised May 2013 Submit Documentation Feedback FERRITE, 6A, 7mΩ, 1806, TAIYO YUDEN MOSFET, N-CH, 150V, 4.8A, PWR SO8, VISHAY MOSFET, P-CH, 20V, 2.4A, SOT-23, VISHAY MOSFET, N-CH, 30V, 25A, PWR SO8, VISHAY MOSFET, P-CH, 20V, 2.4A, SOT-23, VISHAY RESISTOR, TFILM, 10Ω, 1/8W, 1%, 1206, VISHAY N/A RESISTOR, TFILM, 100Ω, 1/10W, 1%, 0805, VISHAY AN-1346 LM5070 "HE" Evaluation Board Copyright © 2004–2013, Texas Instruments Incorporated 9 Bill of Materials www.ti.com Table 1. Bill of Materials (continued) 10 Reference Part Value Mfr. Part Number R8 0.15 WSL1206 0.15